)]}'
{
  "log": [
    {
      "commit": "775ef49bad8e8d9d02fc5968858dce6a00a78475",
      "tree": "eb61ed86fcaa5c168b1bbb301c931179f107b7e7",
      "parents": [
        "e03864e99f5ab0e27a48a17275122ad8f324b615"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Tue Nov 04 17:43:11 2014 +0000"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Tue Nov 04 17:43:11 2014 +0000"
      },
      "message": "Fix store instructions to large frames in ARM opt. compiler.\n\nWhen accessing a stack frame at a large offset, use an\nadditional core register (R5 or R6) as a temporary register\nwhenever IP contains the value to store (and thus cannot be\nused by art::Thumb2Assembler::StoreToOffset as a temporary\nregister to compute the memory address where the value is\nto be stored).  The previous value of R5 (or R6) is saved\non the stack before the emission of the store instruction\nand restored afterwards.\n\nChange-Id: Ic5fd5ab2c09d8327dd1f0f241d40d2c397ce64cd\n"
    }
  ]
}