)]}'
{
  "log": [
    {
      "commit": "77a48ae01bbc5b05ca009cf09e2fcb53e4c8ff23",
      "tree": "780c7d6bdee784c2f8248979de348491cfb63b34",
      "parents": [
        "659562aaf133c41b8d90ec9216c07646f0f14362"
      ],
      "author": {
        "name": "David Brazdil",
        "email": "dbrazdil@google.com",
        "time": "Tue Sep 15 12:34:04 2015 +0000"
      },
      "committer": {
        "name": "David Brazdil",
        "email": "dbrazdil@google.com",
        "time": "Tue Sep 15 12:34:04 2015 +0000"
      },
      "message": "Revert \"Revert \"ART: Register allocation and runtime support for try/catch\"\"\n\nThe original CL triggered b/24084144 which has been fixed\nby Ib72e12a018437c404e82f7ad414554c66a4c6f8c.\n\nThis reverts commit 659562aaf133c41b8d90ec9216c07646f0f14362.\n\nChange-Id: Id8980436172457d0fcb276349c4405f7c4110a55\n"
    },
    {
      "commit": "659562aaf133c41b8d90ec9216c07646f0f14362",
      "tree": "be1beae390262bf2f5a17bfa44de93081a849d07",
      "parents": [
        "b022fa1300e6d78639b3b910af0cf85c43df44bb"
      ],
      "author": {
        "name": "David Brazdil",
        "email": "dbrazdil@google.com",
        "time": "Mon Sep 14 21:26:33 2015 +0000"
      },
      "committer": {
        "name": "David Brazdil",
        "email": "dbrazdil@google.com",
        "time": "Mon Sep 14 21:26:33 2015 +0000"
      },
      "message": "Revert \"ART: Register allocation and runtime support for try/catch\"\n\nBreaks libcore test org.apache.harmony.security.tests.java.security.KeyStorePrivateKeyEntryTest#testGetCertificateChain. Need to investigate.\n\nThis reverts commit b022fa1300e6d78639b3b910af0cf85c43df44bb.\n\nChange-Id: Ib24d3a80064d963d273e557a93469c95f37b1f6f\n"
    },
    {
      "commit": "b022fa1300e6d78639b3b910af0cf85c43df44bb",
      "tree": "780c7d6bdee784c2f8248979de348491cfb63b34",
      "parents": [
        "e481c006e8b055a31d9c7cff27f4145e57e3c113"
      ],
      "author": {
        "name": "David Brazdil",
        "email": "dbrazdil@google.com",
        "time": "Thu Aug 20 17:47:48 2015 +0100"
      },
      "committer": {
        "name": "David Brazdil",
        "email": "dbrazdil@google.com",
        "time": "Mon Sep 14 20:42:58 2015 +0100"
      },
      "message": "ART: Register allocation and runtime support for try/catch\n\nThis patch completes a series of CLs that add support for try/catch\nin the Optimizing compiler. With it, Optimizing can compile all\nmethods containing try/catch, provided they don\u0027t contain catch loops.\nFuture work will focus on improving performance of the generated code.\n\nSsaLivenessAnalysis was updated to propagate liveness information of\ninstructions live at catch blocks, and to keep location information on\ninstructions which may be caught by catch phis.\n\nRegisterAllocator was extended to spill values used after catch, and\nto allocate spill slots for catch phis. Catch phis generated for the\nsame vreg share a spill slot as the raw value must be the same.\n\nLocation builders and slow paths were updated to reflect the fact that\nthrowing an exception may not lead to escaping the method.\n\nInstruction code generators are forbidden from using of implicit null\nchecks in try blocks as live registers need to be saved before handing\nover to the runtime.\n\nCodeGenerator emits a stack map for each catch block, storing locations\nof catch phis. CodeInfo and StackMapStream recognize this new type of\nstack map and store them separate from other stack maps to avoid dex_pc\nconflicts.\n\nAfter having found the target catch block to deliver an exception to,\nQuickExceptionHandler looks up the dex register maps at the throwing\ninstruction and the catch block and copies the values over to their\nrespective locations.\n\nThe runtime-support approach was selected because it allows for the\nbest performance in the normal control-flow path, since no propagation\nof catch phi values is necessary until the exception is thrown. In\naddition, it also greatly simplifies the register allocation phase.\n\nConstantHoisting was removed from LICMTest because it instantiated\n(now abstract) HConstant and was bogus anyway (constants are always in\nthe entry block).\n\nChange-Id: Ie31038ad8e3ee0c13a5bbbbaf5f0b3e532310e4e\n"
    },
    {
      "commit": "80afd02024d20e60b197d3adfbb43cc303cf29e0",
      "tree": "ef054c7b4f2a739f7cf063e0bc4c501c2c7e41b5",
      "parents": [
        "559b178e34c5d92e7932f92e5d8a981ac334606f"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue May 19 18:08:00 2015 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue May 26 15:59:02 2015 +0100"
      },
      "message": "ART: Clean up arm64 kNumberOfXRegisters usage.\n\nAvoid undefined behavior for arm64 stemming from 1u \u003c\u003c 32 in\nloops with upper bound kNumberOfXRegisters.\n\nCreate iterators for enumerating bits in an integer either\nfrom high to low or from low to high and use them for\n\u003carch\u003eContext::FillCalleeSaves() on all architectures.\n\nRefactor runtime/utils.{h,cc} by moving all bit-fiddling\nfunctions to runtime/base/bit_utils.{h,cc} (together with\nthe new bit iterators) and all time-related functions to\nruntime/base/time_utils.{h,cc}. Improve test coverage and\nfix some corner cases for the bit-fiddling functions.\n\nBug: 13925192\nChange-Id: I704884dab15b41ecf7a1c47d397ab1c3fc7ee0f7\n"
    },
    {
      "commit": "8826f67ad53099021f6442364348fa66729288d7",
      "tree": "3f937444d251efa09174ddb586c0eed6918907f6",
      "parents": [
        "ef4366a159ecdd357c98e577583bbe224d065128"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Apr 17 09:15:11 2015 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon May 18 10:22:45 2015 +0100"
      },
      "message": "Callee/caller save logic in register allocator.\n\nPrevent intervals that do not span a \u0027will-call\u0027 safepoint\nto allocate a callee-save register when caller-saves\nare available.\n\nChange-Id: I6e613ab54b087f433bbc433aa62847fbca423377\n"
    },
    {
      "commit": "8cbab3c4de3328b576454ce702d7748f56c44346",
      "tree": "8d95b5f6d451983350839a2b294b4bc869bd852a",
      "parents": [
        "b4186df6c48a88ad8028fcf9e1dac5ce6c391de2"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Apr 23 15:14:36 2015 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Apr 23 18:27:05 2015 +0100"
      },
      "message": "Linear scan: split at better  positions.\n\n- Split at block entry to piggy back on control flow resolution.\n- Split at the loop header, if the split position is within a loop.\n\nChange-Id: I718299a58c02ee02a1b22bda589607c69a35f0e8\n"
    },
    {
      "commit": "5b168deeae2c5a8a566ce5c140741f0e2227af21",
      "tree": "4a572dfc6932d1f478eae594801c59af11628ef8",
      "parents": [
        "b3665e3dfdd23cc7a2f17a0b53bb16205bf4151f"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Mar 27 10:27:22 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Mar 30 12:45:58 2015 +0100"
      },
      "message": "Fix user-build on fugu.\n\nCalling Delete on an array shifts the elements, so when iterating\nover inactives and removing entries we need to decrement for\nthe found interval, but also its potential other half. The code\nused to not decrement for the other half\n\nChange-Id: Idcb1533643c11a37ed4f459fe88aaef208a4bfd6\n"
    },
    {
      "commit": "234d69d075d1608f80adb647f7935077b62b6376",
      "tree": "f6b68ff38722dc91bd0de2387609ee0ce950e0ce",
      "parents": [
        "31df246d330c45f5691e226d176d0c59450f8435"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Mar 09 10:28:50 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Mar 11 14:23:38 2015 +0000"
      },
      "message": "Revert \"Revert \"[optimizing] Enable x86 long support.\"\"\n\nThis reverts commit 154552e666347d41d95d7619c6ee56249ff4feca.\n\nChange-Id: Idc726551c249a888b7ff5fde8508ae50e81b2e13\n"
    },
    {
      "commit": "154552e666347d41d95d7619c6ee56249ff4feca",
      "tree": "b8bdb820be33317f23ef1d3e43d13b2b6bfb3ba5",
      "parents": [
        "b4ba354cf8d22b261205494875cc014f18587b50"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Mar 06 16:10:14 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Mar 06 16:10:14 2015 +0000"
      },
      "message": "Revert \"[optimizing] Enable x86 long support.\"\n\nFew libcore failures.\n\nThis reverts commit b4ba354cf8d22b261205494875cc014f18587b50.\n\nChange-Id: I4a28d853e730dff9b69aec9555505803cf2fcd63\n"
    },
    {
      "commit": "b4ba354cf8d22b261205494875cc014f18587b50",
      "tree": "b6ce1e89f56f4d5adf238188df5b02fd7e2c23ac",
      "parents": [
        "af8db2ea18135588b267fe9a0b2f7af734b906cc"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Mar 05 11:28:58 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Mar 06 11:37:33 2015 +0000"
      },
      "message": "[optimizing] Enable x86 long support.\n\nChange-Id: I9006972a65a1f191c45691104a960366747f9d16\n"
    },
    {
      "commit": "7c3952f423b8213083d60596a5f0bf4237ca3f7b",
      "tree": "40cbc6d30e02ab5edd8598d0f811b62f5c6045ba",
      "parents": [
        "354d58ba776866ea7b1c71f0d0848d5aaa013ae3"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Thu Feb 19 18:21:24 2015 -0800"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Tue Feb 24 15:57:15 2015 -0800"
      },
      "message": "ART: Add -Wunused\n\nUntil the global CFLAGS are fixed, add Wunused. Fix declarations\nin the optimizing compiler.\n\nChange-Id: Ic4553f08e809dc54f3d82af57ac592622c98e000\n"
    },
    {
      "commit": "776b3184ee04092b11edc781cdb81e8ed60601e3",
      "tree": "98458c7087866b988468f5d356550ff14f2ee3af",
      "parents": [
        "1382e569b31f4fab61fcfca5aa93275a2a3cb757"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Feb 23 14:14:57 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Feb 23 14:56:07 2015 +0000"
      },
      "message": "Each primitive kind now spills to different locations.\n\nHaving different slots depending on the types greatly simplifies\nthe parallel move resolver. It also avoids doing FPU \u003c-\u003e Core\nregister swaps, and force backends to implement such a swap.\n\nChange-Id: Ide9f0452e7ccf9efb8adddbcc246d44b937b253c\n"
    },
    {
      "commit": "6c2dff8ff8e1440fa4d9e1b2ba2a44d036882801",
      "tree": "da2d48b3d84733ac6b29194cb2f624693a643d48",
      "parents": [
        "22c9285142169691eb2a9e2d4a49751fc7e57c2a"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 21 14:56:54 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 21 15:19:06 2015 +0000"
      },
      "message": "Revert \"Revert \"Fully support pairs in the register allocator.\"\"\n\nThis reverts commit c399fdc442db82dfda66e6c25518872ab0f1d24f.\n\nChange-Id: I19f8215c4b98f2f0827e04bf7806c3ca439794e5\n"
    },
    {
      "commit": "c399fdc442db82dfda66e6c25518872ab0f1d24f",
      "tree": "6f0841ad5e8e80b09e34e084ae8eac336bce73a2",
      "parents": [
        "41aedbb684ccef76ff8373f39aba606ce4cb3194"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 21 12:42:57 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 21 12:42:57 2015 +0000"
      },
      "message": "Revert \"Fully support pairs in the register allocator.\"\n\nLibcore tests fail.\n\nThis reverts commit 41aedbb684ccef76ff8373f39aba606ce4cb3194.\n\nChange-Id: I2572f120d4bbaeb7a4d4cbfd47ab00c9ea39ac6c\n"
    },
    {
      "commit": "41aedbb684ccef76ff8373f39aba606ce4cb3194",
      "tree": "94929237a0fe9b24dda7409d9433f07e82af4461",
      "parents": [
        "97c89e4c081dcf4bacbde70b6609e366c9da417e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 14 10:49:16 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 21 11:27:57 2015 +0000"
      },
      "message": "Fully support pairs in the register allocator.\n\nEnabled on ARM for longs and doubles.\n\nChange-Id: Id8792d08bd7ca9fb049c5db8a40ae694bafc2d8b\n"
    },
    {
      "commit": "6a5f5b25b3866966175859bc20216c5519d8b029",
      "tree": "b8d60df229a56e3931eaa0486f4451fe9818786d",
      "parents": [
        "ddcaf45db2874ffc37d2a8820e815db19a54c517",
        "dd8f887e81b894bc8075d8bacdb223747b6a8018"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jan 16 08:41:30 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Fri Jan 16 08:41:31 2015 +0000"
      },
      "message": "Merge \"Fix a bug in the register allocator.\""
    },
    {
      "commit": "dd8f887e81b894bc8075d8bacdb223747b6a8018",
      "tree": "2358f04f707177fc5b1a8463973ddd5f295d6e72",
      "parents": [
        "63991dd7c9bd68f23121e420c005628d7307cba3"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jan 15 15:37:37 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jan 16 08:37:59 2015 +0000"
      },
      "message": "Fix a bug in the register allocator.\n\nWhen allocating a register blocked by existing intervals,\nwe need to split inactive intervals at the end of their\nlifetime hole, and not at the next intersection. Otherwise,\nthe allocation for following intervals will not see\nthat a register is being used by the split interval.\n\nChange-Id: I40cc79dde541c07392a7cf4c6f0b291dd1ce1819\n"
    },
    {
      "commit": "f85a9ca9859ad843dc03d3a2b600afbaf2e9bbdd",
      "tree": "a802042fa7a3a8cb820916d558e630596daaa9b4",
      "parents": [
        "8fccea249b1a6f1469eeea42c2b2cca06ce1c70d"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Tue Jan 13 09:20:58 2015 -0500"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Thu Jan 15 11:21:37 2015 -0500"
      },
      "message": "[optimizing compiler] Compute live spill size\n\nThe current stack frame calculation assumes that each live register to\nbe saved/restored has the word size of the machine.  This fails for X86,\nwhere a double in an XMM register takes up 8 bytes.  Change the\ncalculation to keep track of the number of core registers and number of\nfp registers to handle this distinction.\n\nThis is slightly pessimal, as the registers may not be active at the\nsame time, but the only way to handle this would be to allocate both\nclasses of registers simultaneously, or remember all the active\nintervals, matching them up and compute the size of each safepoint\ninterval.\n\nChange-Id: If7860aa319b625c214775347728cdf49a56946eb\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "840e5461a85f8908f51e7f6cd562a9129ff0e7ce",
      "tree": "ea8b4cbc5a0e3dea96fefcd9247e6c06b17ac518",
      "parents": [
        "893e8881e31180721512c1b9e5ffacb03aad2e45"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 07 16:01:24 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jan 08 13:57:51 2015 +0000"
      },
      "message": "Implement double and float support for arm in register allocator.\n\nThe basic approach is:\n- An instruction that needs two registers gets two intervals.\n- When allocating the low part, we also allocate the high part.\n- When splitting a low (or high) interval, we also split the high\n  (or low) equivalent.\n- Allocation follows the (S/D register) requirement that low\n  registers are always even and the high equivalent is low + 1.\n\nChange-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797\n"
    },
    {
      "commit": "3e69f16ae3fddfd24f4f0e29deb106d564ab296c",
      "tree": "c796b1a2f71d4410af9fbdcb970b548a681f3955",
      "parents": [
        "776b880f66edb21cb3b4225877e494ec7a9ec1a2"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@arm.com",
        "time": "Wed Dec 10 10:36:50 2014 +0000"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@arm.com",
        "time": "Wed Dec 10 14:36:14 2014 +0000"
      },
      "message": "Opt compiler: Add arm64 support for register allocation.\n\nChange-Id: Idc6e84eee66170de4a9c0a5844c3da038c083aa7"
    },
    {
      "commit": "296bd60423e0630d8152b99fb7afb20fbff5a18a",
      "tree": "384aa7659763bb77a038a67c27f7cf6059632570",
      "parents": [
        "57b4d1c44e246dfd4aaef2d23b20a696a0c5e57e"
      ],
      "author": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Mon Oct 06 16:47:28 2014 -0700"
      },
      "committer": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Mon Nov 03 16:16:50 2014 -0800"
      },
      "message": "Some improvement to reg alloc.\n\nChange-Id: If579a37791278500a7e5bc763f144c241f261920\n"
    },
    {
      "commit": "102cbed1e52b7c5f09458b44903fe97bb3e14d5f",
      "tree": "cb0a433c8f284021298c8a0c4dd0da97ca9d198a",
      "parents": [
        "07f5c5edb7ef24ac35364e6ef9a8107a44e6564e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Oct 15 18:31:05 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Oct 21 16:03:51 2014 +0100"
      },
      "message": "Implement register allocator for floating point registers.\n\nAlso:\n- Fix misuses of emitting the rex prefix in the x86_64 assembler.\n- Fix movaps code generation in the x86_64 assembler.\n\nChange-Id: Ib6dcf6e7c4a9c43368cfc46b02ba50f69ae69cbe\n"
    },
    {
      "commit": "6f3dbbadf4ce66982eb3d400e0a74cb73eb034f3",
      "tree": "f7a20779e4d665f948c5fbcd26dac0071dafb8d4",
      "parents": [
        "2df6840f68dd18d7dd8dbf53f8b6181bbfdc4fc4"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Tue Oct 14 17:41:57 2014 -0700"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Thu Oct 16 19:27:28 2014 -0700"
      },
      "message": "Make ART compile with GCC -O0 again.\n\nTidy up InstructionSetFeatures so that it has a type hierarchy dependent on\narchitecture.\nAdd to instruction_set_test to warn when InstructionSetFeatures don\u0027t agree\nwith ones from system properties, AT_HWCAP and /proc/cpuinfo.\nClean-up class linker entry point logic to not return entry points but to\ntest whether the passed code is the particular entrypoint. This works around\nimage trampolines that replicate entrypoints.\nBug: 17993736\n\nChange-Id: I5f4b49e88c3b02a79f9bee04f83395146ed7be23\n"
    },
    {
      "commit": "740475d5f45b8caa2c3c6fc51e657ecf4f3547e5",
      "tree": "81196b753045fa16c13a4c1106031c1f28d9d233",
      "parents": [
        "13c4e8f4ef687f650aa76fb15ab12762d5a85602"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Sep 29 10:33:25 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Sep 29 11:04:07 2014 +0100"
      },
      "message": "Fix a bug in the insertion of parallel move.\n\nTo make sure we do not connect interval siblings in the\nsame parallel move, I added a new field in MoveOperands\nthat tells for which instruction this move is for.\nA parallel move should not contains moves for the same instructions.\n\nThe checks revealed a bug when connecting siblings, where\nwe would choose the wrong parallel move.\n\nChange-Id: I70f27ec120886745c187071453c78da4c47c1dd2\n"
    },
    {
      "commit": "3c04974a90b0e03f4b509010bff49f0b2a3da57f",
      "tree": "52649104e3e80272c3774793350f4d9f260ae732",
      "parents": [
        "c0d36abb12cdbb9469039c1dc153a586bd984015"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Sep 24 18:10:46 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Sep 25 12:23:40 2014 +0100"
      },
      "message": "Optimize suspend checks in optimizing compiler.\n\n- Remove the ones added during graph build (they were added\n  for the baseline code generator).\n- Emit them at loop back edges after phi moves, so that the test\n  can directly jump to the loop header.\n- Fix x86 and x86_64 suspend check by using cmpw instead of cmpl.\n\nChange-Id: I6fad5795a55705d86c9e1cb85bf5d63dadfafa2a\n"
    },
    {
      "commit": "3bca0df855f0e575c6ee020ed016999fc8f14122",
      "tree": "15e15c8290ad314c29ca608f51d89d4db68fd9ba",
      "parents": [
        "d41491adb23764f28a80cbb7f2bd7af6491cd892"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Sep 19 11:01:00 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Sep 23 13:57:30 2014 +0100"
      },
      "message": "Support for saving and restoring live registers in a slow path.\n\nAnd use it in suspend check slow paths.\n\nChange-Id: I79caf28f334c145a36180c79a6e2fceae3990c31\n"
    },
    {
      "commit": "aac0f39a3501a7f7dd04b2342c2a16961969f139",
      "tree": "ef71b73a7d95de726d36883e6c88f7c8cbcfaaf6",
      "parents": [
        "56369897d662ea63ea5ed57ae36af0ae0fa1452d"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Sep 16 14:11:14 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Sep 16 14:15:22 2014 +0100"
      },
      "message": "Fix a bug in the register allocator.\n\nWe need to take the live interval that starts first to know\nuntil when a register is free, instead of using the live interval\nthat is last in the inactive list.\n\nChange-Id: I2c9f87481ff1b4fc7b9948db7559b8d3b11d84ce\n"
    },
    {
      "commit": "3946844c34ad965515f677084b07d663d70ad1b8",
      "tree": "0d85bfba2ff69c34a2897351d1e50a1464509305",
      "parents": [
        "e2c23739c6395a83b30ece38f8a2e9e1bf7cf3ce"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Sep 02 15:17:15 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Sep 08 12:15:07 2014 +0100"
      },
      "message": "Runtime support for the new stack maps for the opt compiler.\n\nNow most of the methods supported by the compiler can be optimized,\ninstead of using the baseline.\n\nChange-Id: I80ab36a34913fa4e7dd576c7bf55af63594dc1fa\n"
    },
    {
      "commit": "93bedb7a96c8e6f9b6caa66689bf4f3c520bc234",
      "tree": "0f8cf8717de1ca9fa81b6517030d2ffa160377a1",
      "parents": [
        "b2a59010b787bd9d5d9bf36d32682faa5ad8da24"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jul 18 10:23:59 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jul 18 10:23:59 2014 +0100"
      },
      "message": "We can also run the linear scan register allocator on thumb.\n\nChange-Id: I5d21b5cbcdd93ff36342111de4ebcaab172034dd\n"
    },
    {
      "commit": "e63db27db913f1a88e2095a1ee8239b2bb9124e8",
      "tree": "893dee6783bca6717259321a6e4ba029c9c123e2",
      "parents": [
        "07b8441303ea82fca3cb85d71ecf8752d73cedd7"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Tue Jul 15 15:36:11 2014 -0700"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Tue Jul 15 17:07:49 2014 -0700"
      },
      "message": "Break apart header files.\n\nCreate libart-gtest for common runtime and compiler gtest routines.\nRename CompilerCallbacksImpl that is quick compiler specific.\nRename trace clock source constants to not use the overloaded profiler term.\n\nChange-Id: I4aac4bdc7e7850c68335f81e59a390133b54e933\n"
    },
    {
      "commit": "412f10cfed002ab617c78f2621d68446ca4dd8bd",
      "tree": "bbd9dddd0436da566365ada5deb1840e315e1b11",
      "parents": [
        "d6ab04646d8eec6f24b200f8649f3d942d9ad17e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 19 10:00:34 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jul 02 16:00:32 2014 +0100"
      },
      "message": "Support longs in the register allocator for x86_64.\n\nChange-Id: I7fb6dfb761bc5cf9e5705682032855a0a70ca867\n"
    },
    {
      "commit": "ecb2f9ba57b08ceac4204ddd6a0a88a0524f8741",
      "tree": "0285f887316bc4bb00810bbab1f508a6d2a2df5b",
      "parents": [
        "799605088f51dace7fddaf8493c8c6f3090fdaf6"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jun 13 08:59:59 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Jun 16 09:35:09 2014 +0100"
      },
      "message": "Enable the register allocator on x86_64.\n\nAlso fix an x86_64 assembler bug for movl.\n\nChange-Id: I8d17c68cd35ddd1d8df159f2d6173a013a7c3347\n"
    },
    {
      "commit": "e27f31a81636ad74bd3376ee39cf215941b85c0e",
      "tree": "12dd6a1153b78b831c887f65f0bcef715e89719d",
      "parents": [
        "dfc2091d2fb8a7694f69acf8bd39ce4953e026c2"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 12 17:53:14 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 12 18:05:00 2014 +0100"
      },
      "message": "Enable the register allocator on ARM.\n\n- Also fixes a few bugs/wrong assumptions in code not hit by x86.\n- We need to differentiate between moves due to connecting siblings within\n  a block, and moves due to control flow resolution.\n\nChange-Id: Idd05cf138a71c8f36f5531c473de613c0166fe38\n"
    },
    {
      "commit": "86dbb9a12119273039ce272b41c809fa548b37b6",
      "tree": "a4626e21ae16a9a5e133ea3e5e95b58d2ea4d8e5",
      "parents": [
        "c936622863a50bdda9b10062515dfc02a8c8b652"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jun 04 11:12:39 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 12 10:02:06 2014 +0100"
      },
      "message": "Final CL to enable register allocation on x86.\n\nThis CL implements:\n1) Resolution after allocation: connecting the locations\n   allocated to an interval within a block and between blocks.\n2) Handling of fixed registers: some instructions require\n   inputs/output to be at a specific location, and the allocator\n   needs to deal with them in a special way.\n3) ParallelMoveResolver::EmitNativeCode for x86.\n\nChange-Id: I0da6bd7eb66877987148b87c3be6a983b4e3f858\n"
    },
    {
      "commit": "31d76b42ef5165351499da3f8ee0ac147428c5ed",
      "tree": "4f9cf307923c72f73e4a814662a26406f155c38c",
      "parents": [
        "7eb3fa1e03b070c55ecbc814e2e3ae4409cf7b1e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Jun 09 15:02:22 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Jun 10 10:48:50 2014 +0100"
      },
      "message": "Plug code generator into liveness analysis.\n\nAlso implement spill slot support.\n\nChange-Id: If5e28811e9fbbf3842a258772c633318a2f4fafc\n"
    },
    {
      "commit": "a7062e05e6048c7f817d784a5b94e3122e25b1ec",
      "tree": "a5d6b64ae6d5352f761fc2547bda863281adbe40",
      "parents": [
        "8b5b1e5593ffa77c393e4172b71a3d5a821d2ed8"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu May 22 12:50:17 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon May 26 11:31:38 2014 +0100"
      },
      "message": "Add a linear scan register allocator to the optimizing compiler.\n\nThis is a \"by-the-book\" implementation. It currently only deals\nwith allocating registers, with no hint optimizations.\n\nThe changes remaining to make it functional are:\n- Allocate spill slots.\n- Resolution and placements of Move instructions.\n- Connect it to the code generator.\n\nChange-Id: Ie0b2f6ba1b98da85425be721ce4afecd6b4012a4\n"
    }
  ]
}