)]}' { "log": [ { "commit": "8cf9cb386cd9286d67e879f1ee501ec00d72a4e1", "tree": "88e86e214b425e444760fe4e0ffeee677e1558a2", "parents": [ "914b7b6a6c9f399b26b41e9160e9871ef749e0db" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jul 19 09:28:38 2017 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Jul 24 16:07:10 2017 -0700" }, "message": "ART: Include cleanup\n\nLet clang-format reorder the header includes.\n\nDerived with:\n\n* .clang-format:\n BasedOnStyle: Google\n IncludeIsMainRegex: \u0027(_test|-inl)?$\u0027\n\n* Steps:\n find . -name \u0027*.cc\u0027 -o -name \u0027*.h\u0027 | xargs sed -i.bak -e \u0027s/^#include/ #include/\u0027 ; git commit -a -m \u0027ART: Include cleanup\u0027\n git-clang-format -style\u003dfile HEAD^\n manual inspection\n git commit -a --amend\n\nTest: mmma art\nChange-Id: Ia963a8ce3ce5f96b5e78acd587e26908c7a70d02\n" }, { "commit": "4147fcc43c2ee019a06e55384985e3eaf82dcb8c", "tree": "11ec92efbfddf7736bbc74ed35fcfb3756bfcfb0", "parents": [ "e8f48da635c4d07bbe431e5819da8e1fad91a8ef" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sat Jun 17 19:57:27 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Jul 19 15:03:10 2017 -0700" }, "message": "MIPS: Reduce Baker read barrier code size overhead\n\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-gtest\nTest: testrunner.py --target --optimizing\nTest: same tests as above on CI20\nTest: booted MIPS32 and MIPS64 in QEMU with poisoning\n in configurations:\n - with Baker read barrier thunks\n - without Baker read barrier thunks\n - ART_READ_BARRIER_TYPE\u003dTABLELOOKUP\n\nChange-Id: I79f320bf8862a04215c76cfeff3118ebc87f7ef2\n" }, { "commit": "24ff0235ab631baccd49fb491197d86d1ef97279", "tree": "d999768a0cf955044a4a771fa802b30034dee234", "parents": [ "252eda65ae216ff36a4eca2195d1ec3b29612035", "c043d006845afef99b17aeab8bb6d6da1a42ad37" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 18 09:54:47 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jul 18 09:54:47 2017 +0000" }, "message": "Merge \"Remove the old ARM assemblers from ART.\"" }, { "commit": "93764b8ee58d54118904b8f4473628451e568893", "tree": "729758b4420920b7bb7070dbdac1ecd86810b2a8", "parents": [ "d317295ed07384c69d5890d6b17b80d57139a082" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Mon Jul 17 14:51:53 2017 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Mon Jul 17 18:01:17 2017 -0700" }, "message": "Generalize atomic_method_ref_map to support dex references\n\nGeneralize atomic method ref map to support dex references instead\nof only method references.\n\nThe goal is to use this in a future CL to replace compiled_classes_.\n\nTest: test-art-host\n\nChange-Id: Ic6d1e619584f790eea68f5160fa0fcd664524cd7\n" }, { "commit": "c043d006845afef99b17aeab8bb6d6da1a42ad37", "tree": "756ce3caca2a7ff62a169c003639657bd7124d2f", "parents": [ "9983e302384c12a975c8d2d5ae239f79fd8e1996" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jul 14 16:39:16 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jul 17 18:00:40 2017 +0100" }, "message": "Remove the old ARM assemblers from ART.\n\nNow that the old ARM code generator for ART\u0027s Optimizing\ncompiler is gone, these assemblers no longer have users;\nretiring them.\n\nTest: test.py\nBug: 63316036\nChange-Id: Iaea42432a9e0d3288b71615f85c58846c0336944\n" }, { "commit": "9983e302384c12a975c8d2d5ae239f79fd8e1996", "tree": "4e4d269fe1a3d4f0f1b93cd972adab9f17aab8e0", "parents": [ "bac2bd1c2fbdd94f4d4dfe83d8451f655e875e36" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jul 14 14:34:22 2017 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jul 14 17:25:39 2017 +0100" }, "message": "Remove the old ARM code generator from ART\u0027s Optimizing compiler.\n\nThe AArch32 VIXL-based code generator has been the default\nARM code generator in ART for some time now. The old ARM\ncode generator does not compile anymore; retiring it.\n\nTest: test.py\nBug: 63316036\nChange-Id: Iab8fbc4ac73eac2c1a809cd7b22fec6b619755db\n" }, { "commit": "bac2bd1c2fbdd94f4d4dfe83d8451f655e875e36", "tree": "58ba3b1d28348da478a44234820ab6c485f5ed37", "parents": [ "06410c093de2b8a21bdbd7dfd9ce324fd4e95c3f", "6d729a789d3d7771e13d9445ee0be1d9d48a81b5" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jul 14 10:28:42 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jul 14 10:28:42 2017 +0000" }, "message": "Merge \"Introduce a Marking Register in ARM code generation.\"" }, { "commit": "6d729a789d3d7771e13d9445ee0be1d9d48a81b5", "tree": "360b9af68920f411be5fe6753aaf7ab4976385ea", "parents": [ "8cfbbb826a3ab7bb680cfcd8a8148570b165d620" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jun 30 18:34:01 2017 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jul 13 16:41:07 2017 +0100" }, "message": "Introduce a Marking Register in ARM code generation.\n\nWhen generating code for ARM, maintain the status of\nThread::Current()-\u003eGetIsGcMarking() in register R8,\ndubbed MR (Marking Register), and check the value of that\nregister (instead of loading and checking a read barrier\nmarking entrypoint) in read barriers.\n\nTest: m test-art-target\nTest: m test-art-target with tree built with ART_USE_READ_BARRIER\u003dfalse\nTest: m test-art-host-gtest\nTest: ARM device boot test\nBug: 37707231\nChange-Id: I30b44254460d0bbb9f1b2adc65eca52ca3de3f53\n" }, { "commit": "51765b098301fff1897361b2d1a21af356d9d6d8", "tree": "5d35468c9ecd428803fe7e4339fb8e251b6ed926", "parents": [ "e63a91111d13f33028c2988ded53a4659140ca2e" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Thu Jun 22 13:49:59 2017 +0200" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Thu Jul 13 10:34:27 2017 +0200" }, "message": "MIPS32: ART Vectorizer\n\nMIPS32 implementation which uses MSA extension.\n\nNote: Testing is done with checker parts of tests 640, 645, 646 and\n 651, locally changed to cover MIPS32 cases. These changes can\u0027t\n be included in this patch since MSA is not a default option.\n\nTest: ./testrunner.py --target --optimizing -j1 in QEMU (mips32r6)\nChange-Id: Ieba28f94c48c943d5444017bede9a5d409149762\n" }, { "commit": "97c46466aea25ab63a99b3d1afc558f0d9f55abb", "tree": "afd225f51d28a77329bc2590a025400e088f260c", "parents": [ "00cca3a275562d110a8b35094b9b12fac37f67ab" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu May 11 14:04:03 2017 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jul 11 17:43:27 2017 +0100" }, "message": "Introduce a Marking Register in ARM64 code generation.\n\nWhen generating code for ARM64, maintain the status of\nThread::Current()-\u003eGetIsGcMarking() in register X20,\ndubbed MR (Marking Register), and check the value of that\nregister (instead of loading and checking a read barrier\nmarking entrypoint) in read barriers.\n\nTest: m test-art-target\nTest: m test-art-target with tree built with ART_USE_READ_BARRIER\u003dfalse\nTest: ARM64 device boot test\nBug: 37707231\nChange-Id: Ibe9bc5c99a2176b0a0476e9e9ad7fcc9f745017b\n" }, { "commit": "2e0a7e5047fde08ddd220aaa1a0e64d44ecbb420", "tree": "7c541176dc1b44cc927272f9b38fab4ce7ac9e85", "parents": [ "209b4c7141d7da61790844cd58bd0a9bab2951d8" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Thu Jul 06 11:55:24 2017 +0200" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Thu Jul 06 14:04:01 2017 +0200" }, "message": "MIPS32: Adds changes neccessary for saving 128 bits of data\n\nTest: mma test-art-host-gtest\nTest: ./testrunner.py --optimizing --target in QEMU (MIPS)\n\nChange-Id: I90b7baa1d5f910887bcc3ab80a1a48391ba80c45\n" }, { "commit": "69489fad1e34c005fbe110bfae2a3c6bff879d4e", "tree": "23c50305c52cf076cedd3bfd496a2adf0d1e46b3", "parents": [ "8979f71079ec18fa8d3c0915549ec03ee1fbadf5" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jun 08 18:03:25 2017 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jun 21 21:30:59 2017 -0700" }, "message": "ART: Fix old warnings\n\nFix Wconstant-conversion warnings.\n\nPartially reverts commit df53be273509dd43725870fb20a2c7d71f7fbfd3.\n\nBug: 28149048\nBug: 29823425\nTest: m\nTest: m test-art-host\nChange-Id: Ib377150690c0f2c2142e4b91f2144e2bcaa020ef\n" }, { "commit": "c0fe9db1af30a162448ca5ccd386e970a8d31f83", "tree": "6dbb5549f249b61337f1e70f1911ea1902d2d8fa", "parents": [ "53ac3130edd9c9273f95e3ba0bc5e80f6d2b3f2d", "82b0740f03b1a6acab4558214d3edc362e27e238" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 12 09:09:09 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jun 12 09:09:11 2017 +0000" }, "message": "Merge \"Use IntrusiveForwardList\u003c\u003e for Env-/UsePosition.\"" }, { "commit": "58794c5c23f46a7476a58e5a10dbeebb6321aa90", "tree": "948368dd8d8376a50fe996da0438abe10da1322d", "parents": [ "73321bfdd7e96e3ce62042c9e5be567ed0db1985", "5678db5b3a0275d04bc610236f89fac9f76b5b1e" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Jun 09 18:00:41 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jun 09 18:00:43 2017 +0000" }, "message": "Merge \"ART: Refactor bit_utils and stl_util\"" }, { "commit": "05ae67444e15c9281582ef1fc45c4558d286040e", "tree": "c4c1bb45e81be3367dbfb36af1646f9a5d434078", "parents": [ "ca333f4093648f275b71121121a7c72f99fc11af", "0758ae7c12df9f857b8609e1eab6ad5dfa0e517d" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Jun 09 16:07:38 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jun 09 16:07:40 2017 +0000" }, "message": "Merge \"Introduce a number of MSA instructions for MIPS32\"" }, { "commit": "5678db5b3a0275d04bc610236f89fac9f76b5b1e", "tree": "efc4ffe5d59a0c6c5f4c15a886459962d24de4aa", "parents": [ "83b140474aa1759739c8ee4464bf226c4fa0f6d7" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jun 08 14:11:18 2017 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jun 08 14:11:18 2017 -0700" }, "message": "ART: Refactor bit_utils and stl_util\n\nMove iterator code from bit_utils.h into bit_utils_iterator.h. Move\nIdentity into stl_util_identity.h. Remove now unnecessary includes,\nand fix up transitive users.\n\nTest: m\nChange-Id: Id1ce9cda66827c5d00584f39ed310b6b37629906\n" }, { "commit": "3b7dc35f4e5c4d86c73b6784b7ee0df701c68ec2", "tree": "1e3a56846ec63148142ac6fb1fef214129f4a05e", "parents": [ "8228cdf4ad6322ec8133564aaa51f966d36c0f17" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jun 06 20:02:03 2017 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jun 08 13:13:20 2017 -0700" }, "message": "ART: Clean up allocator.h\n\nMove the single-use typedefs to their users. Remove now-unused\nincludes. Fix up transitive includes.\n\nTest: m\nChange-Id: I953d774b28f1e4f3191f96943e3a69ce66aa398a\n" }, { "commit": "0758ae7c12df9f857b8609e1eab6ad5dfa0e517d", "tree": "cbceef23999bd640e36c052ce2accbab0a81dc22", "parents": [ "4d3df9131c4098828f889b9470c82880efdc91be" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Tue May 23 11:06:23 2017 +0200" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Thu Jun 08 10:56:46 2017 +0200" }, "message": "Introduce a number of MSA instructions for MIPS32\n\nAdded a number of MSA (The MIPS SIMD Architecture) instructions.\nAdded assembler tests for each instruction.\n\nTest: mma test-art-host-gtest\n\nChange-Id: I1d499309fc08923484f64d1883b9c3f95eadd3be\n" }, { "commit": "658263ec2fdc7758dd73c41cdcf0babcdef1e48d", "tree": "493f3cb75d9d856aaade47dd2d008756f9e488a5", "parents": [ "11d72c608e0565fabcf6b2d6c13fbc85c560a608" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Jun 07 09:35:53 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Jun 07 09:41:42 2017 +0200" }, "message": "MIPS64: Add min/max MSA instructions\n\nAdded min_s.df, max_s.df, min_u.df, max_u.df, fmin.df and fmax.df MSA\ninstructions in assembler, disassembler and tests.\n\nThese instructions are needed for min/max support in ART Vectorizer.\n\nTest: mma test-art-host-gtest\nChange-Id: I4e8dd18ca501ac09d938a49388e4a43116660ec9\n" }, { "commit": "36a5d0c3c46a75381f303a0a468eaefe1ac3c982", "tree": "94ea290524323aedc1f0d00e233ab84207507aa2", "parents": [ "0a50965275df2da590c49a7a955e6ff5a7c7d2ae", "19680d3655433e98582983ed0a6d44d6b4822951" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Jun 05 16:59:25 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jun 05 16:59:28 2017 +0000" }, "message": "Merge \"MIPS64: ART Vectorizer\"" }, { "commit": "b486a98aadc95d80548953410cf23edba62259fa", "tree": "b113b7d50a4a015502873b7742c9ece00d293e84", "parents": [ "1656ca9e6996cb555b4463e5efd4bd7e3f4fb816" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jun 01 13:45:54 2017 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Jun 02 08:24:02 2017 -0700" }, "message": "ART: Introduce thread-current-inl.h\n\nFactor out Thread::Current() code into its own -inl file to remove\ntransitive includes.\n\nThis requires at the same time correcting mutex.h, i.e., moving\nsome functions into mutex-inl.h.\n\nTest: m test-art-host\nChange-Id: I88f888b604e0897368d9b483edce6ce4332dd9c9\n" }, { "commit": "82b0740f03b1a6acab4558214d3edc362e27e238", "tree": "c19ec7ad047fbbef0c0f4dcd46905604b75841b5", "parents": [ "8144b1ebea42feaa798419eaf53a6bbbf37822a9" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Mar 01 19:02:04 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jun 01 20:37:10 2017 +0100" }, "message": "Use IntrusiveForwardList\u003c\u003e for Env-/UsePosition.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nChange-Id: I2b720e2ed8f96303cf80e9daa6d5278bf0c3da2f\n" }, { "commit": "deae7db5864fa50c5a1cd6c232a17aeb986b36e1", "tree": "cdedad3d0f921e4f82fa7b65d55820455b7ac0ea", "parents": [ "8d01c3708c4becb186979ed9377aed0fc2954d06" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue May 30 09:56:41 2017 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue May 30 14:15:50 2017 -0700" }, "message": "ART: Add missing namespace comments\n\nAdd closing namespace comments.\n\nBug: 32619234\nTest: m\nChange-Id: I1f50e09dcd1038c4b540b87e5c19e319c1f592e4\n" }, { "commit": "19680d3655433e98582983ed0a6d44d6b4822951", "tree": "15113506e75b1480c5c1d3cfdf9df4480f30eae8", "parents": [ "0a5ace58e973da278049f837bf2cdbaf7b44849c" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu May 11 10:38:36 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Mon May 29 17:57:39 2017 +0200" }, "message": "MIPS64: ART Vectorizer\n\nMIPS64 implementation which uses MSA extension. Also extended all\nrelevant checker tests to test MIPS64 implementation.\n\nTest: booted MIPS64R6 in QEMU\nTest: ./testrunner.py --target --optimizing -j1 in QEMU\n\nChange-Id: I8b8a2f601076bca1925e21213db8ed1d41d79b52\n" }, { "commit": "dbddc22f5dc2d1ff4d4783fbd66c27812f4980d1", "tree": "2a0a8efa1c2630e57ab48ab2de171f2847ff282f", "parents": [ "a559fa1b0d6c276dde2cdc707de1acd4950f7190" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed May 24 12:04:13 2017 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Thu May 25 16:59:44 2017 -0700" }, "message": "Refactor profiles to use TypeReference instead of ClassReference\n\nRefactor type reference into runtime and use it for profiles.\nClassReference was just duplicated code since it wasn\u0027t even using\nthe class def indexes.\n\nTest: test-art-host\n\nBug: 62040831\nChange-Id: Ia92f21c0e85c00321f52c97bb7a90158d882849b\n" }, { "commit": "47aa869c1600b349de716f6990de0f431ce558a9", "tree": "2ca9a3b1919caef73f9ed810048adab331307858", "parents": [ "e74e120dbd3243ae6f43db6fd91ec201f96ef5ea", "365719c23d809e595cf320bfba40e76bb4e87940" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed May 17 14:02:58 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed May 17 14:02:59 2017 +0000" }, "message": "Merge \"No need to lock when calling Thread.interrupted.\"" }, { "commit": "a1633a7077781d9c64a77b27deb1707d1a56906d", "tree": "505f2560cfd247b2e1aab86d3ab96e5c399cb05d", "parents": [ "a774575ae3af3d46955f941ddd08a79caf2aaa94", "c8e93c736c149ce41be073dd24324fb08afb9ae4" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue May 16 15:56:01 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue May 16 15:56:04 2017 +0000" }, "message": "Merge \"Min/max SIMDization support.\"" }, { "commit": "365719c23d809e595cf320bfba40e76bb4e87940", "tree": "0939f0d8dc47723978a665fa11dd637f6976d521", "parents": [ "d6705a0586377f1b0d7d14d3abe2b270bb0adb18" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 08 13:11:50 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue May 16 01:58:03 2017 +0100" }, "message": "No need to lock when calling Thread.interrupted.\n\nAlso intrinsify the Thread.interrupted call.\n\nThe rationale behind this optimization is that the flag can only\nhave two values, and only self can set it to false.\n\nTest: libcore, jdwp, run-tests, 050-sync-test\nChange-Id: I5c2b43bf872ba0bfafcb54b2cfcd19181864bc4c\n" }, { "commit": "c8e93c736c149ce41be073dd24324fb08afb9ae4", "tree": "8e7154cf1bbcee8f5837ee9cb930174e2516ac03", "parents": [ "92f4672f811a4eccdc596f7c2235804abd196fde" ], "author": { "name": "Aart Bik", "email": "ajcbik@ajcbik2.mtv.corp.google.com", "time": "Wed May 10 10:49:22 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon May 15 11:44:58 2017 -0700" }, "message": "Min/max SIMDization support.\n\nRationale:\nThe more vectorized, the better!\n\nTest: test-art-target, test-art-host\n\nChange-Id: I758becca5beaa5b97fab2ab70f2e00cb53458703\n" }, { "commit": "a152c4b160f5f296e55c545d37c29d17b4db2212", "tree": "5496a518583c525f04b5e490f0d7b82630ddb4ff", "parents": [ "54db2e2ff3a5520e75480f5ce2cf25b8dd37588c", "3837011236058617292bee831708449e5100c08c" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri May 12 23:46:13 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri May 12 23:46:15 2017 +0000" }, "message": "Merge \"MIPS64: Add ilvr.df MSA instructions\"" }, { "commit": "63529dd46f4a38f9c35c549399480c725beee884", "tree": "6d67e0788607f788910a503b10000d990463ce47", "parents": [ "f4afd9f34035a67f4f845fc8c273589da7a09adc", "d8b6a53074be7d6b98c651ed8d2127f089da39a6" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu May 11 16:15:45 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu May 11 16:15:47 2017 +0000" }, "message": "Merge \"MIPS64: Saves 128-bit vector registers along SuspendCheckSlowPath\"" }, { "commit": "3837011236058617292bee831708449e5100c08c", "tree": "1f9d72542f9309017433f3a1fe13a5a2dac4e000", "parents": [ "7e4f71f9014c5dc573b4dbbf7faefc4c72d5f55d" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed May 10 14:30:28 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu May 11 10:35:34 2017 +0200" }, "message": "MIPS64: Add ilvr.df MSA instructions\n\nThese instructions are needed for compressed string support\nin ART Vectorizer.\n\nTest: mma test-art-host-gtest\nChange-Id: I269473bb8bcce5aba72201380bb71860e5498d73\n" }, { "commit": "88abba2b0cb0151d89e16da3e64025878dc2f142", "tree": "231e5551a1b8d3c8bf162c9d0f30916b36ba2742", "parents": [ "b9c3a99096c746b09af611e55e11b86600374011" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 03 17:09:25 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 09 15:43:34 2017 +0100" }, "message": "ARM/AOT: Allow 16-bit LDR for Baker read barrier loads.\n\nTest: m test-art-target-gtest\nTest: testrunner.py --target on Nexus 6P.\nTest: testrunner.py --target on Nexus 6P with heap poisoning enabled.\nTest: Repeat the above tests with ART_USE_OLD_ARM_BACKEND\u003dtrue.\nBug: 29516974\nBug: 30126666\nBug: 36141117\nChange-Id: I458f2ec5fe9abead4db06c7595d992945096fb68\n" }, { "commit": "d8b6a53074be7d6b98c651ed8d2127f089da39a6", "tree": "f0780307647818a97f041e62d31cc27fa4cc971a", "parents": [ "81c50bf31d9f9e35890404a2baf93f2c1e061ad9" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Apr 20 11:42:30 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Mon May 08 13:05:20 2017 +0200" }, "message": "MIPS64: Saves 128-bit vector registers along SuspendCheckSlowPath\n\nWe need to save 128 bits of data. This is only done for vector\nregisters that are live, so overhead is not too big.\n\nTest: mma test-art-host-gtest\nTest: ./testrunner.py --optimizing --target in QEMU (MIPS64)\n\nChange-Id: I2cdfeb8056dc5ef35c92f589d8c0399c41d913b2\n" }, { "commit": "eee1c0ec2b08a6be642b329dc2fe885391127da3", "tree": "960bb4df48b4a320df3c58682449abb24b5fb122", "parents": [ "c7cee403ad9a3f7097f5157a621a6a8cb991222e" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Apr 21 17:58:41 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri May 05 12:51:11 2017 +0100" }, "message": "ARM: Link-time generated thunks for Baker CC read barrier.\n\nRemaining work for follow-up CLs:\n - use implicit null check in field thunk,\n - use 16-bit LDRs for fields and GC roots.\n\nTest: m test-art-target-gtest\nTest: testrunner.py --target on Nexus 6P.\nTest: testrunner.py --target on Nexus 6P with heap poisoning enabled.\nTest: Repeat the above tests with ART_USE_OLD_ARM_BACKEND\u003dtrue.\nBug: 29516974\nBug: 30126666\nBug: 36141117\nChange-Id: Iad5addab72d790a9d61879f61f2e75b246bcdf5a\n" }, { "commit": "a57c334075b193de9690fff97acf6c1b1d1283fc", "tree": "3e1ddee842f9c4e78e957f9f6e655ff88ed9ff58", "parents": [ "5887c37b729e16bdef149d900ebc7c9a77a75cb3", "88307edcd5c35bd5f602b4c6b2464c2d4332753e" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Sat Apr 29 06:53:52 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Sat Apr 29 06:53:54 2017 +0000" }, "message": "Merge \"Fix up code warning and errors\"" }, { "commit": "88307edcd5c35bd5f602b4c6b2464c2d4332753e", "tree": "cb41c36536ae87483daa24b6fcf4381b9a5df15d", "parents": [ "18457f487316b2ed2dd584f3e1f07e939e18aef5" ], "author": { "name": "Yi Kong", "email": "yikong@google.com", "time": "Tue Apr 25 22:33:06 2017 -0700" }, "committer": { "name": "Yi Kong", "email": "yikong@google.com", "time": "Fri Apr 28 11:04:12 2017 -0700" }, "message": "Fix up code warning and errors\n\nDiscovered by new LLVM rebase.\n\nClean up, no functionality change.\n\nTest: build\nBug: 37752547\nChange-Id: I7df6097706e0772226dcb07611e7d044a6085421\n" }, { "commit": "80248d7ba4e952f0e0110c036b48963080ef9470", "tree": "887cbde7b310371d8ecba019cec0b2a1000e520a", "parents": [ "6d3c61d8c6d2f96dec8345263c948fae3caa4e1a" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Apr 20 11:55:47 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Apr 21 16:11:50 2017 +0200" }, "message": "MIPS64: Add add_a.df, ave_s/u.df and aver_s/u.df MSA instructions\n\nThese instructions are needed for implementing VecAbs and\nVecHalvingAdd visitors.\n\nTest: mma test-art-host-gtest\n\nChange-Id: Idaec03ea32bbeaba9cb7476dd0f740aa4d9cfa70\n" }, { "commit": "28a24b308f665de64c785e2590f9b23ec6ec25aa", "tree": "3e9f0779038cefbbae5581b5844ce742ea782f9b", "parents": [ "6bc7774426cc0b6bbab5566fa62b3c509455e583" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed Apr 19 23:54:33 2017 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed Apr 19 23:55:36 2017 -0700" }, "message": "Fix some gtests\n\nForgot to retest.\n\nTest: test-art-host-gtest\n\nChange-Id: I72b07c3872079452a3a01db4fbd2c4ee0060f294\n" }, { "commit": "5863f85483c8cc0f21adbd44698fa1018c72f9f7", "tree": "1587ea108c9d74b725b467983e0ac231aef70fc9", "parents": [ "89d424832002732983fa40df244a087e0dd21028" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Thu Mar 23 15:41:37 2017 -0700" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Wed Apr 12 22:09:12 2017 -0700" }, "message": "MIPS64: java.lang.System.arraycopy() for copying char[] to char[].\n\nTest: run-test --64 --no-prebuild --optimizing 011-array-copy\nTest: run-test --64 --no-prebuild 011-array-copy\nTest: run-test --64 --optimizing 011-array-copy\nTest: run-test --64 011-array-copy\nTest: ART_TEST_OPTIMIZING\u003dtrue test-art-target-run-test\nTest: booted MIPS64R6 emulator.\n\nChange-Id: I418571c639b2776869b3c8f3f67c09aadbb30133\n" }, { "commit": "cd0295d81b6d53bbade117a0531b2453e8cb7c7f", "tree": "eceada4e7329ce8fc2e993f414f515c186b81f10", "parents": [ "ef6787bd892b55588ebb2835cc3a3bc4e9e08d04" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Fri Mar 31 15:26:54 2017 -0700" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Mon Apr 10 10:19:30 2017 -0700" }, "message": "MIPS: Use Lsa/Dlsa when possible.\n\nFor MIPS32R6 replace instances of \"sll/addu\" to calculate the\naddress of an item in an array with \"lsa\". For other versions of\nMIPS32 use the \"sll/addu\" sequence. Encapsulate this logic in an\nassembler method to eliminate having a lot of statements like\n\"if (IsR6()) { ... } else { ... }\" scattered throughout the code.\n\nMIPS64 always supports R6. This means that all instances of\n\"dsll/daddu\" used to calculate the address of an item in an array\ncan be replaced by \"dlsa\" so there is no need to encapsulate\nconditional logic in a special method. The code can just emit\n\"dlsa\" directly.\n\nTest: mma -j2 ART_TEST_OPTIMIZING\u003dtrue test-art-target-run-test\nTested on MIPS32, and MIPS64 QEMU.\nTest: \"make test-art-target-gtest32\" on CI20 board.\nTest: \"cd art; test/testrunner/testrunner.py --target --optimizing --32\"\n on CI20 board.\n\nChange-Id: Ibe5facc1bc2a6a7a6584e23d3a48e163ae38077d\n" }, { "commit": "7cd18fb5a7ce83d98b1bbc3c55583fc5f93dc16f", "tree": "2aaab2ad3d40d9044d02a8818991f6845190e118", "parents": [ "674bc3c984b8e24e90e5e8dda20197005dbf8300", "8939c6474a34eb6d642db8fecb8b3a5c3194e464" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Apr 04 17:59:09 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Apr 04 17:59:14 2017 +0000" }, "message": "Merge \"SIMD pcmpgtb,w,d,q for x86/x86_64\"" }, { "commit": "8939c6474a34eb6d642db8fecb8b3a5c3194e464", "tree": "a0a2db32a5147416d796907a3977dd29e04e9328", "parents": [ "08ae45625d059891754e3c3ad63a5e6cae80b96b" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Apr 03 14:09:01 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Apr 04 09:15:45 2017 -0700" }, "message": "SIMD pcmpgtb,w,d,q for x86/x86_64\n\nRationale:\nEnables fast compare gt.\n\nTest: assembler_x86[_64]_test\nChange-Id: I0a069649480529f3fec2c2b100e2aaaa2cd79820\n" }, { "commit": "e2a239560959dafe08c499d61905b69c6f628c02", "tree": "bfc4889ebe0d83d4a6ccf6392708ff0d6c383e9e", "parents": [ "432fccc4c001fcd822f401aea1a4214b713bd896", "3f44403fb5b6c9c6176339ab5888e97d0b617746" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Apr 03 21:42:11 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Apr 03 21:42:13 2017 +0000" }, "message": "Merge \"MIPS64: Add ldi.df MSA instruction\"" }, { "commit": "67d3fd77d1572e46f537dea2fd4ded3ecfd7c202", "tree": "168e7ddf85cbe0710266dc501dac6d7717f25cf8", "parents": [ "5b92c48f99391ae764e1699a22881f9d5cbce721" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Mar 31 15:11:53 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Mar 31 15:11:53 2017 -0700" }, "message": "SIMD pavgb,w for x86/x86_64\n\nRationale:\nBreak-out CL of ART Vectorizer.\nEnables fast halving add with rounding\n\nBug: 34083438\nTest: assembler_x86[_64]_test\nChange-Id: I09173376b803d671a6b05a33e630f45f778cea52\n" }, { "commit": "3f44403fb5b6c9c6176339ab5888e97d0b617746", "tree": "765e3d3968b48fa5236177905fa57c5b60e57653", "parents": [ "bb75449355575a4b1ae72147b80cc7b225092149" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Mar 31 14:38:20 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Mar 31 14:38:55 2017 +0200" }, "message": "MIPS64: Add ldi.df MSA instruction\n\nAlso fixes RepeatTemplatedRegisterImmBits template.\n\nTest: mma test-art-host-gtest\n\nChange-Id: Ib23f8a65ba924623f8c3a2d75d4ec4491d18feb0\n" }, { "commit": "1595815c2a914a78df7dfb6f0082f47d4e82bb36", "tree": "8fd53c3c91158b33e744e43cc655b2e2a180a3fc", "parents": [ "4ba18fdfc2581a2328ab745c2707e3ed375d9e64" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Feb 09 19:08:30 2017 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Mar 28 23:35:34 2017 -0700" }, "message": "MIPS: Implement read barriers.\n\nThis is the core functionality. Further improvements\nwill be done separately.\n\nThis also adds/moves memory barriers where they belong and\nremoves the UnsafeGetLongVolatile and UnsafePutLongVolatile\nMIPS32 intrinsics as they need to load/store a pair of\nregisters atomically, which is not supported directly by\nthe CPU.\n\nTest: booted MIPS32R2 in QEMU\nTest: test-art-target-run-test\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: \"testrunner.py --target --optimizing -j1\"\nTest: same MIPS64 boot/test with ART_READ_BARRIER_TYPE\u003dTABLELOOKUP\nTest: \"testrunner.py --target --optimizing --32 -j2\" on CI20\nTest: same CI20 test with ART_READ_BARRIER_TYPE\u003dTABLELOOKUP\n\nChange-Id: I0ff91525fefba3ec1cc019f50316478a888acced\n" }, { "commit": "325e44f53ed03a9be7aca25edcb3cbc9c4fb0802", "tree": "17be8625da75c653ba986a374bc9d586cce54881", "parents": [ "7b7f8b4e07b57962cacbd9a05d9f5fad4f0a91aa", "49ebbb27ccaccd7d1466eebb24b847118b6f78a3" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Mar 28 17:47:43 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Mar 28 17:47:43 2017 +0000" }, "message": "Merge \"Fix return value of AtomicMethodRefMap::Get()\"" }, { "commit": "fbffc6706a826ef3a6f0839cb75393a34f0c2ef1", "tree": "2b12a7fc7e6cd0d854979760d98739ae18a5968b", "parents": [ "1082e0e46ddfae2ed9cc3d0a3d6025e7335ac239", "65b0263de5fae370604abef02262fb598f5de408" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Mar 28 17:09:28 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Mar 28 17:09:28 2017 +0000" }, "message": "Merge \"MIPS64: Add vector registers to Mips64ManagedRegister class\"" }, { "commit": "49ebbb27ccaccd7d1466eebb24b847118b6f78a3", "tree": "1a44223cdc05c45446a9a37c2ec532e52961f403", "parents": [ "c70d1d99654b25491997589b6ecfa431679ea2e3" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Mar 27 18:10:47 2017 -0700" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Mar 27 18:12:35 2017 -0700" }, "message": "Fix return value of AtomicMethodRefMap::Get()\n\nTest: m test-art-host\nChange-Id: I3f0841af081194f56b5f5004f9bd86fa2ab34238\n" }, { "commit": "65b0263de5fae370604abef02262fb598f5de408", "tree": "9fddf98e068655e521b9a83c9bce33cdebb0e68c", "parents": [ "da9f7eb3e7734b58576f71bad6d90aeea112f408" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Mar 22 07:37:26 2017 +0100" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Mar 24 11:54:13 2017 +0100" }, "message": "MIPS64: Add vector registers to Mips64ManagedRegister class\n\nAlso created managed_register_mips64_test.\n\nTest: mma test-art-host-gtest\n\nChange-Id: I3996691c8cc8bbc73f5d7ea294a31668905f6e8a\n" }, { "commit": "27af937fb4356ed34f175b14c4425fc95f5f8a19", "tree": "4eda35eeb1e1fe26d3125f0be895de5d2d61d771", "parents": [ "f4546792385ece9dd0ba956a6c9580027cfc8fdd" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Mar 15 15:31:34 2017 +0100" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Mar 23 09:44:18 2017 +0100" }, "message": "MIPS64: Check for MSA presence in each MSA instruction\n\nTest: mma test-art-host-gtest\n\nChange-Id: I123fe1e33de13af6a2b2a76f37f7ad23004a81c0\n" }, { "commit": "f9806373ca50896ac54cb9da49a030c13ec14769", "tree": "ff17cf35463c8d8d11891282a0d5839a2d887f80", "parents": [ "35c3ace32134156356da9c6b40d98586d4433553", "5a9e51d39ed3d1015f20b3d12b35747612cca40e" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Mar 20 17:14:10 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Mar 20 17:14:11 2017 +0000" }, "message": "Merge \"Revert \"Revert \"Introduce a number of MSA instructions for MIPS64\"\"\"" }, { "commit": "8200488eedb48c2bc9c22c336c0e6c26b48d3132", "tree": "b2fdeadbeca29f03ebec660d3e091c0740fb61e7", "parents": [ "2f1f1679d2ce9efd1d1817820015eb6ac26d9bfb", "c3fec0cc6fc9698f9fbd39ea817fd7dc64643fcb" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Mar 17 12:00:30 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Mar 17 12:00:32 2017 +0000" }, "message": "Merge \"MIPS64: Adjust Base and Offset\"" }, { "commit": "5a9e51d39ed3d1015f20b3d12b35747612cca40e", "tree": "17d4d1e616d5a516dc8187f165fc68ee97ada185", "parents": [ "8f2b925473cfdc7650cef407102957befe0c6bb5" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Mar 16 16:11:43 2017 +0000" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Mar 17 11:17:49 2017 +0100" }, "message": "Revert \"Revert \"Introduce a number of MSA instructions for MIPS64\"\"\n\nThis reverts commit 219bf253e5158c4f3438e70864b8bf7235c1e193.\n\nFixed memory leak in assembler_mips64_test.cc.\n\nTest: mma valgrind-test-art-host-gtest-assembler_mips64_test64\n\nChange-Id: I238833fd4555623c2716432fc67eab7696f1e28e\n" }, { "commit": "c3fec0cc6fc9698f9fbd39ea817fd7dc64643fcb", "tree": "3c677ea901a9725347bff1a3aa4c2a35cd471e47", "parents": [ "998e42aac59a55585603365367f4351f6d4344b1" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Thu Dec 15 11:44:14 2016 -0800" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Thu Mar 16 14:40:13 2017 -0700" }, "message": "MIPS64: Adjust Base and Offset\n\nMinimize the number of statements needed to load/store data at an\narbitrary offset from a base register.\n\nTest: test-art-host-gtest\nTest: ART_TEST_OPTIMIZING\u003dtrue test-art-target-run-test\n\nChange-Id: I76cc4b715dbb5b41c76b3c537fbd62bae8409bc0\n" }, { "commit": "e0abec751ce81b14a57522b51d43138fa1541d33", "tree": "621b29f3c328197daf68af3e68379a4194387070", "parents": [ "9d619c9555ba8232d4307ca28f750ac170afef92", "13a797bc53596af3d68eeb9721a8d76c23710ce9" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Mar 16 12:55:19 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Mar 16 12:55:20 2017 +0000" }, "message": "Merge \"vixl32: do not use D14 as a temporary.\"" }, { "commit": "13a797bc53596af3d68eeb9721a8d76c23710ce9", "tree": "b2d2b68a1a60215c7e10ac0821c1c761cebda787", "parents": [ "0a1f0798176250853c1fb83f00a436a183d2bfc1" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 15 16:41:31 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Mar 16 11:12:56 2017 +0000" }, "message": "vixl32: do not use D14 as a temporary.\n\nD14 is a callee-save register, which means we would need to\nsave it in the prologue, but at the point we\u0027re using it\nthe prologue has already been generated.\n\nbug: 35977033\ntest: m ART_USE_VIXL_ARM_BACKEND\u003dtrue test-art-target\nChange-Id: Id7340ad9e87a9e527ce0989f45aae0b3a0963206\n" }, { "commit": "fcfaa8d823017eb209fd6e18a6fe496f4c979026", "tree": "aa16954ce73fa029a571162f40d55bab47eb7069", "parents": [ "f01704050792cdb1556b1e2aab415d40424a7280", "219bf253e5158c4f3438e70864b8bf7235c1e193" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Wed Mar 15 22:37:47 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Mar 15 22:37:48 2017 +0000" }, "message": "Merge \"Revert \"Introduce a number of MSA instructions for MIPS64\"\"" }, { "commit": "219bf253e5158c4f3438e70864b8bf7235c1e193", "tree": "0ba845434b3b5679ee62b099c42ad455b4dcc37d", "parents": [ "dcabc8b740bf3066d59348ffdf21c164d2b27cb4" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 15 20:37:50 2017 +0000" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 15 20:37:50 2017 +0000" }, "message": "Revert \"Introduce a number of MSA instructions for MIPS64\"\n\nThis reverts commit dcabc8b740bf3066d59348ffdf21c164d2b27cb4.\n\n\nReason:\nFAILING TESTS\nvalgrind-test-art-host-gtest-assembler_mips64_test32\nninja: build stopped: subcommand failed.\n19:36:36 ninja failed with: exit status 1\nmake: *** [run_soong_ui] Error 1\n\nChange-Id: If658375528d2a0f34bb6b22b6565fab1d863b3f5\n" }, { "commit": "4b4553340dded4e8ce8f56690c08561a39a4aa56", "tree": "c52382b7b1b48ab23bf906ea87cff062acf0d320", "parents": [ "ba05290bb69e6bc9750d2485cd3dbfb013e61412" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 15 11:19:35 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 15 11:46:19 2017 -0700" }, "message": "SIMD cmpeq for x86/x86_64\n\nRationale:\nBreak-out CL of ART Vectorizer.\nEnables fast all-ones optimization.\n\nBug: 34083438\nTest: assembler_x86[_64]_test\nChange-Id: I70bd71305f2ecc322ccada5471c197a578c0526e\n" }, { "commit": "ba05290bb69e6bc9750d2485cd3dbfb013e61412", "tree": "4bc72784ac56dcaf5fbec530ac9c62cb0dcc574d", "parents": [ "92d578f48d2c00497f15d9fe45f7683d9af0e109", "21c580bf3f024f3f02d627013fba18a4b4f855d5" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 15 15:59:10 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Mar 15 15:59:10 2017 +0000" }, "message": "Merge \"SIMD and-not for x86/x86_64\"" }, { "commit": "92d578f48d2c00497f15d9fe45f7683d9af0e109", "tree": "3efef0c0de1728e968803d2a51b5c3b065d9d4f0", "parents": [ "8a31bb939f2ab1fe3f745ade40408ac07267208a", "dcabc8b740bf3066d59348ffdf21c164d2b27cb4" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 15 15:58:56 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Mar 15 15:58:57 2017 +0000" }, "message": "Merge \"Introduce a number of MSA instructions for MIPS64\"" }, { "commit": "dcabc8b740bf3066d59348ffdf21c164d2b27cb4", "tree": "1b16fe71dc17f5e3fad5e1f6a865141b5d22da6b", "parents": [ "96cc0a004b5685d8a3fea3cee3105fbbff73437f" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Mar 10 11:53:48 2017 +0100" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Tue Mar 14 17:21:19 2017 +0100" }, "message": "Introduce a number of MSA instructions for MIPS64\n\nAdded a number of MSA (The MIPS SIMD Architecture) instructions.\nAdded assembler tests for each instruction.\nMade necessary changes in disassembler for these instructions.\n\nTest: mma test-art-host-gtest\n\nChange-Id: I380f02c6ae5424a96ad999037153228acb07a108\n" }, { "commit": "ba89c34e94a82f0a6904dcc62caa6aa7bb14c12c", "tree": "a10992eabb2aade0c97e283038873a6c36d05132", "parents": [ "224f6ab7620ddbc20a338e56ccf9952d86b08b51" ], "author": { "name": "Tijana Jakovljevic", "email": "tijana.jakovljevic@imgtec.com", "time": "Fri Mar 10 13:36:08 2017 +0100" }, "committer": { "name": "Tijana Jakovljevic", "email": "tijana.jakovljevic@imgtec.com", "time": "Tue Mar 14 07:40:59 2017 +0100" }, "message": "MIPS64: Improve storing of constants in fields and array elements\n\nTest: booted MIPS64 in QEMU\nTest: mma test-art-target-run-test\nTest: mma test-art-host-gtest-assembler_mips64_test\n\nChange-Id: I8e0002166174eebea1309358eb9d96f34eee3225\n" }, { "commit": "21c580bf3f024f3f02d627013fba18a4b4f855d5", "tree": "d9186fa18d4bd5de8e76fb7b9a5d4a3f0f1f5e24", "parents": [ "01ea2aa05d6889b4ec08679606d3cdf36b302a8f" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Mar 13 11:52:07 2017 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Mar 13 11:52:07 2017 -0700" }, "message": "SIMD and-not for x86/x86_64\n\nRationale:\nBreak-out CL of ART Vectorizer.\nEnables and-not optimization.\n\nBug: 34083438\nTest: assembler_x86[_64]_test\nChange-Id: I8fa61d88f9f014973b0d9707d39be56a7f995db8\n" }, { "commit": "5743386b4d161f3884275c66b0783bd3cc3a8050", "tree": "6794f8047586e7bc02702cc560bca51d1ab5bcc3", "parents": [ "425b5d23e2c60d295471817a75b1b554481c5334" ], "author": { "name": "Tijana Jakovljevic", "email": "tijana.jakovljevic@imgtec.com", "time": "Tue Jan 17 16:59:03 2017 +0100" }, "committer": { "name": "Tijana Jakovljevic", "email": "tijana.jakovljevic@imgtec.com", "time": "Fri Mar 03 09:36:43 2017 +0100" }, "message": "MIPS64: Refactor implicit null checks in array/field get/set\n\nRationale: on MIPS64 64-bit loads and stores may be performed\nas pairs of 32-bit loads/stores. Implicit null checks must be\nassociated with the first 32-bit load/store in a pair and not\nthe last. This change ensures proper association of said checks\n(a few were done after the last 32-bit load/store in a pair)\nand lays ground for further improvements in array/field get/set.\n\nAdditionally ported to MIPS32.\n\nTest: mma test-art-target-run-test in QEMU\nTest: mma test-art-host-gtest\n\nChange-Id: If2612df62c21522959e69c637a36cc4ea962a32e\n" }, { "commit": "41ee103aadadfd71193157a1b850adbb91ac0d27", "tree": "ed73fb0cbc734c6dd3f6a35b82d8683bcda251d3", "parents": [ "0058a5487cf210abbe60840e732fdc9d81f1c1e1", "c061de1236e98fdd34d0214a9bbcc0e2149ff226" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Mar 01 13:16:48 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Mar 01 13:16:48 2017 +0000" }, "message": "Merge \"MIPS: Implement heap poisoning in ART\u0027s Optimizing compiler.\"" }, { "commit": "4cc7e8f848de11089a9b99cad549c5a2b7e275a6", "tree": "e43cbfc76e5b9383e3d99337d05dcd531a1af802", "parents": [ "69dcdead8a6271587e0686798a26f95e92629fc1", "647169364c40e731ac41d5655c6315ec22e29970" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Feb 28 12:43:06 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Feb 28 12:43:07 2017 +0000" }, "message": "Merge \"ARM: VIXL32: Use LoadLiteral for double constants.\"" }, { "commit": "3ae3b59e3354d1d387d216ac2fa5d481d3f2e833", "tree": "39aef45e8dde4dbbd9c24aab4a38e8350f39fc6d", "parents": [ "6c8ce9fa356554c2c82d400bfab6a239c35e8b7c" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Feb 24 14:09:15 2017 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Feb 24 14:09:15 2017 -0800" }, "message": "SIMD type conversion for x86\n\nRationale:\nBreak-out CL of ART Vectorizer: 1 OF many\nNeeded to demonstrate that same-length\ntype conversions easily fit the model.\n\nBug: 34083438\nTest: assembler_x86[_64]_test\nChange-Id: Ib9959a7e18485ab1629978c61032fcda16792951\n" }, { "commit": "647169364c40e731ac41d5655c6315ec22e29970", "tree": "a952c209f17c77928fca685d8e73f13f558bd4b6", "parents": [ "6cc0250f1d1507957fc2fe1543179eab5a8b53f9" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Fri Feb 10 13:39:43 2017 +0000" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Feb 23 16:01:54 2017 +0000" }, "message": "ARM: VIXL32: Use LoadLiteral for double constants.\n\nUse LoadLiteral for generating double constants if the constant\ndoesn\u0027t fit VMOV instruction encoding:\n\n0x00000004 ed9f0b07 vldr d0, 0x00000024\n+ entry in literal pool\n\nvs\n\n0x00000008 f64f0ca1 mov ip, #63649\n0x0000000c f2ce6c31 movt ip, #58929\n0x00000010 ee80cb10 vdup.32 d0, ip\n0x00000014 f6414cd6 mov ip, #7382\n0x00000018 f2c40cc8 movt ip, #16584\n0x0000001c ee20cb10 vmov.32 d0[1], ip\n\nTest: ART_USE_VIXL_ARM_BACKEND\u003dtrue m test-art-host\nTest: ART_USE_VIXL_ARM_BACKEND\u003dtrue m test-art-target\nChange-Id: Ia0343bd6b9473870e364df95f2ccfae9750050e0\n" }, { "commit": "c061de1236e98fdd34d0214a9bbcc0e2149ff226", "tree": "31f6644cf080613d8493db8f510810a89cc6a718", "parents": [ "4c9c57054578022d9ab8442264fbc661769f97f5" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Feb 14 13:27:23 2017 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Feb 22 14:10:59 2017 -0800" }, "message": "MIPS: Implement heap poisoning in ART\u0027s Optimizing compiler.\n\nThis is in preparation for read barrier support.\n\nBug: 12687968\n\nTest: test-art-host-gtest\nTest: booted MIPS32R2 in QEMU\nTest: test-art-target\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target (both MIPS64R6 and MIPS32R6)\n\nNote: built with ART_HEAP_POISONING\u003dtrue.\n\nChange-Id: I0e6e04ff8de2fc8ca6126388409fa218e6920734\n" }, { "commit": "3e1070239a920cc94b020a621acf4daeccebb140", "tree": "10149549582fa984d81b737ac236c6bc931fe6db", "parents": [ "30e015c442c8033390c30d2f293604723c29bc75" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Feb 22 10:57:03 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Feb 22 17:33:17 2017 +0000" }, "message": "Avoid excessive allocation of std::set\u003c\u003e nodes in SwapSpace.\n\nThis does not affect the overall memory usage but avoids\na lot of deallocations followed by allocation.\n\nMeasured compilation of a big app using heap track:\n bytes allocated in total (ignoring deallocations): 4.14GB -\u003e 4.04GB\n calls to allocation functions: 21662554 -\u003e 19545823\n\nTest: m test-art-host-gtest\nTest: Manually check that oat file for the big app remains identical.\nBug: 34053922\nChange-Id: I00568422ba5510550986e29f30bace9ae6245269\n" }, { "commit": "e69d7a9bc042423a89a6d7b6b1c2236911f67b59", "tree": "06b8836ff5f24fc625be4c40b996b6cefca0258b", "parents": [ "6a669aac63ffc17b5e903aa4a1f285fe338eadcf" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Feb 17 11:48:23 2017 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Feb 17 11:48:23 2017 -0800" }, "message": "Added a few more integral SIMD extensions for x86/x86_64 (SSE).\n\nRationale:\nART vectorizer needs a couple of extra SIMD operations before\nsending out the larger general CL.\n\nTest: assembler_x86[_64]_test\nBug: 34083438\nChange-Id: Id156283424ad311e6109b360efcd409c671cd5b7\n" }, { "commit": "68555e952eea58023fa403951b1491496acf0f4b", "tree": "304d10e4d1b11698d73e0b5fb3d9aa69daccca9d", "parents": [ "5abcfe6254acce99bf25a151b19ffe5c9b50494f" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Feb 13 14:28:45 2017 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Mon Feb 13 14:28:45 2017 -0800" }, "message": "Added a few integral SIMD extensions for x86/x86_64 (SSE).\n\nRationale:\nART vectorizer needs SIMD for integer operations too.\n\nTest: assembler_x86[_64]_test\nBug: 34083438\nChange-Id: Id6fec558c617d38cb643839eafcd10e59dcd6e0a\n" }, { "commit": "97c381e3ce34cd327c2ec35fa850bd0eaa9b697f", "tree": "4a21b2db89c578cdb2908547547e0546748eec7f", "parents": [ "3cb871ab1af47576959fd24a99d370381b8f193e" ], "author": { "name": "David Sehr", "email": "sehr@google.com", "time": "Wed Feb 01 15:09:58 2017 -0800" }, "committer": { "name": "David Sehr", "email": "sehr@google.com", "time": "Wed Feb 01 15:51:42 2017 -0800" }, "message": "Separate art::Exec from utils\n\nThe rest of utils.cc does not depend on art::Runtime. This separates\nthe part dependent on that class, so that including utils.cc in the\nbuild does not require the entire Runtime. Another preparatory cleanup\nto getting tools to build on Windows.\n\nBug: 22322814\nTest: test-art\nChange-Id: I194ff363fc2ab87e5311ecea6973a2d0fad2621d\n" }, { "commit": "12e06edcdc7a986c127aed58dd836d6767d0e21d", "tree": "01addea5fd1df2c6eb7ec8355138d3d203518b03", "parents": [ "f2042db1b41cc21cc540c5ad7d353cbe1e3a32df" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Jan 31 16:11:24 2017 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Jan 31 16:29:17 2017 -0800" }, "message": "Added few more SIMD extensions for x86/x86_64 (SSE).\n\nRationale:\nPrototype ART vectorizer needs way to set invariant vectors.\n\nTest: assembler_x86[_64]_test\nBug: 34083438\nChange-Id: I5ab2ad77b8f9b64b46cc8635ad926e54787508a2\n" }, { "commit": "b048cb74b742b03eb6dd5f1d6dd49e559f730b36", "tree": "b1f663cbb343488a548cce4db352dbc4af720a89", "parents": [ "f34077c96af3389e8eae65252d4c5d51cf630039" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jan 23 22:50:24 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 26 09:56:36 2017 +0000" }, "message": "Add per array size allocation entrypoints.\n\n- Update architectures that have fast paths for\n array allocation to use it.\n- Will add more fast paths in follow-up CLs.\n\nTest: test-art-target test-art-host.\nChange-Id: I138cccd16464a85de22a8ed31c915f876e78fb04\n" }, { "commit": "95f271496da7421021ccb9845726a94cd5eaa914", "tree": "91ed5a3cd3394996e15072f363801409d27b3fcd", "parents": [ "5e821602426718bf971c3d693c3f8ff15d85017d" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Jan 20 11:11:11 2017 +0100" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Jan 20 11:13:31 2017 +0100" }, "message": "MIPS64: Extend assembler_mips64_test\n\nAdd tests for several existing instructions.\n\nTest: mma test-art-host-gtest-assembler_mips64_test\n\nChange-Id: I1505dc0cf019de2afedc9648e3fd41e7fd051861\n" }, { "commit": "8d91ac31ccb92557e434d89ffade3372466e1af5", "tree": "37fd364ba6c9a6cf5e6a60a00c2542c5ffb12528", "parents": [ "2f670ccba022fe557c637571ac781519f0e84463" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 18 18:07:15 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 19 11:56:43 2017 +0000" }, "message": "Remove unused array entrypoints.\n\nTest: test-art-host test-art-target\nChange-Id: I910d1c912c7c9056ecea0e1e7da7afb2a7220dfa\n" }, { "commit": "39cee66a8ddf0254626c9591662cf87e4a1cedc4", "tree": "be25df71e51ce03a8847c23934322b8f282a291b", "parents": [ "a3974581751cd73a896f7c4fcab71beb17c4f9dc" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 13 16:04:53 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 18 11:12:33 2017 +0000" }, "message": "Entrypoints cleanup.\n\nRemove unused ones to facilitate the transition to compressed\ndex caches.\n\ntest: test-art-host, test-art-target\nChange-Id: I1d1cb0daffa86dd9dda2eaa3c1ea3650a5c8d9d0\n" }, { "commit": "55ddcc8fe93d5b22e1ab092d20ba8f76a834c0cf", "tree": "b22aeb9d8d3a3fb3c549fd95ca7fed50a2f5cea3", "parents": [ "ce27739a1207c530c0ecebaefef80652f401f2d1", "c778226256bced7105fcbb1a028dfbba135c6c29" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Jan 17 22:10:25 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jan 17 22:10:26 2017 +0000" }, "message": "Merge \"Introduce a number of SIMD extensions for x86/x86_64 (SSE).\"" }, { "commit": "e71b35446985835363a4508646cf7b1121bd95a3", "tree": "bd40763b04ba2028f3383736b2a14808e407120c", "parents": [ "8bd59a0fd46db83616785168231e09fb95ed2ead" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jan 16 14:58:23 2017 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jan 17 11:55:07 2017 +0000" }, "message": "Move some fields in art::Thread to reduce maintenance burden.\n\nMove fields `thread_local_start`, `thread_local_pos`,\n`thread_local_end` and `thread_local_objects` before fields\n`jni_entrypoints` and `quick_entrypoints` within\nart::Thread, to avoid repetitive art::Thread field moves in\nfuture CLs caused by the addition or deletion of entry\npoints.\n\nTest: m test-art-host\ntest: m test-art-target (on ARM)\nChange-Id: Ib67842e44a7f21a871ca4d1bb95dc6f7cfedc829\n" }, { "commit": "ac141397dc29189ad2b2df41f8d4312246beec60", "tree": "a2f481463a14695bf9327fd2f549878ecf30c77b", "parents": [ "5c9f90c5ecf2ff6f93ada0f7b18b46d866c59ea1" ], "author": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Fri Jan 13 11:53:47 2017 +0000" }, "committer": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Sun Jan 15 15:18:07 2017 +0000" }, "message": "Revert \"Revert \"ART: Compiler support for invoke-polymorphic.\"\"\n\nThis reverts commit 0fb5af1c8287b1ec85c55c306a1c43820c38a337.\n\nThis takes us back to the original change and attempts to fix the\nissues encountered:\n\n- Adds transition record push/pop around artInvokePolymorphic.\n- Changes X86/X64 relocations for MacSDK.\n- Implements MIPS entrypoint for art_quick_invoke_polymorphic.\n- Corrects size of returned reference in art_quick_invoke_polymorphic\n on ARM.\n\nBug: 30550796,33191393\nTest: art/test/run-test 953\nTest: m test-art-run-test\n\nChange-Id: Ib6b93e00b37b9d4ab743a3470ab3d77fe857cda8\n" }, { "commit": "c778226256bced7105fcbb1a028dfbba135c6c29", "tree": "0191f8a968593112bcc66d8dd6efb572b888a0ed", "parents": [ "8799ea0a82bbe7d4fbd2375ae20fa8a720c887d4" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Jan 13 16:20:08 2017 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Jan 13 17:05:02 2017 -0800" }, "message": "Introduce a number of SIMD extensions for x86/x86_64 (SSE).\n\nRationale:\nAs a first step exploring how useful an ART vectorizer may be,\nintroducing a number of floating-point SIMD instructions.\n\nTest: assembler_x86[_64]_test\nBug: 34083438\nChange-Id: I0285dd9fca51f31875a6bbe728f873c48089940d\n" }, { "commit": "0d3998b5ff619364acf47bec0b541e7a49bd6fe7", "tree": "a4763c0660372f6311b612c09267cbbc2fe71e89", "parents": [ "aa89a4c6fca095904521842c018399f1e3501a45" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 12 15:35:12 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 12 16:51:12 2017 +0000" }, "message": "Revert \"Revert \"Make object allocation entrypoints only take a class.\"\"\n\nThis reverts commit f7aaacd97881c6924b8212c7f8fe4a4c8721ef53.\n\nChange-Id: I6756cd1e6110bb45231f62f5e388f16c044cb145\n" }, { "commit": "f7aaacd97881c6924b8212c7f8fe4a4c8721ef53", "tree": "780209ac8e992fa63307062977f672aa5bb55d9e", "parents": [ "2b615ba29c4dfcf54aaf44955f2eac60f5080b2e" ], "author": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Thu Jan 12 02:58:38 2017 +0000" }, "committer": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Thu Jan 12 02:58:38 2017 +0000" }, "message": "Revert \"Make object allocation entrypoints only take a class.\"\n\n960-default-smali64 is failing.\n\nThis reverts commit 2b615ba29c4dfcf54aaf44955f2eac60f5080b2e.\n\nChange-Id: Iebb8ee5a917fa84c5f01660ce432798524d078ef\n" }, { "commit": "2b615ba29c4dfcf54aaf44955f2eac60f5080b2e", "tree": "0a2fe5f9243645a054d4aa094bff5a69cc1abb88", "parents": [ "c9a060f2688599d4a402ee6234db46c2e9b7463f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 06 14:40:07 2017 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 11 10:34:10 2017 +0000" }, "message": "Make object allocation entrypoints only take a class.\n\nChange motivated by:\n- Dex cache compression: having the allocation fast path do a\n dex cache lookup will be too expensive. So instead, rely on the\n compiler having direct access to the class (either through BSS for\n AOT, or JIT tables for JIT).\n- Inlining: the entrypoints relied on the caller of the allocation to\n have the same dex cache as the outer method (stored at the bottom of\n the stack). This meant we could not inline methods from a different\n dex file that do allocations. By avoiding the dex cache lookup in\n the entrypoint, we can now remove this restriction.\n\nCode expansion on average for Docs/Gms/FB/Framework (go/lem numbers):\n- Around 0.8% on arm64\n- Around 1% for x64, arm\n- Around 1.5% on x86\n\nTest: test-art-host, test-art-target, ART_USE_READ_BARRIER\u003dtrue/false\nTest: test-art-host, test-art-target, ART_DEFAULT_GC_TYPE\u003dSS ART_USE_TLAB\u003dtrue\n\nChange-Id: I41f3748bb4d251996aaf6a90fae4c50176f9295f\n" }, { "commit": "f67dadb5550ee2bd9db0b7b0b75d8c44ddf170d2", "tree": "44f61f9bd0a674cae29c42e6dff72d4ff14189d0", "parents": [ "cda4b75615f5f11c101ff846a05affda405b101b", "0960ac5a5a255bb3e8418e185914243aeef54a7c" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Jan 05 17:37:56 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jan 05 17:37:57 2017 +0000" }, "message": "Merge \"MIPS64: Implement table-based packed switch\"" }, { "commit": "8174621224ecfc81dae10d1e3a317404c695a3ee", "tree": "fdcfa65d493183e0e807252dd3346d306c3ccee9", "parents": [ "f0bfd75c19b109e6a84fb3c2a81d3933a95a2738", "692235eb54544277e2bde862caa6038472fab833" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 05 13:27:14 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jan 05 13:27:15 2017 +0000" }, "message": "Merge \"MIPS32: java.lang.String.getChars\"" }, { "commit": "059802455e80a92a0fac780246968588bb0cf88b", "tree": "0e21efe27665f80998ac61f0f2e16be4cb2d4715", "parents": [ "e2157fb29e02561bc3197ab49e6c1d9dfe801b81", "f8d19c285204cbe44309d560a35a0fbf667e3ca2" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 04 10:06:27 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jan 04 10:06:27 2017 +0000" }, "message": "Merge changes from topic \u0027VIXLUpdate\u0027\n\n* changes:\n ARM: VIXL32: Use a default code buffer capacity of 1Kb.\n ART: VIXL32: Fix assembler test after VIXL update.\n" }, { "commit": "692235eb54544277e2bde862caa6038472fab833", "tree": "e33282f7de0e4aa8e76129597cc1ef2aa3fa13a3", "parents": [ "00797355fa88299db5b4ac941bbda17cd97ab39e" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Mon Nov 21 16:04:53 2016 -0800" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Tue Jan 03 12:07:45 2017 -0800" }, "message": "MIPS32: java.lang.String.getChars\n\nUse memcpy(3) to copy characters under the assumption that memcpy()\nhas been hand optimized for best performance on the platform being\ntested.\n\nTest: run-test --optimizing 020-string\nTest: run-test 020-string\nTest: run-test --no-prebuild --optimizing 020-string\nTest: run-test --no-prebuild 020-string\nTest: run-test --optimizing 082-inline-execute\nTest: run-test 082-inline-execute\nTest: run-test --no-prebuild --optimizing 082-inline-execute\nTest: run-test --no-prebuild 082-inline-execute\nTest: mma -j2 ART_TEST_OPTIMIZING\u003dtrue test-art-target-run-test\nTest: booted MIPS32R2 emulator.\n\nNote: Tested against both the MIPS32R2, and MIPS64R6 emulators.\n\nChange-Id: I4192cf6244db120c8de5cc4932d4132acfc9740d\n" }, { "commit": "66e3919bc42ddca40302ce5ee32e3ade248dd2b6", "tree": "3800e8499317efc4b5bca06e483b2bcbd9da8d9d", "parents": [ "6a14c622700e088173ba909799c1e1785aeb4b34", "e36605910cb13da1440fb9d7a8293842a9209c97" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Jan 03 11:13:50 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jan 03 11:13:51 2017 +0000" }, "message": "Merge \"MIPS64: java.lang.String.getChars\"" }, { "commit": "f8d19c285204cbe44309d560a35a0fbf667e3ca2", "tree": "81930e48a85fe8efad1c14c308a9a3aebe9cc62d", "parents": [ "f2665fa6e5ca54c7d4f084ec1fab9a20e96aea75" ], "author": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Tue Dec 20 09:43:32 2016 +0000" }, "committer": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Thu Dec 22 14:58:46 2016 +0000" }, "message": "ARM: VIXL32: Use a default code buffer capacity of 1Kb.\n\nTest: mma test-art-host \u0026\u0026 mma test-art-target\n\nChange-Id: I238c40e775338b63cbdb8868c09d0555b0c3b077\n" }, { "commit": "f2665fa6e5ca54c7d4f084ec1fab9a20e96aea75", "tree": "2de4c1166f3686b3e1b15c76b14082847985dff6", "parents": [ "294e107e8947224ea6540af5068bce2492ee8d5b" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Wed Dec 21 18:42:21 2016 +0000" }, "committer": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Thu Dec 22 14:58:46 2016 +0000" }, "message": "ART: VIXL32: Fix assembler test after VIXL update.\n\nVeneer pool is emitted 4 bytes later, so the expected output for\nthe test has been adjusted.\n\nTest: test-art-host\nTest: test-art-target\nChange-Id: I3d656224fd4151904b8096486adecb6ef1eafea6\n" }, { "commit": "0960ac5a5a255bb3e8418e185914243aeef54a7c", "tree": "7163af0759328285dce0e3a5af13bd5b0cc042c0", "parents": [ "07001c8540718117b91e8137804fa94d35cbb37a" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Dec 20 17:24:59 2016 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Dec 21 16:01:49 2016 -0800" }, "message": "MIPS64: Implement table-based packed switch\n\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-run-test-optimizing (MIPS64R6) in QEMU\nTest: test-art-host-gtest\n\nChange-Id: I333dca43fca57ae7e6021bb84585487c889417c3\n" }, { "commit": "1ffb6fc9210eabd6c272018aaae63a6ed46d89e1", "tree": "bc5718b5653137bc48c637c50a2b801ad1a86323", "parents": [ "06ce6d4359ed897f1d1b39be4e748f0c4f3ca2ff", "517d9f6678c5d577f25777bc000a83afd5503874" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 20 13:52:48 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Dec 20 13:52:48 2016 +0000" }, "message": "Merge \"ARM: VIXL32: Use 16-bit encoding for B(cond,...) where possible.\"" }, { "commit": "06ce6d4359ed897f1d1b39be4e748f0c4f3ca2ff", "tree": "57f3da550807191fa705f2d639051f156f60c30e", "parents": [ "eaaaaef76b7702af91cc599c0d020fa495990c7f", "f63f569eeefe3907c48a175494a2a0ba351b641a" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Dec 20 12:00:20 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Dec 20 12:00:21 2016 +0000" }, "message": "Merge \"MIPS64: Improve string and class loads.\"" }, { "commit": "f63f569eeefe3907c48a175494a2a0ba351b641a", "tree": "c2ba1621cbcd77571378b8261ec6d47c754953aa", "parents": [ "2c43590dc2bb7fb4a3a015b1b65543bb8705ffe8" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Dec 13 17:43:11 2016 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Dec 19 14:47:16 2016 -0800" }, "message": "MIPS64: Improve string and class loads.\n\nThis adds most kinds of string/class loads.\nJIT string/class loads are TBD separately.\n\nThis also fixes Mips64Assembler::LoadLabelAddress()\n(adding a constant to a 64-bit address must be done\nusing daddiu, not addiu).\n\nTest: test-art-host-gtest\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: \"make -j1 ART_TEST_DEFAULT_COMPILER\u003dfalse ART_TEST_OPTIMIZING\u003dtrue\n ART_TEST_INTERPRETER\u003dfalse ART_TEST_JIT\u003dfalse\n ART_TEST_PIC_TEST\u003dtrue test-art-target-run-test64\"\n\nChange-Id: I1f94ece4cd202382c11167e1ed958e9d08d92822\n" }, { "commit": "685e4a325221a302255f4232edcbaa554159543d", "tree": "61d0e5a7b6f7ce94f7615b9015bb61f40f80a76e", "parents": [ "76873db28c738bceef766047eb8452a6a5c447fc", "8f840f805579896809f6a17705402a85793ebce9" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 19 09:31:18 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Dec 19 09:31:19 2016 +0000" }, "message": "Merge \"ARM: Fix vixl related branch issue in JNI.\"" } ], "next": "8f840f805579896809f6a17705402a85793ebce9" }