)]}'
{
  "log": [
    {
      "commit": "0f3d7acf40b2ba1b04a9b359950a30b6314ace07",
      "tree": "fe25b27252489b17dd9865ddf688649dc9495ff7",
      "parents": [
        "50fe6dc170402600936d72a5fd729b5ebda0294b"
      ],
      "author": {
        "name": "Evgeny Astigeevich",
        "email": "evgeny.astigeevich@linaro.org",
        "time": "Thu Aug 06 16:28:37 2020 +0100"
      },
      "committer": {
        "name": "Evgeny Astigeevich",
        "email": "evgeny.astigeevich@linaro.org",
        "time": "Tue Aug 18 15:10:01 2020 +0100"
      },
      "message": "ART: Add HasNonNegativeInputAt and HasNonNegativeOrMinIntInputAt\n\nWhen it can be quickly checked that an input operand in non-negative,\nadditional optimizations can be applied during code generation.\n\nThe CL adds HasNonNegativeInputAt and HasNonNegativeOrMinIntInputAt\nwhich can be used to check if the input operand of an instruction at\nthe index is non-negative. They guarantee that at the time of checks\nthe instruction can have non-negative inputs. Other optimizations after\nthat might break the invariant.\n\nOptimizations HRem/HDiv for ARM32/ARM64 are moved to used the new methods.\n\nTest: 411-checker-hdiv-hrem-pow2\nTest: 411-checker-hdiv-hrem-const\nTest: test.py --host --optimizing --jit --gtest --interpreter\nTest: test.py -target --optimizing --jit --interpreter\nTest: run-gtests.sh\nChange-Id: Icf8574699e003bba194097c4e39660de16aa53d9\n"
    },
    {
      "commit": "af92a0f06fe3ab2618ccc220df3dacc3a20d8bb1",
      "tree": "a1825765fba713b9805a26b35743506907cdefe8",
      "parents": [
        "8d799686ff11ef800a8489272f4e0b36b6ab21b3"
      ],
      "author": {
        "name": "Evgeny Astigeevich",
        "email": "evgeny.astigeevich@linaro.org",
        "time": "Fri Jun 26 13:28:33 2020 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jul 02 10:49:08 2020 +0000"
      },
      "message": "ARM: Optimize Div/Rem by 2^n for non-negative dividends\n\nWhen it can be proved that dividends are non-negative or the min integer\nif their type is integral, there is no need to generate instructions\ncorrecting the result.\n\nThe CL implements this optimization for ARM32/ARM64.\n\nTest: 411-checker-hdiv-hrem-pow2\nTest: test.py --host --optimizing --jit --gtest --interpreter\nTest: test.py -target --optimizing --jit --interpreter\nTest: run-gtests.sh\n\nChange-Id: I11211a42918b5801fce8e78f305e69549739c23c\n"
    },
    {
      "commit": "0a51605ddd81635135463dab08b6f7c21b58ffb0",
      "tree": "820f338333010f4d6e4b543ffea47e9ff7d2dd3f",
      "parents": [
        "e2727154f25e0db9a5bb92af494d8e47b181dfcf"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Oct 14 13:00:44 2019 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Oct 14 13:00:44 2019 +0000"
      },
      "message": "Revert \"Make compiler/optimizing/ symbols hidden.\"\n\nThis reverts commit e2727154f25e0db9a5bb92af494d8e47b181dfcf.\n\nReason for revert: Breaks ASAN tests (ODR violation).\nBug: 142365358\n\nChange-Id: I38103d74a1297256c81d90872b6902ff1e9ef7a4\n"
    },
    {
      "commit": "e2727154f25e0db9a5bb92af494d8e47b181dfcf",
      "tree": "0ddc6eec3ad9508d7eb1f2b941786dd0ed7d2cd8",
      "parents": [
        "c78860b91ae07eed92f86876e7a03132adea6fcd"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Oct 10 10:46:42 2019 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Oct 14 08:22:00 2019 +0000"
      },
      "message": "Make compiler/optimizing/ symbols hidden.\n\nMake symbols in compiler/optimizing hidden by a namespace\nattribute. The unit intrinsic_objects.{h,cc} is excluded as\nit is needed by dex2oat.\n\nAs the symbols are no longer exported, gtests are now linked\nwith the static version of the libartd-compiler library.\n\nlibart-compiler.so size:\n  - before:\n    arm: 2396152\n    arm64: 3345280\n  - after:\n    arm: 2016176 (-371KiB, -15.9%)\n    arm64: 2874480 (-460KiB, -14.1%)\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nBug: 142365358\nChange-Id: I1fb04a33351f53f00b389a1642e81a68e40912a8\n"
    },
    {
      "commit": "57943810cfc789da890d73621741729da5feaaf8",
      "tree": "367677a982a45af98ffe3e79543615875e8550b4",
      "parents": [
        "d5153627778e71ef68b510ce03c77467fa4d85bd"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Wed Dec 06 21:39:13 2017 -0800"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Thu Dec 07 16:26:11 2017 -0800"
      },
      "message": "ART: Replace base/logging with android-base/logging\n\nReplace wherever possible. ART\u0027s base/logging is now mainly VLOG\nand initialization code that is unnecessary to pull in and makes\nchanges to verbose logging more painful than they have to be.\n\nTest: m test-art-host\nChange-Id: I3e3a4672ba5b621e57590a526c7d1c8b749e4f6e\n"
    },
    {
      "commit": "b3e773eea39a156b3eacf915ba84e3af1a5c14fa",
      "tree": "6c0d3a748d7b445a0d776ed306c7add43a0e1dd3",
      "parents": [
        "05aeb408f292d8d94af1646a94bc69faf77f0b46"
      ],
      "author": {
        "name": "David Brazdil",
        "email": "dbrazdil@google.com",
        "time": "Tue Jan 26 11:28:37 2016 +0000"
      },
      "committer": {
        "name": "David Brazdil",
        "email": "dbrazdil@google.com",
        "time": "Thu Jan 28 15:48:00 2016 +0000"
      },
      "message": "ART: Implement support for instruction inlining\n\nOptimizing HIR contains \u0027non-materialized\u0027 instructions which are\nemitted at their use sites rather than their defining sites. This\nwas not properly handled by the liveness analysis which did not\nadjust the use positions of the inputs of such instructions.\nDespite the analysis being incorrect, the current use cases never\nproduce incorrect code.\n\nThis patch generalizes the concept of inlined instructions and\nupdates liveness analysis to set the compute use positions correctly.\n\nChange-Id: Id703c154b20ab861241ae5c715a150385d3ff621\n"
    },
    {
      "commit": "0debae7bc89eb05f7a2bf7dccd223318fad7c88d",
      "tree": "3da9656dc77d271b12c1b02793e7d713ae3da790",
      "parents": [
        "991842a5273d20695dd5f35eb9a9e28c386c5b4b"
      ],
      "author": {
        "name": "David Brazdil",
        "email": "dbrazdil@google.com",
        "time": "Thu Nov 12 18:37:00 2015 +0000"
      },
      "committer": {
        "name": "David Brazdil",
        "email": "dbrazdil@google.com",
        "time": "Tue Nov 17 15:12:00 2015 +0000"
      },
      "message": "ART: Refactor GenerateTestAndBranch\n\nEach code generator implements a method for generating condition\nevaluation and branching to arbitrary labels. This patch refactors\nit for better clarity but also to generate fewer jumps when the true\nbranch is the fallthrough successor.\n\nThis is preliminary work for implementing HSelect.\n\nChange-Id: Iaa545a5ecbacb761c5aa241fa69140cf6eb5952f\n"
    },
    {
      "commit": "b8b97695d178337736b61609220613b92f344d45",
      "tree": "8b412373d1f21cac78168e284e36977a7fab0875",
      "parents": [
        "b24301b06b31b463f7e92ebc9a8f75839e54b746"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Fri May 22 16:58:19 2015 -0400"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Thu Nov 05 10:44:24 2015 -0500"
      },
      "message": "Fix conditional jump over jmp (X86/X86-64/ARM32)\n\nOptimize the code generation for \u0027if\u0027 statements to jump to the\n\u0027false\u0027 block if the next block to be generated is the \u0027true\u0027 block.\n\nAdd an X86-64 test for this case.\n\nNote that ARM64 \u0026 MIPS64 have not been updated.\n\nChange-Id: Iebb1352feb9d3bd0142d8b0621a2e3069a708ea7\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "b19930c5cba3cf662dce5ee057fcc9829b4cbb9c",
      "tree": "c226f8fffc4522b273072c516507083e2a77c505",
      "parents": [
        "0f88e87085b7cf6544dadff3f555773966a6853e"
      ],
      "author": {
        "name": "Guillaume Sanchez",
        "email": "guillaumesa@google.com",
        "time": "Thu Apr 09 21:12:15 2015 +0100"
      },
      "committer": {
        "name": "Guillaume Sanchez",
        "email": "guillaumesa@google.com",
        "time": "Fri Apr 10 10:28:02 2015 +0100"
      },
      "message": "Follow up of \"div/rem on x86 and x86_64\", to tidy up the code a little.\n\nChange-Id: Ibf39cbc8ac1d773599d70be2cb1e941674b60f1d\n"
    },
    {
      "commit": "0f88e87085b7cf6544dadff3f555773966a6853e",
      "tree": "ea0ae17c712b995e258f1f749a1b8cd98b1fa34b",
      "parents": [
        "c4bd0e6a7f4839ea99222f06979cc2369cb9bf10"
      ],
      "author": {
        "name": "Guillaume Sanchez",
        "email": "guillaumesa@google.com",
        "time": "Mon Mar 30 17:55:45 2015 +0100"
      },
      "committer": {
        "name": "Guillaume Sanchez",
        "email": "guillaumesa@google.com",
        "time": "Thu Apr 09 12:24:10 2015 +0100"
      },
      "message": "Speedup div/rem by constants on x86 and x86_64\n\nThis is done using the algorithms in Hacker\u0027s Delight chapter 10.\n\nChange-Id: I7bacefe10067569769ed31a1f7834f796fb41119\n"
    }
  ]
}