)]}' { "log": [ { "commit": "952dbb19cd094b8bfb01dbb33e0878db429e499a", "tree": "82932c2b00245042e2c129f3d4133f6431657da3", "parents": [ "df638c66d1f385d4e217b2ab22c5e48a7eefdef4" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 28 12:01:51 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Aug 04 14:51:52 2016 +0100" }, "message": "Change suspend entrypoint to save all registers.\n\nWe avoid the need to save/restore registers in slow paths\nand get significant code size savings. On Nexus 9, AOSP:\n - 32-bit boot.oat: -1.4MiB (-1.9%)\n - 64-bit boot.oat: -2.0MiB (-2.3%)\n - other 32-bit oat files in dalvik-cache: -200KiB (-1.7%)\n - other 64-bit oat files in dalvik-cache: -2.3MiB (-2.1%)\n\nTest: Run ART test suite on host and Nexus 9 with gc stress.\nBug: 30212852\nChange-Id: I7015afc1e7d30341618c9200a3dc9ae277afd134\n" }, { "commit": "d22b69a12777014a92a3551eba65a4c69f2800b2", "tree": "9610ef0db5bdd3b21bfcfa4de2f1f3328b928f5b", "parents": [ "e3051bf60783fa18e6f8c7ac6f73091f05af5665", "d549c28cfbddba945cb88857bcca3dce1414fb29" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jul 28 16:20:19 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 28 16:20:19 2016 +0000" }, "message": "Merge \"Remove two ReadBarrierMarkRegX entrypoints.\"" }, { "commit": "d549c28cfbddba945cb88857bcca3dce1414fb29", "tree": "584d765beea2cd6ceb4d56789ccc5c8f64db967e", "parents": [ "9e27d02040ff87eb8e2d56d21347a77cb800eddf" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jul 25 12:49:15 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jul 25 12:49:15 2016 +0100" }, "message": "Remove two ReadBarrierMarkRegX entrypoints.\n\nAs entry points ReadBarrierMarkReg30 and\nReadBarrierMarkReg31 are undefined on all architectures\nsupporting the read barrier configuration (ARM, ARM64, x86\nand x86-64), remove them from the entry point list.\n\nTest: ART host and target (ARM, ARM64) tests.\nBug: 29506760\nBug: 12687968\nChange-Id: I500626e54f00aebfc095b4ef5f81b49fa43f7768\n" }, { "commit": "4b5f7919842ef88526b9237413bb968a5b6dfeed", "tree": "0983c949692b909d6b46ec25462d98232909daef", "parents": [ "d8b668fbb6937bcaafaf3129bd01a7372547ab35" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Thu Jul 21 14:59:04 2016 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri Jul 22 16:54:21 2016 -0700" }, "message": "Add fast path to arm64 READ_BARRIER macro\n\nEAAC benchmark time from 978.7857143ms to 969.5714286ms on N9 based\non 42 samples. Reduces artReadBarrierSlow calls from 9M to 1M.\n\nNot a huge improvement since we were already checking the lock word in\nReadBarrier::Barrier.\n\nTest: N9 boots, test-art-host, EEAC runs. (All with CC enabled).\n\nBug: 30162165\nBug: 12687968\n\nChange-Id: Ifb97b52ea84e21c7df83addfb91c5f05f41db32d\n" }, { "commit": "b78b3a8d93196db13d19fdac9fafcf6a4312856a", "tree": "657816479a70d6f395d4ecad3bd75c02046b2d83", "parents": [ "ed33b7357c0a2d7388c9da017aea57c1b81521f2", "d207b42dda8bb66c1754f4e85c03e354d0d22ff2" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Jul 21 14:19:33 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 21 14:19:33 2016 +0000" }, "message": "Merge \"Change return type of artIsAssignableFromCode for MIPS64\"" }, { "commit": "ed33b7357c0a2d7388c9da017aea57c1b81521f2", "tree": "01c187be9729579b83127e32ce5883ef188462a7", "parents": [ "057361ca33625ed14b33ffd8e641e27916fb2fea", "cddb9d2f67baa09552710540c77950a1d95a8f90" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jul 21 14:17:40 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 21 14:17:41 2016 +0000" }, "message": "Merge \"Fix the definition of MACRO_LITERAL for OS X on x86-64.\"" }, { "commit": "cddb9d2f67baa09552710540c77950a1d95a8f90", "tree": "decd02a9aaeb3db51057246b349238cd5eeee7de", "parents": [ "74c0d1bb67f9c6ee8306f0318ab7251d56dc99d6" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jul 05 18:55:32 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jul 21 13:45:48 2016 +0000" }, "message": "Fix the definition of MACRO_LITERAL for OS X on x86-64.\n\nTest: \"ART_USE_READ_BARRIER\u003dtrue mmma art\" on OS X.\nChange-Id: Ia2d4c7a3eb7fec346ddfa4c7b0f7b700f1137344\n" }, { "commit": "d207b42dda8bb66c1754f4e85c03e354d0d22ff2", "tree": "ee6d0f2d98c73f7fbb8f83d6dbd2b0f1bf2cff82", "parents": [ "057361ca33625ed14b33ffd8e641e27916fb2fea" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Jul 21 14:21:46 2016 +0200" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 21 13:29:05 2016 +0000" }, "message": "Change return type of artIsAssignableFromCode for MIPS64\n\nThis has been missed by Ic505befc6c94e2dccbc8abf2b13d4c2d662e68d1.\nThis fixes MIPS64 build.\n\nBug: 30232671\nTest: make -j 32 out/target/product/generic_mips64/obj/SHARED_LIBRARIES/libart_intermediates/arch/mips64/entrypoints_init_mips64.o\nChange-Id: Iec89d25e2d38c6efc0d1025767d0ac2a8bdb7dcd\n" }, { "commit": "057361ca33625ed14b33ffd8e641e27916fb2fea", "tree": "cf13a0b5c0e5504fdcf320ab9a9936d0d489bdf5", "parents": [ "65ad9b3516c4f4bc4e7abf5c6e065a675cf024d8", "4359e61927866c254bc2d701e3ea4c48de10b79c" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jul 21 12:11:15 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 21 12:11:15 2016 +0000" }, "message": "Merge \"Move caller-saves saving/restoring to ReadBarrierMarkRegX.\"" }, { "commit": "4359e61927866c254bc2d701e3ea4c48de10b79c", "tree": "05d274ecd6b5ff6eb890f64cd3bb670c7170bf15", "parents": [ "2be946bbf995496fe56364d9b7c4957fcb6aeec5" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jul 20 11:32:19 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jul 21 11:21:20 2016 +0100" }, "message": "Move caller-saves saving/restoring to ReadBarrierMarkRegX.\n\nInstead of saving/restoring live caller-save registers\nbefore/after the call to read barrier mark entry points\nReadBarrierMarkRegX, have these entry points save/restore\nall the caller-save registers themselves (except register\nrX, which contains the return value).\n\nAlso refactor the assembly code of these entry points\nusing macros.\n\n* Boot image code size variation on Nexus 5X\n (aosp_bullhead-userdebug build):\n - total ARM64 framework Oat files size change:\n 119196792 bytes -\u003e 115575920 bytes (-3.04%)\n - total ARM framework Oat files size change:\n 100435212 bytes -\u003e 97621188 bytes (-2.80%)\n\n* Benchmarks (ARM64) score variations on Nexus 5X\n (aosp_bullhead-userdebug build):\n - RitzPerf (lower is better)\n - average score difference: -2.71%\n - CaffeineMark (higher is better)\n - no real difference for most tests\n (absolute variation lower than 1%)\n - better score on the \"Method\" benchmark:\n score variation 41253 -\u003e 44891 (+8.82%)\n\nTest: ART host and target (ARM, ARM64) tests.\nBug: 29506760\nBug: 12687968\nChange-Id: I881bf73139a3f1c2bee9ffc6fc8c00f9a392afa6\n" }, { "commit": "6740997e6934bbca27d5830a32352d82aabbd38b", "tree": "684ab2e46ddeaaf251fb6919bf64295810e46afa", "parents": [ "dc4f4d42aa1712a7ac2e4c24c0aebe58b71ae2c0" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jul 19 22:34:53 2016 -0700" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jul 20 11:44:25 2016 +0100" }, "message": "ART: Change return types of field access entrypoints\n\nEnsure that return types guarantee full-width data as the compiled\ncode and mterp expect by using size_t and ssize_t.\n\nThis fixes Clang no longer sign-/zero-extending small return types.\n\nBug: 30232671\nTest: m ART_TEST_RUN_TEST_NDEBUG\u003dtrue ART_TEST_INTERPRETER\u003dtrue test-art-host-run-test\nChange-Id: Ic505befc6c94e2dccbc8abf2b13d4c2d662e68d1\n" }, { "commit": "011dc2c4b9f3a064cba801679aedd3251fe191e3", "tree": "08924388d8a91759c8aa7acfc1bc53153605e4df", "parents": [ "4c489f48ef432126b8e7a84b61c1c13a7514c085" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Mon Jul 18 11:11:45 2016 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Mon Jul 18 15:02:27 2016 -0700" }, "message": "Do allocation fence before pushing on allocation stack\n\nHeap::VisitObjects relies on having valid classes for objects in\nthe allocation stack. If the writes reorder, the thread calling\nVisitObjects could see the free list pointer instead of the class\nof the object. I believe this is causing crashes in VisitObjects.\n\nBug: 28790624\n\nTest: Volantis booted\n\nChange-Id: I0f2d4097de1ef3f5caf670ecc977d4d6837872ca\n" }, { "commit": "02b75806a80f8b75c3d6ba2ff97c995117630f36", "tree": "ecdb1852c3e33f120110091cc2d07a9737fbd3b5", "parents": [ "5f485719b166ceb8e591329d40e76c5e50988022" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jul 13 11:54:35 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jul 13 11:54:35 2016 +0100" }, "message": "Introduce more compact ReadBarrierMark slow-paths.\n\nReplace entry point ReadBarrierMark with 32\nReadBarrierMarkRegX entry points, using register\nnumber X as input and output (instead of the standard\nruntime calling convention) to save two moves in Baker\u0027s\nread barrier mark slow-path code.\n\nTest: ART host and target (ARM, ARM64) tests.\nBug: 29506760\nBug: 12687968\nChange-Id: I73cfb82831cf040b8b018e984163c865cc44ed87\n" }, { "commit": "7d14037d259c4f0adadd97adab11b36cb7f2fd18", "tree": "d94443ad3b7ea951335b7db1fc897f2d99e3d392", "parents": [ "59313b203568253eda1f394e5e0d1912e1ff8fb9", "0e5ff796e3ab641581aeea4ad53f88594fad7797" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jul 08 11:19:03 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jul 08 11:19:03 2016 +0000" }, "message": "Merge \"Mark ReadBarrierJni as a direct entry point on MIPS32.\"" }, { "commit": "c96b0b00ade5145096e86c94b3ed5854bd0abfdb", "tree": "f6d9d057c9c55a7ef8de4afc29635f3cb550128b", "parents": [ "94aaec95445ac06ed5ec065a7e21ddd752652cee", "a7821bffd3aba0705144059c30ba0fef4a400e3d" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jul 06 13:20:52 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jul 06 13:20:52 2016 +0000" }, "message": "Merge \"Fix stack alignment in x86 read barrier entry points.\"" }, { "commit": "0e5ff796e3ab641581aeea4ad53f88594fad7797", "tree": "d5dee2e26c5c3a9897c6d1dcedd01103479eb8c9", "parents": [ "74c0d1bb67f9c6ee8306f0318ab7251d56dc99d6" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jul 06 13:45:52 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jul 06 13:50:33 2016 +0100" }, "message": "Mark ReadBarrierJni as a direct entry point on MIPS32.\n\nThe ReadBarrierJni MIPS32 entry point is a direct reference\nto the native (C++) method art::ReadBarrierJni.\n\nTest: Build ART for MIPS32.\nBug: 12687968\nChange-Id: I6475855f4696690a681f69931618a055be65a00a\n" }, { "commit": "ed22d481c12f1e03ea2ce78a0ce71f9d219892ee", "tree": "54f510fad4e6c1d8ba955bf5d5bfe43fb6aab83b", "parents": [ "74c0d1bb67f9c6ee8306f0318ab7251d56dc99d6", "aaeef5ed498f83125a54ef1cf2d044d2872f888f" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jul 06 09:35:26 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jul 06 09:35:26 2016 +0000" }, "message": "Merge \"Remove stray end of macro.\"" }, { "commit": "aaeef5ed498f83125a54ef1cf2d044d2872f888f", "tree": "e6120dcd2b24c41dafafc719794e7f01fb920a61", "parents": [ "1fdb340de4e608a88e8683c857cad5d0da2c16de" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jul 05 18:43:51 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jul 05 18:43:51 2016 +0100" }, "message": "Remove stray end of macro.\n\nThese lines used to be part of the definition of\nSETUP_REFS_ONLY_CALLEE_SAVE_FRAME_PRESERVE_RTEMP2,\nwhich has been deleted.\n\nTest: ART target (ARM) tests.\nBug: 29259539\nChange-Id: I4eda77cb739e58d387ffab61a127dc7bc24e2374\n" }, { "commit": "74c0d1bb67f9c6ee8306f0318ab7251d56dc99d6", "tree": "38ce4ec6ab0ae5ed99f16c695441135fd36d26dd", "parents": [ "f7ba875851ba537237ca797f7dcdbca064e87c34", "c42a4d5973c27f192b4fd144d742e277545f96be" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Jul 05 10:10:25 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jul 05 10:10:25 2016 +0000" }, "message": "Merge \"MIPS32: Fix MipsInstructionSetFeatures::FromVariant()\"" }, { "commit": "5d45e8f13366b27c1c6ccc203e8e06ceb22c9e99", "tree": "d5f684c771fd20c068ddbf6426f34d41d8db60fe", "parents": [ "6e739acde3aaa1fa2ae2c226298418ee3193b32b" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Jun 30 16:40:20 2016 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Jul 01 10:02:04 2016 +0200" }, "message": "MIPS: Use $a0 instead $zero for passing faulting address\n\nAlso replaced register numbers with register names to prevent\nfuture similar errors.\n\nThis fixes following tests for MIPS32 and MIPS64:\n * 034-call-null\n * 038-inner-null\n * 046-reflect\n * 083-compiler-regressions\n * 123-compiler-regressions-mt\n * 800-smali\n\nChange-Id: I6e49cec60a9c2b0553d7e94c24553e307b70c603\n" }, { "commit": "c42a4d5973c27f192b4fd144d742e277545f96be", "tree": "a2748e27974d64fb583e79a32c219559cd408393", "parents": [ "04e5e590f4eece8bd88b36d761edd8733f5065a1" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Jun 28 16:55:04 2016 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Jun 30 14:33:51 2016 -0700" }, "message": "MIPS32: Fix MipsInstructionSetFeatures::FromVariant()\n\nMake it possible to completely override build-time instruction\nset features with the provided variant string. Add sanity checks.\nComment on the \"default\" variant behavior.\n\nTested:\n- test-art-host-gtest\n- test-art-target-gtest and test-art-target-run-test-optimizing on:\n - MIPS32R6 (2nd arch) QEMU\n - CI20 board\n\nChange-Id: I2470b7115a5b5e333e2e7a156e68c39945fb02e9\n" }, { "commit": "a7821bffd3aba0705144059c30ba0fef4a400e3d", "tree": "fca59701e204f4a0e4081346b1e396b14c47d0c2", "parents": [ "19c10147cd5f3270c8604d06c4a0e05cbc49e2f1" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jun 30 16:21:31 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jun 30 16:21:31 2016 +0100" }, "message": "Fix stack alignment in x86 read barrier entry points.\n\nTest: ART tests.\nBug: 12687968\nChange-Id: I5cbb3e8c0a012d0ea00ef2c2f9715b7e167928f0\n" }, { "commit": "5b64306ffc1d9e8fa8187bc8d003e25314d04741", "tree": "3b80b92aab3d5507e35d40457b9eae12123f8862", "parents": [ "b98a57d27672ca021f766f786b0700951084548d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 29 14:34:21 2016 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 29 14:34:21 2016 +0100" }, "message": "Fix mac build.\n\nbug:29321958\nChange-Id: Ibd51d408dd97876eb3237df5606dbe9290ca7254\n" }, { "commit": "e8e1127da3f154fae8d2eb16a94203544a182159", "tree": "930aa5bd3f4e81dcf1b27043844da55a3dcb5cc4", "parents": [ "739dc72773c5dee583a1d322f91b5abd61f9889d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jun 28 18:08:46 2016 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 29 12:31:52 2016 +0100" }, "message": "Do checks on the fault address when we think it\u0027s an NPE.\n\nbug:29321958\nChange-Id: I28f4da56eb3e0b48721d3ac41114858bc80daadb\n" }, { "commit": "4692c35c151951aa1fa901ca24bfa302a9beeacf", "tree": "8d28d7714dd7fa0ae1ff44888ae61f3c8786bfeb", "parents": [ "f6d4f6e0e61977777b7a9ca18b75bcd26e98e9f9", "87f3fcbd0db352157fc59148e94647ef21b73bce" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 21 16:18:10 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jun 21 16:18:10 2016 +0000" }, "message": "Merge \"Replace String.charAt() with HIR.\"" }, { "commit": "87f3fcbd0db352157fc59148e94647ef21b73bce", "tree": "5bdeabb246f5de86704333b3fcbccc6e9146d246", "parents": [ "b94b5706f0b8e2e1c7e1db22274f9f4bae0c4b5a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Apr 28 15:52:11 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 21 15:17:38 2016 +0100" }, "message": "Replace String.charAt() with HIR.\n\nReplace String.charAt() with HArrayLength, HBoundsCheck and\nHArrayGet. This allows GVN on the HArrayLength and BCE on\nthe HBoundsCheck as well as using the infrastructure for\nHArrayGet, i.e. better handling of constant indexes than\nthe old intrinsic and using the HArm64IntermediateAddress.\n\nBug: 28330359\nChange-Id: I32bf1da7eeafe82537a60416abf6ac412baa80dc\n" }, { "commit": "2ebef63b07a13f6bddf8ce93cdd2271b2eafbfad", "tree": "63fee45a0bcf0e70b182088f0a170f9dec32dcf4", "parents": [ "9a8620e45e6eedadaa476322841e26858d10eeee" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 21 11:24:47 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 21 12:29:00 2016 +0100" }, "message": "x86: Fix CFI info for FOUR_ARG_DOWNCALL.\n\nFollow-up to\n https://android-review.googlesource.com/237073\n\nBug: 28348339\nChange-Id: I586828acf1269a6677128a0ded48cb8039024143\n" }, { "commit": "453134813e9ba2b91622550d76ddff44a1ab48ab", "tree": "4e442dcb911462f4c25a3685eee9a9ecb45246df", "parents": [ "93f26bed246c352522ff2c3ea8a5e08093de16be", "3098c8cef67748d33366cfdd76e2713f03cce17e" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jun 15 10:38:23 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jun 15 10:38:23 2016 +0000" }, "message": "Merge \"ARM: Use GOT_PREL references for Runtime::Current().\"" }, { "commit": "eeca2b2966a24f1575b9c693b049a4c0b9b49807", "tree": "1bd6ad97e477cd70af218903b4dc7f306b1e7b1c", "parents": [ "4070f3fb514feb3f387e5cc312c148d82d4f5a60" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jun 14 17:24:51 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jun 14 17:24:51 2016 -0700" }, "message": "ART: Empty out sa_mask in ArmInstructionSetFeatures\n\nFor sdiv hardware detection by signal, empty out sa_mask.\n\nBug: 29282211\nChange-Id: I7c85273f95089fcce75319843e5921842ea6df4d\n" }, { "commit": "3098c8cef67748d33366cfdd76e2713f03cce17e", "tree": "6884fecf58b61dd01cc5fe7c39ca50b64af6c68a", "parents": [ "63e0a7d057adbe17ba0d34624d83f1120cb1162f" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 14 17:43:17 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 14 19:15:53 2016 +0100" }, "message": "ARM: Use GOT_PREL references for Runtime::Current().\n\nBug: 29259539\nChange-Id: I5039ff016403d438f496a55d4bb1775c3d67c09c\n" }, { "commit": "0f838aa279a296b5f14c231065bb2f96b02d9caf", "tree": "bfcfb623b4e57ba2b0e4c88e735447b5a6f8f7c6", "parents": [ "616723f67e253c3eba8123029b45684e1f33454e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 08 18:01:22 2016 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 09 10:36:15 2016 +0100" }, "message": "Fix FOUR_ARG_DOWNCALL assembly stubs on arm and x86.\n\nThey were creating a stack that the runtime did not understand.\n\nbug:28348339\nChange-Id: Ic03663552209beda8ff1e79db58bedc8f34d9a0e\n" }, { "commit": "3c7787fb2e197934a0e87329644384445b1d062f", "tree": "5942b3faa6b23abdccb98a2f9b9a13fa75ca6d36", "parents": [ "80fd43eead361bd3b61d646e5c8efcdd0720304d", "fba39972d99701c80bf3beb7451aca508d67593c" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue May 24 18:19:35 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue May 24 18:19:35 2016 +0000" }, "message": "Merge \"Fix misc-macro-parentheses warnings.\"" }, { "commit": "c25cbf14595799265d3d1b5bafb8dd00b91dbbc1", "tree": "3bb842edbcff3de90246eed1672c0cd1069ff17b", "parents": [ "a741785dddab1f4b79253514287860d11c5800c6" ], "author": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Mon Apr 18 09:00:11 2016 +0100" }, "committer": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Fri May 20 11:56:14 2016 +0100" }, "message": "ARM: Add new String.compareTo intrinsic.\n\nBenchmarked on Nexus6P big, little, and all cores. The new intrinsic is\nfaster than pStringCompareTo for compare lengths on [1,512], so the\nruntime call is no longer needed.\n\nChange-Id: If853b592dfc5e561ea3389b51729f37a2c89c18e\n" }, { "commit": "fba39972d99701c80bf3beb7451aca508d67593c", "tree": "0d80ecb6997290140503926b08a72e7418915526", "parents": [ "718d4e269810c17d03df909c84b2f7bbd4f61fb9" ], "author": { "name": "Chih-Hung Hsieh", "email": "chh@google.com", "time": "Wed May 11 11:26:48 2016 -0700" }, "committer": { "name": "Chih-Hung Hsieh", "email": "chh@google.com", "time": "Fri May 13 10:38:56 2016 -0700" }, "message": "Fix misc-macro-parentheses warnings.\n\n* Add parentheses to fix warnings.\n* Use NOLINT to suppress wrong clang-tidy warnings.\n\nBug: 28705665\nChange-Id: Icc8bc9b59583dee0ea17ab83e0ff0383b8599c3e\n" }, { "commit": "266f2d4d51a18a703b2d4fbfedc63eb1baaf3ffb", "tree": "91f5266174101542904ce79af11ecbe705c8c0b9", "parents": [ "60be30a353aa8515c72aa5240508128bb3ad9829", "d3a8110dcc56681d35a145c3657418b21c57852a" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon May 09 19:57:08 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon May 09 19:57:08 2016 +0000" }, "message": "Merge \"Revert \"Revert \"Assembly RegionTLAB allocation fast path for x86_64\"\"\"" }, { "commit": "c5818f6e388781cb52551c48b6d9bd941b66e942", "tree": "126184d1a314b11e135dccf0984aaade6265d562", "parents": [ "fbcf46e35eea33fa11ade68a66c5773ab16ae2e2", "1f36f411e8f51969f0af95fa60b9809656403c0a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 04 09:34:37 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed May 04 09:34:37 2016 +0000" }, "message": "Merge \"ARM64: Add new String.compareTo intrinsic.\"" }, { "commit": "1f36f411e8f51969f0af95fa60b9809656403c0a", "tree": "74518592cea0038ac518a4eac93b4315baf3c63c", "parents": [ "b324635492bb7d205beddf1a86f3f7a31e905fca" ], "author": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Thu Apr 21 11:13:45 2016 +0100" }, "committer": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Tue May 03 12:07:41 2016 +0100" }, "message": "ARM64: Add new String.compareTo intrinsic.\n\nBenchmarked on Nexus6P big, little, and all cores. The new intrinsic\nis faster than pStringCompareTo for compare lengths on [1,512], so the\nruntime call is no longer needed.\n\nChange-Id: If94bfe24d9bf4dddcca648cc0b563709fc407b34\n" }, { "commit": "764946701593bcf79560ab5aace501f915e12bae", "tree": "9e45b62c9a03892666c1e273521ecce7afa451a6", "parents": [ "c7ed09bd5d6f2c7af3bcba1c39b3f9185af68796" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Apr 29 15:04:49 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Apr 29 16:06:38 2016 -0700" }, "message": "ART: Fix Mac build\n\nFix Mac build after fc6898769ae1ef91ec3e41c0a273401213cb82cd.\n\nBug: 28423466\n\n(cherry picked from commit 4cf9adc1ed1bcbfe45c9caf944130aae7e39a4cd)\n\nChange-Id: I6942bc86f1b0819d84bced5499afb0a4d235a39e\n" }, { "commit": "c7ed09bd5d6f2c7af3bcba1c39b3f9185af68796", "tree": "bfad0c9f5236cc4d158bc0c64d5ef645ce09d283", "parents": [ "0f35e0b26d8c7738ca7b284357afa9dafb659d47" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Apr 25 20:08:55 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Apr 29 16:06:14 2016 -0700" }, "message": "ART: Log all monitor operations to systrace\n\nAdd a VLOG option (\"-verbose:systrace-locks\") to log all monitor\noperations to systrace. This requires non-fastpath thread\nentrypoints, and ATRACE tags for locking and unlocking.\n\nDo a bit of cleanup to the entrypoint initialization to share\ncommon setup.\n\nBug: 28423466\n\n(cherry picked from commit fc6898769ae1ef91ec3e41c0a273401213cb82cd)\n\nChange-Id: Ie67e4aa946ec15f8fcf8cb7134c5d3cff0119ab3\n" }, { "commit": "e42888f9df4163303244070c65d5229d3e201742", "tree": "c3c3e380ed16676186040f1da6042fc2cd58e041", "parents": [ "7f98c9a6babe3a21d84ce1f1e1273c99975a47f5" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Thu Apr 14 10:49:19 2016 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed Apr 27 12:45:30 2016 -0700" }, "message": "Write conflict tables in image\n\nAdd image sections for runtime methods and conflict tables. This\nmakes it that we do not need to fake up a length prefixed array\nfor runtime methods.\n\nReduces .art private dirty and PSS.\n\nSystem wide .art PSS goes from 32.5MB to 30.5MB after system boot.\n\nBusiness card .art private dirty goes from 588K to 504K.\n\nIncreases image size by ~100K.\n\nBug: 27906566\n\n(cherry picked from commit cda9386add68d94697449c6cb08b356747e55c21)\n\nChange-Id: I38cbe3150c3eeb385b8cad7cf93614e3980f4162\n" }, { "commit": "2bd7d2d6d92daa796ee33e70bb788d3dae1f2fc9", "tree": "05fb9863605b5e8e91864ea8466fd946da6528e2", "parents": [ "4e377e58066ccef401276d7d0985521e5e63d1fb" ], "author": { "name": "Junmo Park", "email": "junmoz.park@samsung.com", "time": "Wed Apr 27 16:51:50 2016 +0900" }, "committer": { "name": "Junmo Park", "email": "junmoz.park@samsung.com", "time": "Wed Apr 27 16:51:50 2016 +0900" }, "message": "ART: add exynos-m1 to a53 #835769 \u0026 #843419 erratum exception list\n\nExynos-M1 is custom-designed 64-bit ARM CPU and does not need this A53\nerratum handling.\n\nChange-Id: I15087b05769eb8d4f80219064549b0b45884bf7c\nSigned-off-by: Junmo Park \u003cjunmoz.park@samsung.com\u003e\n" }, { "commit": "d3a8110dcc56681d35a145c3657418b21c57852a", "tree": "ed7873ed7ede7da3bdfa08441c0f2c00f8504f4f", "parents": [ "d5e665a28e8406c11fb2114d9ab52281976ac1ae" ], "author": { "name": "Sang, Chunlei", "email": "chunlei.sang@intel.com", "time": "Mon Apr 25 10:05:07 2016 +0800" }, "committer": { "name": "Sang, Chunlei", "email": "chunlei.sang@intel.com", "time": "Mon Apr 25 10:57:07 2016 +0800" }, "message": "Revert \"Revert \"Assembly RegionTLAB allocation fast path for x86_64\"\"\n\nThis reverts commit 5ef46671f22640ae1df548aef2fc8f9a61f5ddb4.\n\nChange-Id: Ied2ed491f1ab675db300829f2bf259dbb24cdd20\n" }, { "commit": "8828030a442c343c777894d05037aded78c17aed", "tree": "8debdd46cef55a4abc9e75b30e493372366e505b", "parents": [ "f6e6331180c16c3b2d626af3179f9aa03ae511c8", "5ef46671f22640ae1df548aef2fc8f9a61f5ddb4" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Apr 22 19:51:36 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Apr 22 19:51:37 2016 +0000" }, "message": "Merge \"Revert \"Assembly RegionTLAB allocation fast path for x86_64\"\"" }, { "commit": "5ef46671f22640ae1df548aef2fc8f9a61f5ddb4", "tree": "fe71b6246b5564737a7f5ed0503706a4e8777b6c", "parents": [ "9a966cbbf195a1a4c24ff651f8056b64ffa7f715" ], "author": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Fri Apr 22 19:09:16 2016 +0000" }, "committer": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Fri Apr 22 19:09:16 2016 +0000" }, "message": "Revert \"Assembly RegionTLAB allocation fast path for x86_64\"\n\nThis reverts commit 9a966cbbf195a1a4c24ff651f8056b64ffa7f715.\n\nThe mac build breaks.\n\nChange-Id: I045ece805d42050a14e67f0c8cb3d6f3755d79f4\n" }, { "commit": "747a566ab71b1a9f226af2ca857a657053cef4ab", "tree": "4abbac49a26773b0b06636e304dbefa4ab81870b", "parents": [ "4f4a6c47ef269c68bc136f0805e5e99512d970b7", "9a966cbbf195a1a4c24ff651f8056b64ffa7f715" ], "author": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Fri Apr 22 17:51:40 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Apr 22 17:51:40 2016 +0000" }, "message": "Merge \"Assembly RegionTLAB allocation fast path for x86_64\"" }, { "commit": "bb661c0f0cb72d4bbfc2e251f6ded6949a713292", "tree": "4fe7e66f3385b1955934d3ec6f02e00bde6e13b8", "parents": [ "f7cda8088ec57ab1422f85f08df78e217a9f7094" ], "author": { "name": "Bilyan Borisov", "email": "bilyan.borisov@linaro.org", "time": "Mon Apr 04 16:27:32 2016 +0100" }, "committer": { "name": "Bilyan Borisov", "email": "bilyan.borisov@linaro.org", "time": "Fri Apr 22 13:33:30 2016 +0100" }, "message": "Refactor use of __ANDROID__ macro\n\nWe use the __ANDROID__ macro, which is provided by the toolchain, in\nnumerous places. This patch refactors the usage of this by defining a\nnew macro, ART_TARGET_ANDROID, that is being passed during build to\nART_TARGET_CFLAGS in Android.common_build.mk on the same line as\nART_TARGET. The codebase currently assumes that the existence of the\n__ANDROID__ macro implies that we are compiling art for an android\ntarget device. This is because, currently, target builds are compiled\nwith target toolchains that provide the macro, while host toolchains\ndo not. With this change this assumption is still preserved. However,\nin a future patch we will add the ability to compile art for a linux\ntarget, and in that case the ART_TARGET_ANDROID macro won\u0027t be passed\nanymore.\n\nChange-Id: I1f3a811aa735c87087d812da27fc6b08f01bad51\n" }, { "commit": "ebe4d21570a1c9a37355fe2039439f8585d163a3", "tree": "30e07dbfa6a66ea15e75a16fc6d3330ef0a9e6e0", "parents": [ "2efce70e4204e1a52769c63dac43c9d4af105751", "69cee6a161a39c2aea0088a4638135ae2d8499e5" ], "author": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Thu Apr 21 19:49:06 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 21 19:49:06 2016 +0000" }, "message": "Merge \"Revert \"Revert \"Assembly TLAB and RegionTLAB allocation fast path for x86\"\"\"" }, { "commit": "2efce70e4204e1a52769c63dac43c9d4af105751", "tree": "d812f91e3ca3d64c42d7e0d876b4559e62616406", "parents": [ "70c0f4e15797902e248e8b7aa0e013fe6d426c71", "7aa04a145e2e0d2949a1a1c7fd4c72d08d698587" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Apr 21 19:36:23 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 21 19:36:24 2016 +0000" }, "message": "Merge \"X86/X86_64: Switch to locked add from mfence\"" }, { "commit": "69cee6a161a39c2aea0088a4638135ae2d8499e5", "tree": "d470fa5a88765484c00987ca5f9e9a1c3ee28403", "parents": [ "2374e0fae984c2c7cf8517c23ecaf1e599236dd9" ], "author": { "name": "Sang, Chunlei", "email": "chunlei.sang@intel.com", "time": "Thu Apr 21 10:22:02 2016 +0800" }, "committer": { "name": "Sang, Chunlei", "email": "chunlei.sang@intel.com", "time": "Thu Apr 21 10:23:48 2016 +0800" }, "message": "Revert \"Revert \"Assembly TLAB and RegionTLAB allocation fast path for x86\"\"\n\nThis reverts commit 0cd1bf7a68bf39867b8d229a6afeb6b2c66b7acd.\n\nChange-Id: I79cae41c110343bbc1537063e1140484f2769ca2\n" }, { "commit": "9d7c524c9bd603b1df9e88132f7ea4d59dab44a3", "tree": "fb44a111581e6e6e341896cd3c76c633a774631f", "parents": [ "213120f7b06b6ffd5fa063079f3440fc5cc3e27e", "0cd1bf7a68bf39867b8d229a6afeb6b2c66b7acd" ], "author": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Thu Apr 21 00:42:14 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 21 00:42:15 2016 +0000" }, "message": "Merge \"Revert \"Assembly TLAB and RegionTLAB allocation fast path for x86\"\"" }, { "commit": "0cd1bf7a68bf39867b8d229a6afeb6b2c66b7acd", "tree": "fe71b6246b5564737a7f5ed0503706a4e8777b6c", "parents": [ "84ed7d06d5585611a067491243ab560fe5260cae" ], "author": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Wed Apr 20 23:51:25 2016 +0000" }, "committer": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Wed Apr 20 23:51:25 2016 +0000" }, "message": "Revert \"Assembly TLAB and RegionTLAB allocation fast path for x86\"\n\nThis reverts commit 84ed7d06d5585611a067491243ab560fe5260cae.\n\nThis breaks the mac build.\n\nChange-Id: I90ea0872073135c8ff2089e05b8b16985ef95773\n" }, { "commit": "213120f7b06b6ffd5fa063079f3440fc5cc3e27e", "tree": "5edbad550b8057ecb11a9c6a2bb0afe9a4012b95", "parents": [ "1878667110aeb3e289799b02bb530a050ff05390", "84ed7d06d5585611a067491243ab560fe5260cae" ], "author": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Wed Apr 20 23:14:16 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Apr 20 23:14:16 2016 +0000" }, "message": "Merge \"Assembly TLAB and RegionTLAB allocation fast path for x86\"" }, { "commit": "1878667110aeb3e289799b02bb530a050ff05390", "tree": "fb44a111581e6e6e341896cd3c76c633a774631f", "parents": [ "0b577a9a31c02ed1a7946abdad9519e0d1e11633", "8a2c62c62b3398afbac00b1cb8772ae5b53b62a3" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Apr 20 21:26:53 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Apr 20 21:26:53 2016 +0000" }, "message": "Merge \"ART: Change x86 from modify_ldt to set_thread_data\"" }, { "commit": "9a966cbbf195a1a4c24ff651f8056b64ffa7f715", "tree": "7a95e3553bd38ac872cdd5402dafefccf359e779", "parents": [ "2374e0fae984c2c7cf8517c23ecaf1e599236dd9" ], "author": { "name": "Sang, Chunlei", "email": "chunlei.sang@intel.com", "time": "Wed Apr 20 10:08:25 2016 +0800" }, "committer": { "name": "Sang, Chunlei", "email": "chunlei.sang@intel.com", "time": "Wed Apr 20 11:59:29 2016 +0800" }, "message": "Assembly RegionTLAB allocation fast path for x86_64\n\nChange-Id: If8ad7f8ac79cbc143939b96271ab9b7c2eddee75\n" }, { "commit": "84ed7d06d5585611a067491243ab560fe5260cae", "tree": "90237132c0ef69fea023ddaacb4a85abeeef7012", "parents": [ "2374e0fae984c2c7cf8517c23ecaf1e599236dd9" ], "author": { "name": "Sang, Chunlei", "email": "chunlei.sang@intel.com", "time": "Wed Apr 20 08:40:18 2016 +0800" }, "committer": { "name": "Sang, Chunlei", "email": "chunlei.sang@intel.com", "time": "Wed Apr 20 10:01:57 2016 +0800" }, "message": "Assembly TLAB and RegionTLAB allocation fast path for x86\n\nChange-Id: I63471cb1d7be5e5bb42faf782a0ebae46a9094ec\n" }, { "commit": "ab4c64b2001e0d517429ffcc03f0f354ea48a840", "tree": "6b0e6f95ff57d2d43f18d67bb83de02b0547782d", "parents": [ "dc1d10458ea2cf29fd861f32ab28e9abac0239ec" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Apr 14 11:46:58 2016 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Apr 14 11:48:14 2016 +0200" }, "message": "Fix copy-paste nit\n\nPair ENTRY and END macros.\n\nChange-Id: I17dcc61cdd02b2c26b9920e5385b6cb1420b18dd\n" }, { "commit": "7aa04a145e2e0d2949a1a1c7fd4c72d08d698587", "tree": "631554549d4b4dbde438fa0e6e636832427fe6c5", "parents": [ "4009bc645e3358d3150b7f94dd90a2c939f0fa51" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Jan 27 22:39:07 2016 -0500" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Apr 12 17:25:51 2016 -0400" }, "message": "X86/X86_64: Switch to locked add from mfence\n\nI finally received the answers about the performance of locked add vs.\nmfence for Java memory semantics. Locked add has been faster than\nmfence for all processors since the Pentium 4. Accordingly, I have made\nthe synchronization use locked add at all times, removing it from an\ninstruction set feature.\n\nAlso add support in the optimizing compiler for barrier type\nkNTStoreStore, which is used after non-temporal moves.\n\nChange-Id: Ib47c2fd64c2ff2128ad677f1f39c73444afb8e94\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "ec9a828fa4a4638d2d17124c4fa835f15c7c5589", "tree": "d6f91bc54a8216358cfc7aa62aab2a615a41160f", "parents": [ "934c5b69b1e78e22cd242c692f9ae4606799af31", "cd77378e668c5d58cf53af33f9c1ca2bf7c1108a" ], "author": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Tue Apr 12 17:33:34 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Apr 12 17:33:35 2016 +0000" }, "message": "Merge \"Assembly region TLAB allocation fast path for arm64.\"" }, { "commit": "cd77378e668c5d58cf53af33f9c1ca2bf7c1108a", "tree": "e7b6e175130430ac805cf03b57dae956b8d100b3", "parents": [ "f2197e43f42499be852a0fce2d755f25e2007be8" ], "author": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Thu Apr 07 17:18:24 2016 -0700" }, "committer": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Mon Apr 11 16:58:24 2016 -0700" }, "message": "Assembly region TLAB allocation fast path for arm64.\n\nThis is for the CC collector.\n\nShare the common fast path code with the tlab fast path code.\n\nSpeedup (on N9):\n BinaryTrees: 1235 -\u003e 443 ms (-64%)\n MemAllocTest: 1647 -\u003e 766 ms (-53%)\n\nBug: 9986565\nBug: 12687968\nChange-Id: I67049cc0b4d6508934f07d039d421ee162b330bf\n" }, { "commit": "1e24b28e89223dc4749a54582e7eaf929ca0cb5f", "tree": "d38ec1dcec77c16a51787a1d93c77a9a56114993", "parents": [ "b5a0647c2323246a9328b6eb0123df60e26d4d66", "59028d90d51a800bcea8be354d77d7be924da3a0" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Apr 11 15:45:57 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Apr 11 15:45:57 2016 +0000" }, "message": "Merge \"MIPS: Improving art_quick_imt_conflict_trampoline\"" }, { "commit": "4009bc645e3358d3150b7f94dd90a2c939f0fa51", "tree": "633b259e23785a06123984777442b56b9c6269a3", "parents": [ "dea59334a2bf9f7709fdb1874c5db6e9537bc291", "3bc13817a19e36f3833bb44624ef86800892eaad" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Apr 11 08:24:18 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Apr 11 08:24:19 2016 +0000" }, "message": "Merge \"Implement on-stack replacement for MIPS32 and MIPS64\"" }, { "commit": "8a2c62c62b3398afbac00b1cb8772ae5b53b62a3", "tree": "2b4b855620269077e8bc0f547d255061908ef8be", "parents": [ "6c5d868c94401aeb7596d5d36380b61c7ed81222" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Feb 16 15:58:20 2016 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Apr 08 10:36:10 2016 -0700" }, "message": "ART: Change x86 from modify_ldt to set_thread_data\n\nDo not use modify_ldt, so it can be deprecated.\n\nBug: 27199066\nChange-Id: Ib5fb40d4f720b697d786c5c971638fd57681d308\n" }, { "commit": "9d07e3d128ccfa0ef7670feadd424a825e447d1d", "tree": "dfb677fd75f0f297fef9bc49311cf1d22c770f56", "parents": [ "eb98c0ded592cfca8187c744393c82efd1020b2a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Mar 31 12:02:28 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Apr 04 17:50:20 2016 +0100" }, "message": "Clean up OatQuickMethodHeader after Quick removal.\n\nThis reduces the size of the pre-header by 8 bytes, reducing\noat file size and mmapped .text section size. The memory\nneeded to store a CompiledMethod by dex2oat is also reduced,\nfor 32-bit dex2oat by 8B and for 64-bit dex2oat by 16B. The\naosp_flounder-userdebug 32-bit and 64-bit boot.oat are each\nabout 1.1MiB smaller.\n\nDisable the broken StubTest.IMT, b/27991555 .\n\nChange-Id: I05fe45c28c8ffb7a0fa8b1117b969786748b1039\n" }, { "commit": "59028d90d51a800bcea8be354d77d7be924da3a0", "tree": "7e2f5057e3332661dd815d7f916ddb78c853fe6b", "parents": [ "cf0f8560f41467331427418584687830932e66ed" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Tue Mar 29 18:05:03 2016 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Apr 01 17:13:37 2016 +0200" }, "message": "MIPS: Improving art_quick_imt_conflict_trampoline\n\nThis is fixing stub_test for MIPS32 and MIPS64. This is follow up\nchange for Ie74d1c77cf73d451a1142bdc5e3683f9f84bb4e7.\n\nChange-Id: I3c53ef690aff49d7cf9ad3de3aaed9a3d2e1c6b9\n" }, { "commit": "3bc13817a19e36f3833bb44624ef86800892eaad", "tree": "92fcdaedfb24b0692ba9e67632c1de825bd0a06a", "parents": [ "5d87b29339c5301bea0bf2c3f47e520e3d7b0d16" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Tue Mar 22 17:16:05 2016 +0100" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Mar 25 15:46:06 2016 +0100" }, "message": "Implement on-stack replacement for MIPS32 and MIPS64\n\nChange-Id: I4e589f0597b597adff95e1289f20deb2eab97e9b\n" }, { "commit": "484fb9fde79c9c36d186cd2c7cfd8ad51f2ffead", "tree": "0837e06568032e088266a0b64ab56600e9c14a34", "parents": [ "2e384346d93a747e19fb74f32eba2d1e9403721f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Mar 24 14:31:30 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Mar 24 14:33:05 2016 +0000" }, "message": "Fix stub_test after semantic conflicting merge.\n\nhttps://android-review.googlesource.com/#/c/209881/ does\nnot set the ImtConflictTable when we\u0027re a AOT runtime, which the\nstub test pretends to be.\n\nChange-Id: I70e00b265e982b46b577ff19ac9272cfee45940d\n" }, { "commit": "1004faa49ff92fad27422f5acbc463b2dbe5bca5", "tree": "f60445511025f0ac7a7ad754e5f5821642949eb9", "parents": [ "3920099f578fd8015777bc3c1c7392a08b1e08e7" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 23 14:28:30 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 23 14:28:30 2016 +0000" }, "message": "Re-enable IMT stub test.\n\nbug:27794971\nChange-Id: Ief5cbb9ca4a07596a2f389e386124f9bb5323073\n" }, { "commit": "f9018b03ac0ae8e344b9efbeaa5d99e0eb8e9b60", "tree": "aa96e3618695b384cb3f83ec13f929db888feadc", "parents": [ "48e722432bb6e19df7bba02427e4a707e671af06" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Mar 22 21:47:16 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Mar 22 21:48:44 2016 +0000" }, "message": "Disable test for now.\n\nbug:27794971\nChange-Id: I31e1b2472271c6f54c9e0b7bf75fbdf7ebeba73d\n" }, { "commit": "796d63050a18f263b93ea34951a61deaecab3422", "tree": "813865c31b25ac06006e4ee3932b4e918c708c9b", "parents": [ "eecf60d51b481647c8508f22b3d6ce437773ea0c" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sun Mar 13 22:22:31 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Mar 22 15:17:58 2016 +0000" }, "message": "Add an ImtConflictTable to better resolve IMT conflicts.\n\n- Attach a ImtConflictTable to conflict runtime ArtMethod.\n- Initially 0, a new one will be created at the first hit of\n the conflict method.\n- If the assembly code does not find a target method in the table,\n we will create a new one again, copying the data from the previous\n table and adding the new mapping.\n\nImplemented for arm/arm64/x86/x64.\n\nbug:27556801\nbug:24769046\n\nChange-Id: Ie74d1c77cf73d451a1142bdc5e3683f9f84bb4e7\n" }, { "commit": "eecf60d51b481647c8508f22b3d6ce437773ea0c", "tree": "a4935e728efd1b6f3124447ed55539d9a578d73a", "parents": [ "a373a33d33b8a5b4fd0d4c35645e2e4353ebde9b", "69dd2ed448f5ebf29ff1c9ec6eb77b78e4f85a76" ], "author": { "name": "Bill Buzbee", "email": "buzbee@google.com", "time": "Tue Mar 22 11:20:32 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Mar 22 11:20:32 2016 +0000" }, "message": "Merge \"ART: remove nested include in arch_test\"" }, { "commit": "69dd2ed448f5ebf29ff1c9ec6eb77b78e4f85a76", "tree": "1d056b0559eaf4e5bca6184d86a8bec8c3faef0e", "parents": [ "6a329292736c3dd74e9c8cb319c2a233d07fe524" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon Mar 21 15:11:04 2016 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon Mar 21 15:11:04 2016 -0700" }, "message": "ART: remove nested include in arch_test\n\narch_test #includes asm_support.h while inside the art namespace.\nWe\u0027ve gotten away with this until now because the files that\nasm_support.h includes had already been included earlier (and thus,\nwere empty via the #ifdef guard). However, adding new #includes to\nasm_support.h results in art::art:: namespace ugliness.\n\nChange-Id: Ie2671c456bb631976b4280f29a5656b086138047\n" }, { "commit": "590b1362b64d7feeb688d787c1d140d9b7ca78b1", "tree": "38317f89a5b7e7a1016473acde80f7201b5eb209", "parents": [ "459898dc4470559ba1e1d578bc52a914d1f573f5" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Mon Mar 21 14:24:43 2016 +0100" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Mon Mar 21 15:36:48 2016 +0100" }, "message": "Suppress MIPS32 assembler warnings\n\nSuppressing \"no .cprestore pseudo-op used in PIC code\".\nSuppressing \"used $at without .set noat\".\nFixing some typos.\n\nChange-Id: I45267890b070cee3dd7f3708cf73e157a08f798e\n" }, { "commit": "d72945c6b18831630af8755fcf041f5a59c82cae", "tree": "413977fb152b0db8b19320431d5d620521d5751a", "parents": [ "8e57978b5f330a322f05644c2db7fa8ce89b1b46" ], "author": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Wed Mar 16 11:23:10 2016 -0700" }, "committer": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Wed Mar 16 13:54:01 2016 -0700" }, "message": "Revert \"Revert \"Assembly TLAB allocation fast path for arm64.\"\"\n\nThis reverts commit 52fa2c698b995c21940f366cf3a44204ddf4f8e9.\n\nFix the mvn instructions.\n\nBug: 9986565\nChange-Id: Ib7b2023cd54c57131442e1de85c64f40b818313d\n" }, { "commit": "52fa2c698b995c21940f366cf3a44204ddf4f8e9", "tree": "976463c15a1616b128551d32b3fdea6c8b48a3a5", "parents": [ "4344e11598b3079032773ad7e381658f39bed92e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 16 10:23:03 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 16 10:23:31 2016 +0000" }, "message": "Revert \"Assembly TLAB allocation fast path for arm64.\"\n\nAssembly code does not compile\nBug: 9986565\n\nThis reverts commit b7e52b02a82c69e59c88f06945fb21672dfe9923.\n\nChange-Id: I80de1bcd6270e2d76f79cb708811a41c039ea5bb\n" }, { "commit": "563cf332e4560601207b2d039b42f6b0fdff8ce8", "tree": "2584f2a938507b6d0fcd18915f627992f1eccfd6", "parents": [ "448f21e2c1cb43b193736598719979ebd2aed0b0" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 16 10:22:09 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 16 10:22:09 2016 +0000" }, "message": "Revert \"Tentative fix for build breakage with read barriers.\"\n\nThis reverts commit 448f21e2c1cb43b193736598719979ebd2aed0b0.\n\nChange-Id: Id821effa06697b1464581bcd9c8f34cd0ea69896\n" }, { "commit": "448f21e2c1cb43b193736598719979ebd2aed0b0", "tree": "eff0cd1fcffd7609cda6ca3018c8945aee0d2949", "parents": [ "553ed05100f079203371da55e8a9d824b8e9948e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 16 09:36:35 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 16 09:36:46 2016 +0000" }, "message": "Tentative fix for build breakage with read barriers.\n\nChange-Id: I490821357525bdeb19c330f350635bd645f8ab53\n" }, { "commit": "b7e52b02a82c69e59c88f06945fb21672dfe9923", "tree": "89700d959a34dfd18a65e98db3b4b22dde6761a0", "parents": [ "2f74be0856b56942614ec65896853a58a37b7aff" ], "author": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Wed Mar 09 21:14:41 2016 -0800" }, "committer": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Tue Mar 15 11:31:18 2016 -0700" }, "message": "Assembly TLAB allocation fast path for arm64.\n\nThis is the arm64 version of CL 187537.\n\nSpeedup (GSS GC with TLAB on N9):\n BinaryTrees: 591 -\u003e 493 ms (-17%)\n MemAllocTest: 792 -\u003e 755 ms (-5%)\n\nBug: 9986565\n\nChange-Id: Icdad28cab0fd835679c640b7eae59b33ac2d6654\n" }, { "commit": "91cdf71e166630eb5e28e02298b0ba6ed4037553", "tree": "ef47c10b5c283fa7ee194db100a18439b7f75ab6", "parents": [ "43bad209f99df82412dadab5e3b735bb12d257ab", "10d4c08c0ea9df0a85a11e1c77974df24078c0ec" ], "author": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Fri Mar 11 21:18:21 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Mar 11 21:18:21 2016 +0000" }, "message": "Merge \"Assembly region TLAB allocation fast path for arm.\"" }, { "commit": "10d4c08c0ea9df0a85a11e1c77974df24078c0ec", "tree": "6d56cd6cfdac03d6fb6a1cb66153f2179c858f49", "parents": [ "da11cef6fb6d8a9e08cb445576a50abff8773a25" ], "author": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Wed Feb 24 12:51:18 2016 -0800" }, "committer": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Fri Mar 11 13:16:55 2016 -0800" }, "message": "Assembly region TLAB allocation fast path for arm.\n\nThis is for the CC collector.\n\nShare the common fast path code with the tlab fast path code.\n\nSpeedup (on N5):\n BinaryTrees: 2291 -\u003e 902 ms (-60%)\n MemAllocTest: 2137 -\u003e 1845 ms (-14%)\n\nBug: 9986565\nBug: 12687968\n\nChange-Id: Ica63094ec2f85eaa4fd04d202a20090399275d85\n" }, { "commit": "0555c78e5015ea4f9b1c064a5c77eb693f2edbe1", "tree": "aa22b4388b129ea9628383cc5ed6157fc4e0c744", "parents": [ "59c16a91633cb2268f9a7c052f6a761d711d0184", "cf283daf579e9eda586f312c3fc89444601e2525" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Mar 10 17:09:37 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Mar 10 17:09:38 2016 +0000" }, "message": "Merge \"MIPS32: java.lang.Thread, and java.lang.String intrinsics:\"" }, { "commit": "f969a209c30e3af636342d2fb7851d82a2529bf7", "tree": "6cf14b0ef2a82f6552c497f1889f967f9f722e5f", "parents": [ "ce51701b0621754a81125df3ed62e07c0497cafd" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Mar 09 16:14:00 2016 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Mar 09 16:14:00 2016 +0000" }, "message": "Fix and enable java.lang.StringFactory intrinsics.\n\nThe following intrinsics were not considered by the\nintrinsics recognizer:\n- StringNewStringFromBytes\n- StringNewStringFromChars\n- StringNewStringFromString\nThis CL enables them and add tests for them.\n\nThis CL also:\n- Fixes the locations of the ARM64 \u0026 MIPS64\n StringNewStringFromString intrinsics.\n- Fixes the definitions of the FOUR_ARG_DOWNCALL macros on\n ARM and x86, which are used to implement the\n art_quick_alloc_string_from_bytes* runtime entry points.\n- Fixes PC info (stack maps) recording in the\n StringNewStringFromBytes, StringNewStringFromChars and\n StringNewStringFromString ARM, ARM64 \u0026 MIPS64 intrinsics.\n\nBug: 27425743\nChange-Id: I38c00d3f0b2e6b64f7d3fe9146743493bef9e45c\n" }, { "commit": "cf283daf579e9eda586f312c3fc89444601e2525", "tree": "390efcd25be46065f56ce653d86d7b4b5d99e585", "parents": [ "2f6ad55a3bfa16867146233e1eb8b822b1daab4b" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Tue Jan 19 16:45:35 2016 -0800" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Tue Mar 08 10:43:14 2016 -0800" }, "message": "MIPS32: java.lang.Thread, and java.lang.String intrinsics:\n\n- Thread java.lang.Thread.currentThread()\n- int java.lang.String.compareTo(String anotherString)\n- int java.lang.String.indexOf(int ch)\n- int java.lang.String.indexOf(int ch, int fromIndex)\n- java.lang.StringFactory.newStringFromBytes(byte[] data,\n int high,\n int offset,\n int byteCount)\n- java.lang.StringFactory.newStringFromChars(int offset,\n int charCount,\n char[] data)\n- java.lang.StringFactory.newStringFromString(String toCopy)\n\nChange-Id: I96a06ff81e1e3bf18d45760282356854efaf4945\n" }, { "commit": "7e1ce285c3c2cbd8d97c744699c2f2347fa7487b", "tree": "40d525eeda56a05576cb396a72479c366d2d463f", "parents": [ "4e4e64511e530db37b33f450016afe49db3c4b20" ], "author": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Fri Dec 11 15:46:19 2015 -0800" }, "committer": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Thu Feb 25 14:00:48 2016 -0800" }, "message": "Assembly TLAB allocation fast path for arm.\n\nSpeedup (GSS GC with TLAB on N5):\n BinaryTrees: 1872 -\u003e 796 ms (-57%)\n MemAllocTest: 2522 -\u003e 2219 ms (-12%)\n\nBug: 9986565\nChange-Id: Icb9d1259461f3abe83a4a82c8aff911937eaf57d\n" }, { "commit": "db11e7ecc9c902ffde6336c261fe236299a81944", "tree": "177fc8673b271192c86797ba64fb12557520df33", "parents": [ "f5a28f77abefc080a870869ae933106435af4232", "970e19164326d93947441f9f0c2c754225dfb6e8" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Feb 24 21:37:29 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Feb 24 21:37:29 2016 +0000" }, "message": "Merge \"Made art/runtime/arch/stub_test.cc compile with -O2 again.\"" }, { "commit": "970e19164326d93947441f9f0c2c754225dfb6e8", "tree": "2829252b919888076014bf727d396722b1c5a9dd", "parents": [ "d15ede2df7d157ea5480614fd18c2bf0d37a6c2a" ], "author": { "name": "Bilyan Borisov", "email": "bilyan.borisov@linaro.org", "time": "Wed Feb 10 11:51:17 2016 +0000" }, "committer": { "name": "Bilyan Borisov", "email": "bilyan.borisov@linaro.org", "time": "Wed Feb 24 14:49:55 2016 +0000" }, "message": "Made art/runtime/arch/stub_test.cc compile with -O2 again.\n\nThe test file art/runtime/arch/stub_test.cc wasn\u0027t compiling with -O2\nas the optimisations interacted with -fstack-protector-strong. The\naarch64 _asm_ block in the Invoke3WithReferrerAndHidden function was\nclobbering all possible registers, and clang requires at least one\nregister to be live across an _asm_ block to do the checking.\n\nThe fix was to remove a callee-saved register, x20, from the clobber\nlist of the aarch64 asm block of Invoke3WithReferrerAndHidden. The\nblock was also modified to save and restore x20 to ensure that it\nwon\u0027t be clobbered by the stubs invoked by the blr instruction. Also\nadded some comments above the clobber list.\n\nChange-Id: I03597fd2d14cf2d6e32edf02835aee2eb68bab17\n" }, { "commit": "b74353a6765447b1551b337fd76803eb6aa86b8b", "tree": "a04175cdbeef83f485c0cbe8a4265abc207780b4", "parents": [ "e33d20e321b630bcab83f6dfbfac2788d8145148" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Fri Nov 20 09:07:09 2015 -0800" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Mon Feb 22 12:42:57 2016 -0800" }, "message": "MIPS32: Implement intrinsics from java.lang.Math:\n\n- abs(double) - abs(float) - abs(int)\n- abs(long) - max(double, double) - max(float, float)\n- max(int, int) - max(long, long) - min(double, double)\n- min(float, float) - min(int, int) - min(long, long)\n- sqrt(double)\n\nThe math intrinsics:\n\n- ceil(double) - floor(double) - rint(double)\n- round(double) - round(float)\n\naren\u0027t implemented because they require instructions which only exist\nfor MIPS64, or for MIPS32r6.\n\nChange-Id: I943be3592b52a423fcb7ac40f46f38a5e2a58c50\n" }, { "commit": "d9994f069dfeaa32ba929ca78816b5b83e2a4134", "tree": "a826990f89d8f546921902933a4cc05b57196971", "parents": [ "be89a6f1d9e41b154be3fe1da97cedb6964fbd35" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Feb 11 17:35:55 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Feb 11 21:47:46 2016 +0000" }, "message": "Re-enable OSR.\n\nFixes two bugs:\n- Dealing with proxy methods, which the compiler and code cache\n does not handle.\n- Dealing with phi types, that may have been speculatively optimized\n but do not hold once jumping to the compiled code.\n\nChange-Id: I7dcd9976ef7b12128fff95d2b7ed3e69cc42e90a\n" }, { "commit": "c70646e3c75ec97648bfa7c295e4b1685895afcc", "tree": "3d2d1cfd39762cb264d34bc906f8e38e15643f31", "parents": [ "96bbc8fcac2d408e0afdcae933653198fb8bbe92", "d70dc9d824b715475d7fb3900757dba2f4d67f50" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Feb 09 18:47:23 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Feb 09 18:47:23 2016 +0000" }, "message": "Merge \"ARM: Add direct calls to math intrinsics\"" }, { "commit": "d9bc433a89c41a255d1b669d075f802597839bdc", "tree": "8a2a82b3c5457b0a778cb82d5e69b8e2ef8ee3f3", "parents": [ "e6141d7aba1078c0465294408133aaf00ae47f1b" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Feb 05 23:32:25 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Feb 05 23:32:25 2016 +0000" }, "message": "Point fixes after OSR change.\n\n- ldr -\u003e ldrb in osr stub for arm32\n- disable 570-checker-osr for tracing\n- don\u0027t osr proxy methods.\n\nChange-Id: I9c713c9b7eab86ca9beb75f228fb3b76185621ef\n" }, { "commit": "b331febbab8e916680faba722cc84b66b84218a3", "tree": "35f985b021e476914bfe91492da23fee218014a7", "parents": [ "586996afc905518ed926e4680aab67bedabec9b7" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Feb 05 16:51:53 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Feb 05 17:11:54 2016 +0000" }, "message": "Revert \"Revert \"Implement on-stack replacement for arm/arm64/x86/x86_64.\"\"\n\nThis reverts commit bd89a5c556324062b7d841843b039392e84cfaf4.\n\nChange-Id: I08d190431520baa7fcec8fbdb444519f25ac8d44\n" }, { "commit": "d70dc9d824b715475d7fb3900757dba2f4d67f50", "tree": "96c4899b0989c61470bfb899b719a63bd9d3f937", "parents": [ "85b3b52a931b54380be3753216e97431ae2215a9" ], "author": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Thu Feb 04 14:59:04 2016 +0000" }, "committer": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Thu Feb 04 17:17:32 2016 +0000" }, "message": "ARM: Add direct calls to math intrinsics\n\nThis change mirrors the work that has already been done for x86 and\nx86_64. The following functions are affected: cos, sin, acos, asin,\natan, atan2, cbrt, cosh, exp, expm1, hypot, log, log10, nextafter,\nsinh, tan, tanh.\n\nChange-Id: I476348271a4cfc2579d1ea00ba4a80430f81f0fe\n" }, { "commit": "b328291eff12b5a44b026962c17befcf3170c37b", "tree": "8c6a827f42407b8181c5b09444f41bad6dd599ba", "parents": [ "2f0f5ffcfcbe05d0fa20592294e6a12959e3dada", "982a9a818915a0a03a1b6ac6f05e01934d9d27e8" ], "author": { "name": "Hans Boehm", "email": "hboehm@google.com", "time": "Tue Feb 02 23:11:14 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Feb 02 23:11:14 2016 +0000" }, "message": "Merge \"Rosalloc fast path in assembly for MIPS64\"" }, { "commit": "5f16c05407ed5f7f72fa761263fd5eac37de0077", "tree": "69983c047840a25851ad570eb838675284ccaa56", "parents": [ "b86f963ce95b25bfae892fa425ab02f2fb706f87", "4a6a67ca93289b232a620bdf8bf30ff8b7b0b428" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Feb 02 14:36:58 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Feb 02 14:36:58 2016 +0000" }, "message": "Merge \"Remove unused DMB code paths in the ARM64 Optimizing Compiler\"" }, { "commit": "02fc24ea55aa71a352e64d6878ee3bace6050da1", "tree": "21716366702da084a2743a23f20349e33b97e995", "parents": [ "909147a304500737824de5e1feab135560881e86" ], "author": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Wed Jan 20 16:48:19 2016 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Feb 02 11:51:42 2016 +0000" }, "message": "ARM64: Add direct calls to math intrinsics\n\nThis change mirrors the work that has already been done for x86 and\nx86_64. The following functions are affected: cos, sin, acos, asin,\natan, atan2, cbrt, cosh, exp, expm1, hypot, log, log10, nextafter,\nsinh, tan, tanh.\n\nChange-Id: I0f381bd2c1c4273b243c045107110fed551c6124\nSigned-off-by: Anton Kirilov \u003canton.kirilov@linaro.org\u003e\n" }, { "commit": "d967266cdfc8011c81ba6e9857a247c4a73bd0fc", "tree": "7bf469b0656c4819921799d814b2ca7a4f1705be", "parents": [ "ba5ea7003f071f85936ee351aff46f64a56ee096" ], "author": { "name": "Lazar Trsic", "email": "Lazar.Trsic@imgtec.com", "time": "Thu Sep 03 17:33:01 2015 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Jan 29 17:38:06 2016 +0100" }, "message": "MIPS64: Remove unaligned memory access from art generated code\n\nUnaligned memory access was caused by sd, ld, ldc1 and sdc1\ninstructions. Check if offset is unaligned and replace it\nwith two 32 bit memory accesses, if so.\n\nAdded assembler tests for new instructions, as well as assembler\ntests for LoadFromOffset, LoadFpuFromOffset, StoreToOffset and\nStoreFpuToOffset.\n\nChange-Id: I0228a4a2ce6c801eeb5b46952b8330e14468deb3\n" }, { "commit": "4a6a67ca93289b232a620bdf8bf30ff8b7b0b428", "tree": "54e8c8fad3de00a8edd2fb8766bdfb0e2b6fc533", "parents": [ "2aaf58e90c9229610b2a16644e9866b6741ce9ca" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Wed Jan 27 09:19:56 2016 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Wed Jan 27 21:24:08 2016 +0000" }, "message": "Remove unused DMB code paths in the ARM64 Optimizing Compiler\n\nCurrently all ARM64 CPUs will be using the acquire-release code paths.\nThis patch removes the instruction set feature PreferAcquireRelease()\nas well as all the unused DMB code paths.\n\nChange-Id: I61c320d6d685f96c9e260f25eac3593907793830\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@linaro.org\u003e\n" }, { "commit": "982a9a818915a0a03a1b6ac6f05e01934d9d27e8", "tree": "87853cfe764550594e354a8c0b31506fbcc35cdb", "parents": [ "60edf5cd5f563cbde69821796159db889c362c5b" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Mon Dec 21 12:00:54 2015 +0100" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Jan 27 18:30:13 2016 +0100" }, "message": "Rosalloc fast path in assembly for MIPS64\n\nChange-Id: I93c49a8b45365aacfd7825bdd841f39d7059a967\n" }, { "commit": "715d06b4498af3d4661e0090d606641d65040a08", "tree": "b795c976f33156631bef70fe6362b6eefc529ce2", "parents": [ "48dfaba75f564c58af1d29b676a5fe1b52a536dd" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Jan 21 15:52:58 2016 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Jan 21 16:41:41 2016 -0800" }, "message": "Fix cpu-info/cpp-defines mismatch.\n\nRationale:\n__POPCNT__ is the right way to cpp-test for popcnt support\n\nChange-Id: I3dac215f862701e04519e89ca97c159b1e4385c8\n" }, { "commit": "3f67e692860d281858485d48a4f1f81b907f1444", "tree": "a14d3bdc1416dc3db74983d34a408a8b48cbce9c", "parents": [ "6aadaef35ea52506db61e463910c2520b702ca5e" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Jan 15 14:35:12 2016 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Jan 20 20:14:00 2016 -0800" }, "message": "Implemented BitCount as an intrinsic. With unit test.\n\nRationale:\nRecognizing this important operation as an intrinsic has\nvarious advantages:\n(1) having the no-side-effects/no-throw allows for\n much more GVN/LICM/BCE.\n(2) Some architectures, like x86_64, provide direct\n support for this operation.\n\nPerformance improvements on X86_64:\nCheckersEvalBench (32-bit bitboard): 27,210KNS -\u003e 36,798KNS \u003d + 35%\nReversiEvalBench (64-bit bitboard): 52,562KNS -\u003e 89,086KNS \u003d + 69%\n\nChange-Id: I65d549b0469b7909b12c6611cdc34a8640a5751f\n" }, { "commit": "745f3cdbdabfcd251a61a6819a0c391e3d8db260", "tree": "99b3c24608b8dd578091fe17b0f7f0b8ca4800b3", "parents": [ "e1b0f475e851072d0083faf6e07d274e9f1fe6a5" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Jan 15 14:08:47 2016 +0100" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Jan 15 15:19:49 2016 +0100" }, "message": "MIPS64: Fix stub_test in a proper way\n\nThis reverts commit dc2388f9e7929faecaea9446c6ebd522445ac915 and\nfixes stub_test in a proper way. Register names $12-$15 has been\nused in the clobber list instead aliases t0-t3 because they are\nambiguous.\n\nChange-Id: Idf8c866267a169c00046cc0a8191ec9712a5f937\n" } ], "next": "f5b84ee14a3bc578f799a39dca1ae512b49356ea" }