)]}'
{
  "log": [
    {
      "commit": "a2ebdd74eb2f36e6efa7a482bc11c7b93d97c2c3",
      "tree": "2d63c98a1f729f1e17969bfbc4b7dc1da48f4567",
      "parents": [
        "11f9d2130e938511efceb6d2a4793cee7dfdde35"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sun Mar 04 14:57:06 2012 -0800"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sun Mar 04 15:00:36 2012 -0800"
      },
      "message": "Complete MIPS code generation support\n\nWith this CL code generation for MIPS is complete (though untested on\nactual hardware).  Core and the boot classpath compile without issue.\n\nThe primary thrust here was to support expanding of short branch\nsequences to long form during assembly if the displacement field overflowed.\nThat led to a general cleanup of creation on LIR nodes outside of the\nnormal flow.\n\nAlso introduced is a README to describe the state of MIPS support, as well\nas memory barrier handling.\n\nChange-Id: I251a2ef8d74bc7183406dce9493464be24a9d7f7\n"
    },
    {
      "commit": "c5159d55ca8e9022b748176f9f53676e8e9d4cd2",
      "tree": "d407a682788fbbca4dbd0821350058a3c2901617",
      "parents": [
        "5b455485c1deda58959fdc410050e01448c032c2"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sat Mar 03 11:48:39 2012 -0800"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sat Mar 03 16:32:24 2012 -0800"
      },
      "message": "MIPS switch table support\n\nAnd 64-bit neg/add/sub (ouch! Mips has no carry bit...)\n\nChange-Id: Ifb94324a0052d6069977fb8f22679b95890445d8\n"
    },
    {
      "commit": "0398c42cd64682d18120a26c6c39b193fdf97658",
      "tree": "f5a60c8bca5d4acd7b31d21239f3c74bf7c7d42c",
      "parents": [
        "82488f563e7f72f8c626052893c1792d76ab3faf"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Fri Mar 02 15:22:47 2012 -0800"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Fri Mar 02 15:22:47 2012 -0800"
      },
      "message": "More MIPS support\n\nWorking through the unimps.\n\nChange-Id: Ie088d2061ca9a77f42ebd75e2936159465deed10\n"
    },
    {
      "commit": "82488f563e7f72f8c626052893c1792d76ab3faf",
      "tree": "e17e3bc62adf8b57bfeb86a3a879dfb099d3d1d7",
      "parents": [
        "013b6f296ff7c0cb6aa5aeb6868df05995eeadb7"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Fri Mar 02 08:20:26 2012 -0800"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Fri Mar 02 13:02:52 2012 -0800"
      },
      "message": "Multi-target Codegen cleanup\n\nTrying to get a bit more consistent in the abstraction layer\nnaming:\n\n     genXXX   -\u003e high-level codegen, for ex: genIGet()\n     opXXX    -\u003e instruction-level output, for ex: opRegImm()\n\nAlso more fleshing out of the Mips codegen support.\n\nChange-Id: Iafdf397cbb5015bfe3aa2c38680d96c7c05f8bc4\n"
    },
    {
      "commit": "71ac99485e79ad7eb1ba3ea2d404d53bb5784c13",
      "tree": "1a3a853d1b3b64f3d99b4b8f8dd9d2f85cd13d92",
      "parents": [
        "5de3494e4297c0d480409da3fecee39173f1d4e1"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Thu Mar 01 17:23:10 2012 -0800"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Thu Mar 01 17:23:10 2012 -0800"
      },
      "message": "Change assembler to use byte instruction lengths\n\nChange the Arm \u0026 Mips instruction templaces to record instruction\nsize in bytes rather than half-words.  Also includes a few Mips\nchanges to get us in compilable state.\n\nChange-Id: I5a4f6cbd0cb0569805d9dfbd341c244152e59ac7\n"
    },
    {
      "commit": "5de3494e4297c0d480409da3fecee39173f1d4e1",
      "tree": "269cd3447925d0b474d47fb056da4730f288ee12",
      "parents": [
        "6edfde4ae89f3a16d22ca82c928a5dd420e9fce9"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Thu Mar 01 14:51:57 2012 -0800"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Thu Mar 01 16:43:54 2012 -0800"
      },
      "message": "Another step towards a Mips target\n\nUpdating the MIPS target to use the now common codegen routines.\nStill much to do, but the general structure is sufficient to allow\nwork to begin on the other target.\n\nChange-Id: I0d288fdfb59c8e76fad73185fdd56b345e87b604\n"
    },
    {
      "commit": "31a4a6f5717f645da6b97ccc1e420ae1e1c71ce0",
      "tree": "de07c7175bcda6c2e3f11329d72d142319354f3f",
      "parents": [
        "32c9a2decebe7b736e1f05b53b5822affea5e81d"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Tue Feb 28 15:36:15 2012 -0800"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Wed Feb 29 18:52:47 2012 -0800"
      },
      "message": "More target-independence\n\nContinuing to move target-specific code from the Arm\ncode generator into the independent realm.  This will be\ndone in multiple small steps.\n\nIn this CL, the focus is on unifying the LIR data structure and\nvarious enums that don\u0027t really need to be target specific. Also\ncreates two new shared source files: GenCommon.cc (to hold\ntop-level code generation functions) and GenInvoke.cc (which\nis likely to be shared only by the Arm and Mips targets).\n\nAlso added is a makefile hack to build for Mips (which we\u0027ll\neventually remove when the compiler support multiple targets\nvia the command line) and various minor cleanups.\n\nOverall, this CL moves more than 3,000 lines of code from\ntarget dependent to target independent.\n\nChange-Id: I431ca4ae728100ed7d0e9d83a966a3f789f731b1\n"
    },
    {
      "commit": "e3acd07f28d5625062b599c2817cb5f7a53f54a9",
      "tree": "d38696b0235dab5d8ef791cdb9fb311a6705e03b",
      "parents": [
        "55b796c6f1fdc36494463a3deeb1e248800695e9"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sat Feb 25 17:03:10 2012 -0800"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sun Feb 26 20:44:46 2012 -0800"
      },
      "message": "Multi-target support\n\nThis CL represents a step towards splitting out the target dependent\nand target independent portions of the compiler, and also adds in the\nbeginning of a MIPS compiler based on the MIPS AOSP Jit submission.\n\nMore polish is clearly needed, but the split is here probably pretty\nclose.  The MIPS code will not compile at this point (and there is no\nmakefile target at present), but it\u0027s pretty close.\n\nThere should be no changes in functionality of the Arm compiler in this\nCL - just moved stuff around.\n\nChange-Id: Ia66b2847e22644a1ec63e66bf5f2fee722f963d4\n"
    }
  ]
}