)]}'
{
  "log": [
    {
      "commit": "0700b69cb0c81c3590726be7fbe5b98531cec76b",
      "tree": "9699ae3c78a2c7546918ba03aa43b0306d4f48a5",
      "parents": [
        "6194403a984dd814f01e6f7c6b270342d760388d"
      ],
      "author": {
        "name": "Raphael Gault",
        "email": "raphael.gault@linaro.org",
        "time": "Wed Sep 30 08:33:10 2020 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Sep 06 08:58:50 2021 +0000"
      },
      "message": "SVE: Extract Intermediate Address for SVE Vector Memory Operations\n\nThis patch introduces an optimization that extracts and factorizes\nthe \"base + offset\" common part for the address computation when\nperforming an SVE vector memory operation (VecStore/VecLoad).\n\nWith SVE enabled by default:\n\nTest: ./art/test.py --simulate-arm64 --run-test --optimizing \\\n(With the VIXL simulator patch)\n\nTest: ./art/test.py --target --64 --optimizing \\\n(On Arm FVP with SVE - See steps in test/README.arm_fvp.md)\n\nTest: 527-checker-array-access, 655-checker-simd-arm.\n\nChange-Id: Icd49e57d5550d1530445a94e5d49e217a999d06d\n"
    },
    {
      "commit": "8ba4de1a5684686447a578bdc425321fd3bccca6",
      "tree": "20c24450b24950266ccc235306e3ad2109c57497",
      "parents": [
        "32bf6d39bc020cacfc655ce60630f4a0da3b45cf"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Wed Dec 04 21:10:23 2019 +0000"
      },
      "committer": {
        "name": "Ulyana Trafimovich",
        "email": "skvadrik@google.com",
        "time": "Thu Feb 04 06:16:33 2021 +0000"
      },
      "message": "ART: Implement predicated SIMD vectorization.\n\nThis CL brings support for predicated execution for\nauto-vectorizer and implements arm64 SVE vector backend.\n\nThis version passes all the VIXL simulator-runnable tests in\nSVE mode with checker off (as all VecOp CHECKs need to be\nadjusted for an extra input) and all tests in NEON mode.\n\nTest: art SIMD tests on VIXL simulator.\nTest: art tests on FVP (steps in test/README.arm_fvp.md)\n\nChange-Id: Ib78bde31a15e6713d875d6668ad4458f5519605f\n"
    },
    {
      "commit": "3d190c0f01071c5c402a96ac77ef07d20291405a",
      "tree": "c99b356725b7474448ae2c14d7bbe0e491c0cd15",
      "parents": [
        "86c8752f64629325026945cd4eabd1dcea224acb"
      ],
      "author": {
        "name": "Evgeny Astigeevich",
        "email": "evgeny.astigeevich@linaro.org",
        "time": "Wed Jun 17 15:37:02 2020 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Jun 19 11:32:38 2020 +0000"
      },
      "message": "ART: Transform Sub+Sub into Sub+Add to merge Shl\n\nIn the instruction sequence like the following:\n  t1 \u003d Shl(a, n)\n  t2 \u003d Sub(t1, *)\n  r  \u003d Sub(*, t2)\nShl cannot be merged with Sub. However it can be done when the first Sub\noperands are reordered and the second Sub is replaced with Add:\n  t1 \u003d Shl(a, n)\n  t2 \u003d Sub(*, t1)\n  r  \u003d Add(*, t2)\n\nThis CL implements this transformation in the ARM/ARM64 instruction simplifiers.\n\nTest: 411-checker-instruct-simplifier-hrem\nTest: test.py --host --optimizing --jit --gtest --interpreter\nTest: test.py --target --optimizing --jit --interpreter\nTest: run-gtests.sh\nChange-Id: I24fde29d307f3ad53a8df8bbafe945b4f733ce6c\n"
    },
    {
      "commit": "0a51605ddd81635135463dab08b6f7c21b58ffb0",
      "tree": "820f338333010f4d6e4b543ffea47e9ff7d2dd3f",
      "parents": [
        "e2727154f25e0db9a5bb92af494d8e47b181dfcf"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Oct 14 13:00:44 2019 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Oct 14 13:00:44 2019 +0000"
      },
      "message": "Revert \"Make compiler/optimizing/ symbols hidden.\"\n\nThis reverts commit e2727154f25e0db9a5bb92af494d8e47b181dfcf.\n\nReason for revert: Breaks ASAN tests (ODR violation).\nBug: 142365358\n\nChange-Id: I38103d74a1297256c81d90872b6902ff1e9ef7a4\n"
    },
    {
      "commit": "e2727154f25e0db9a5bb92af494d8e47b181dfcf",
      "tree": "0ddc6eec3ad9508d7eb1f2b941786dd0ed7d2cd8",
      "parents": [
        "c78860b91ae07eed92f86876e7a03132adea6fcd"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Oct 10 10:46:42 2019 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Oct 14 08:22:00 2019 +0000"
      },
      "message": "Make compiler/optimizing/ symbols hidden.\n\nMake symbols in compiler/optimizing hidden by a namespace\nattribute. The unit intrinsic_objects.{h,cc} is excluded as\nit is needed by dex2oat.\n\nAs the symbols are no longer exported, gtests are now linked\nwith the static version of the libartd-compiler library.\n\nlibart-compiler.so size:\n  - before:\n    arm: 2396152\n    arm64: 3345280\n  - after:\n    arm: 2016176 (-371KiB, -15.9%)\n    arm64: 2874480 (-460KiB, -14.1%)\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nBug: 142365358\nChange-Id: I1fb04a33351f53f00b389a1642e81a68e40912a8\n"
    },
    {
      "commit": "3db70689e3e1c92344d436a8ea4265046bdef449",
      "tree": "3db08743e968062ed5bdc143233cdb3c4564696b",
      "parents": [
        "1650dafad62578a1766bd617d78458a4cf1e2a9a"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Wed Dec 26 15:12:03 2018 -0800"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Thu Dec 27 12:56:39 2018 -0800"
      },
      "message": "ART: Refactor for bugprone-argument-comment\n\nHandles compiler.\n\nBug: 116054210\nTest: WITH_TIDY\u003d1 mmma art\nChange-Id: I5cdfe73c31ac39144838a2736146b71de037425e\n"
    },
    {
      "commit": "bbc6e7edb5fca4a61ac53dd9bce79cb4f0bb3403",
      "tree": "0fbce767bc383358cf4cd65aafc74140e1850982",
      "parents": [
        "19379b58bd433da91230e4fe6cd96e7416d16adc"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Fri Aug 24 16:58:47 2018 +0100"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Tue Aug 28 11:06:07 2018 +0100"
      },
      "message": "Use \u0027final\u0027 and \u0027override\u0027 specifiers directly in ART.\n\nRemove all uses of macros \u0027FINAL\u0027 and \u0027OVERRIDE\u0027 and replace them with\n\u0027final\u0027 and \u0027override\u0027 specifiers. Remove all definitions of these\nmacros as well, which were located in these files:\n- libartbase/base/macros.h\n- test/913-heaps/heaps.cc\n- test/ti-agent/ti_macros.h\n\nART is now using C++14; the \u0027final\u0027 and \u0027override\u0027 specifiers have\nbeen introduced in C++11.\n\nTest: mmma art\nChange-Id: I256c7758155a71a2940ef2574925a44076feeebf\n"
    },
    {
      "commit": "2477320a8d9de58ede68e2645ea53c10f71dcd57",
      "tree": "f428a6856e10d8ebaff0bb2da544a8d41c35ab77",
      "parents": [
        "5a87e19e4bf1b6719c2aad3effde1b38d2c3085c"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Apr 26 10:28:51 2018 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Apr 26 10:28:51 2018 -0700"
      },
      "message": "Step 1 of 2: conditional passes.\n\nRationale:\nThe change adds a return value to Run() in preparation of\nconditional pass execution. The value returned by Run() is\nbest effort, returning false means no optimizations were\napplied or no useful information was obtained. I filled\nin a few cases with more exact information, others\nstill just return true. In addition, it integrates inlining\nas a regular pass, avoiding the ugly \"break\" into\noptimizations1 and optimziations2.\n\nBug: b/78171933, b/74026074\n\nTest: test-art-host,target\nChange-Id: Ia39c5c83c01dcd79841e4b623917d61c754cf075\n"
    },
    {
      "commit": "cd09e1f4f9902b82fa62cb2da984ea499e3b2d70",
      "tree": "535f7f75849af30b67c560804125ead95909d72b",
      "parents": [
        "72a3f1da3a300b486626b066e33280108b5ce994"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Nov 24 15:02:40 2017 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Nov 27 19:02:34 2017 +0000"
      },
      "message": "Fix stats reporting over 100% methods compiled.\n\nAdd statistics for intrinsic and native stub compilation\nand JIT failing to allocate memory for committing the\ncode. Clean up recording of compilation statistics.\n\nNew statistics when building aosp_taimen-userdebug boot\nimage with --dump-stats:\n  Attempted compilation of 94304 methods: 99.99% (94295) compiled.\n  OptStat#AttemptBytecodeCompilation: 89487\n  OptStat#AttemptIntrinsicCompilation: 160\n  OptStat#CompiledNativeStub: 4733\n  OptStat#CompiledIntrinsic: 84\n  OptStat#CompiledBytecode: 89478\n  ...\nwhere 94304\u003d89487+4733+84 and 94295\u003d89478+4733+84.\n\nTest: testrunner.py -b --host --optimizing\nTest: Manually inspect output of building boot image\n      with --dump-stats.\nBug: 69627511\nChange-Id: I15eb2b062a96f09a7721948bcc77b83ee4f18efd\n"
    },
    {
      "commit": "33bff25bcd7a02d35c54f63740eadb1a4833fc92",
      "tree": "553db4f60878acf2a0fa7036a739d406df9a29b7",
      "parents": [
        "321b3ca9a36d769283c64d4bdee0798db80af524"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Nov 01 14:35:42 2017 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Nov 02 10:11:02 2017 +0000"
      },
      "message": "ART: Make InstructionSet an enum class and add kLast.\n\nAdding InstructionSet::kLast shall make it easier to encode\nthe InstructionSet in fewer bits using BitField\u003c\u003e. However,\nintroducing `kLast` into the `art` namespace is not a good\nidea, so we change the InstructionSet to an enum class.\nThis also uncovered a case of InstructionSet::kNone being\nerroneously used instead of vixl32::Condition::None(), so\nit\u0027s good to remove `kNone` from the `art` namespace.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nChange-Id: I6fa6168dfba4ed6da86d021a69c80224f09997a6\n"
    },
    {
      "commit": "ca6fff898afcb62491458ae8bcd428bfb3043da1",
      "tree": "195a6b16d3a4b34acc2faf91ce56f448efb15e07",
      "parents": [
        "aa7273e56fbafc2692c8d20a31b50d2f4bdd2aa1"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Oct 03 14:49:14 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Oct 06 17:53:50 2017 +0100"
      },
      "message": "ART: Use ScopedArenaAllocator for pass-local data.\n\nPasses using local ArenaAllocator were hiding their memory\nusage from the allocation counting, making it difficult to\ntrack down where memory was used. Using ScopedArenaAllocator\nreveals the memory usage.\n\nThis changes the HGraph constructor which requires a lot of\nchanges in tests. Refactor these tests to limit the amount\nof work needed the next time we change that constructor.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: Build with kArenaAllocatorCountAllocations \u003d true.\nBug: 64312607\nChange-Id: I34939e4086b500d6e827ff3ef2211d1a421ac91a\n"
    },
    {
      "commit": "0f689e773c49536208d40a2e23410deea4acc184",
      "tree": "688a08e69ff658719a81a65461019e015ca4b8d8",
      "parents": [
        "cd9903db5d0cdb9664d42c11ab04954a829206c8"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Oct 02 12:38:21 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Oct 02 12:38:21 2017 +0100"
      },
      "message": "ARM/ARM64: Move simplifier visitors to .cc files.\n\nTest: Rely on TreeHugger.\nChange-Id: Ib2cad20a4d6252812aaf6fa09a576bdfca423b70\n"
    },
    {
      "commit": "0ebe0d83138bba1996e9c8007969b5381d972b32",
      "tree": "a5ee66ebc5b587ade97e56ac8fc7d832fbbed4af",
      "parents": [
        "e1e347dace0ded83774999bb26c37527dcdb1d5a"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Sep 21 22:50:39 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Sep 25 15:45:01 2017 +0100"
      },
      "message": "ART: Introduce compiler data type.\n\nReplace most uses of the runtime\u0027s Primitive in compiler\nwith a new class DataType. This prepares for introducing\nnew types, such as Uint8, that the runtime does not need\nto know about.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nBug: 23964345\nChange-Id: Iec2ad82454eec678fffcd8279a9746b90feb9b0c\n"
    },
    {
      "commit": "bc5460b850a0fa2d8dcf6c8d36b0eb86f8fe46a8",
      "tree": "0db1314987cd0f24c7294c4ad540c7f28e2739d9",
      "parents": [
        "c1bb1cd339b2ebea9c4770fb4d61bacd7d77746f"
      ],
      "author": {
        "name": "Lena Djokic",
        "email": "Lena.Djokic@imgtec.com",
        "time": "Thu Jul 20 16:07:36 2017 +0200"
      },
      "committer": {
        "name": "Goran Jakovljevic",
        "email": "Goran.Jakovljevic@imgtec.com",
        "time": "Mon Aug 14 10:16:34 2017 +0200"
      },
      "message": "MIPS: Support MultiplyAccumulate for SIMD.\n\nMoved support for multiply accumulate from arm64-specific to\ngeneral instruction simplification.\nAlso extended 550-checker-multiply-accumulate test.\n\nTest: test-art-host, test-art-target\n\nChange-Id: If113f0f0d5cb48e8a76273c919cfa2f49fce667d\n"
    },
    {
      "commit": "e1811ed6b57a54dc8ebd327e4bd2c4422092a3a0",
      "tree": "e3ce48e66190c11a8b5342f4ec0d1046ba28d788",
      "parents": [
        "7113885fcd983b33ee1e350865d21517d6297843"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu Apr 27 16:50:47 2017 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu May 11 10:06:04 2017 +0100"
      },
      "message": "ARM64: Share address computation across SIMD LDRs/STRs.\n\nFor array accesses the element address has the following structure:\nAddress \u003d CONST_OFFSET + base_addr + index \u003c\u003c ELEM_SHIFT\n\nTaking into account ARM64 LDR/STR addressing modes address part\n(CONST_OFFSET + index \u003c\u003c ELEM_SHIFT) can be shared across array\naccess with the same data type and index.\n\nFor example, for the following loop 5 accesses can share address\ncomputation:\n\nvoid foo(int[] a, int[] b, int[] c) {\n  for (i...) {\n    a[i] \u003d a[i] + 5;\n    b[i] \u003d b[i] + c[i];\n  }\n}\n\nTest: test-art-host, test-art-target\n\nChange-Id: I46af3b4e4a55004336672cdba3296b7622d815ca\n"
    },
    {
      "commit": "f34dd206d0073fb3949be872224420a8488f551f",
      "tree": "b24b451af6efdd9f67c4cbd5c37ebb4ec6a4aaad",
      "parents": [
        "1f56cb5c594f5757085820b1042988d10f02bb0b"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Mon Apr 10 17:41:46 2017 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu Apr 20 00:21:29 2017 +0100"
      },
      "message": "ARM64: Support MultiplyAccumulate for SIMD.\n\nTest: test-art-host, test-art-target.\n\nChange-Id: I06af8415e15352d09d176cae828163cbe99ae7a7\n"
    },
    {
      "commit": "74234daabb28a4b9c804bf8bf908e7334bd4d400",
      "tree": "0b60cb00ab117c1a9a4b92983514962198b548bf",
      "parents": [
        "a7e9bfafeb64b1142433a41b05ddc263cadc61e3"
      ],
      "author": {
        "name": "Anton Kirilov",
        "email": "anton.kirilov@linaro.org",
        "time": "Fri Jan 13 14:42:47 2017 +0000"
      },
      "committer": {
        "name": "Anton Kirilov",
        "email": "anton.kirilov@linaro.org",
        "time": "Fri Feb 17 14:59:27 2017 +0000"
      },
      "message": "ARM: Merge data-processing instructions and shifts/(un)signed extensions\n\nThis commit mirrors the work that has already been done for ARM64.\n\nTest: m test-art-target-run-test-551-checker-shifter-operand\nChange-Id: Iec8c1563b035f40f0e18dcffde28d91dc21922f8\n"
    },
    {
      "commit": "fdaf0f45510374d3a122fdc85d68793e2431175e",
      "tree": "3315c82410fd42612bb501bed150df454dde0dde",
      "parents": [
        "b02b8d7df48ea3314cfcb3c08d84ac9556363833"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Oct 13 19:29:53 2016 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Nov 09 11:08:31 2016 +0000"
      },
      "message": "Change string compression encoding.\n\nEncode the string compression flag as the least significant\nbit of the \"count\" field, with 0 meaning compressed and 1\nmeaning uncompressed.\n\nThe main vdex file is a tiny bit larger (+28B for prebuilt\nboot images, +32 for on-device built images) and the oat\nfile sizes change. Measured on Nexus 9, AOSP ToT, these\nchanges are insignificant when string compression is\ndisabled (-200B for the 32-bit boot*.oat for prebuilt boot\nimage, -4KiB when built on the device attributable to\nrounding, -16B for 64-bit boot*.oat for prebuilt boot image,\nno change when built on device) but with string compression\nenabled we get significant differences:\n  prebuilt multi-part boot image:\n    - 32-bit boot*.oat: -28KiB\n    - 64-bit boot*.oat: -24KiB\n  on-device built single boot image:\n    - 32-bit boot.oat: -32KiB\n    - 64-bit boot.oat: -28KiB\nThe boot image oat file overhead for string compression:\n  prebuilt multi-part boot image:\n    - 32-bit boot*.oat: before: ~80KiB after: ~52KiB\n    - 64-bit boot*.oat: before: ~116KiB after: ~92KiB\n  on-device built single boot image:\n    - 32-bit boot.oat: before: 92KiB after: 60KiB\n    - 64-bit boot.oat: before: 116KiB after: 92KiB\n\nThe differences in the SplitStringBenchmark seem to be lost\nin the noise.\n\nTest: Run ART test suite on host and Nexus 9 with Optimizing.\nTest: Run ART test suite on host and Nexus 9 with interpreter.\nTest: All of the above with string compression enabled.\nBug: 31040547\n\nChange-Id: I7570c2b700f1a31004a2d3c18b1cc30046d35a74\n"
    },
    {
      "commit": "0576575d075e97a227010b4adf74ad5c8a920bde",
      "tree": "c31eb030933e74d6d103979bcf0d1226e769eb5b",
      "parents": [
        "9e5739aaa690a8529c104f4c05035a657616c310"
      ],
      "author": {
        "name": "jessicahandojo",
        "email": "jessicahandojo@google.com",
        "time": "Fri Sep 09 19:01:32 2016 -0700"
      },
      "committer": {
        "name": "jessicahandojo",
        "email": "jessicahandojo@google.com",
        "time": "Fri Sep 30 10:51:50 2016 -0700"
      },
      "message": "String Compression for ARM and ARM64\n\nChanges on intrinsics and Code Generation on ARM and ARM64\nfor string compression feature. Currently the feature is off.\n\nThe size of boot.oat and boot.art for ARM before and after the\nchanges (feature OFF) are still. When the feature ON,\nboot.oat increased by 0.60% and boot.art decreased by 9.38%.\n\nMeanwhile for ARM64, size of boot.oat and boot.art before and\nafter changes (feature OFF) are still. When the feature ON,\nboot.oat increased by 0.48% and boot.art decreased by 6.58%.\n\nTurn feature on: runtime/mirror/string.h (kUseStringCompression \u003d true)\nruntime/asm_support.h (STRING_COMPRESSION_FEATURE 1)\n\nTest: m -j31 test-art-target\nAll tests passed both when the mirror::kUseStringCompression\nis ON and OFF.\n\nBug: 31040547\nChange-Id: I24e86b99391df33ba27df747779b648c5a820649\n"
    },
    {
      "commit": "328429ff48d06e2cad4ebdd3568ab06de916a10a",
      "tree": "6290ac8afc3e93488382727f6765f548a2cfff04",
      "parents": [
        "79e73245140f4115039a7284b3797d701f368fe6"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Wed Jul 06 16:23:04 2016 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Jul 21 09:16:43 2016 +0000"
      },
      "message": "ARM: Port instr simplification of array accesses.\n\nAfter changing the addressing mode for array accesses (in\nhttps://android-review.googlesource.com/248406) the \u0027add\u0027\ninstruction that calculates the base address for the array can be\nshared across accesses to the same array.\n\nBefore https://android-review.googlesource.com/248406:\n    add IP, r[Array], r[Index0], LSL #2\n    ldr r0, [IP, #12]\n    add IP, r[Array], r[Index1], LSL #2\n    ldr r0, [IP, #12]\n\nBefore this CL:\n    add IP. r[Array], #12\n    ldr r0, [IP, r[Index0], LSL #2]\n    add IP. r[Array], #12\n    ldr r0, [IP, r[Index1], LSL #2]\n\nAfter this CL:\n    add IP. r[Array], #12\n    ldr r0, [IP, r[Index0], LSL #2]\n    ldr r0, [IP, r[Index1], LSL #2]\n\nLink to the original optimization:\n    https://android-review.googlesource.com/#/c/127310/\n\nTest: Run ART test suite on Nexus 6.\nChange-Id: Iee26f9a0a7ca46abb90e3f60d19d22dc8dee4d8f\n"
    },
    {
      "commit": "87f3fcbd0db352157fc59148e94647ef21b73bce",
      "tree": "5bdeabb246f5de86704333b3fcbccc6e9146d246",
      "parents": [
        "b94b5706f0b8e2e1c7e1db22274f9f4bae0c4b5a"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Apr 28 15:52:11 2016 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Jun 21 15:17:38 2016 +0100"
      },
      "message": "Replace String.charAt() with HIR.\n\nReplace String.charAt() with HArrayLength, HBoundsCheck and\nHArrayGet. This allows GVN on the HArrayLength and BCE on\nthe HBoundsCheck as well as using the infrastructure for\nHArrayGet, i.e. better handling of constant indexes than\nthe old intrinsic and using the HArm64IntermediateAddress.\n\nBug: 28330359\nChange-Id: I32bf1da7eeafe82537a60416abf6ac412baa80dc\n"
    },
    {
      "commit": "46817b876ab00d6b78905b80ed12b4344c522b6c",
      "tree": "6715bee60b0682a10437866c9617cb442146aa2f",
      "parents": [
        "f59149a151ee694484e21da7b3b207920dead5a6"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Mar 29 12:21:58 2016 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Apr 19 18:33:06 2016 +0100"
      },
      "message": "Use iterators \"before\" the use node in HUserRecord\u003c\u003e.\n\nCreate a new template class IntrusiveForwardList\u003c\u003e that\nmimicks std::forward_list\u003c\u003e except that all allocations\nare handled externally. This is essentially the same as\nboost::intrusive::slist\u003c\u003e but since we\u0027re not using Boost\nwe have to reinvent the wheel.\n\nUse the new container to replace the HUseList and use the\niterators to \"before\" use nodes in HUserRecord\u003c\u003e to avoid\nthe extra pointer to the previous node which was used\nexclusively for removing nodes from the list. This reduces\nthe size of the HUseListNode by 25%, 32B to 24B in 64-bit\ncompiler, 16B to 12B in 32-bit compiler. This translates\ndirectly to overall memory savings for the 64-bit compiler\nbut due to rounding up of the arena allocations to 8B, we\ndo not get any improvement in the 32-bit compiler.\n\nCompiling the Nexus 5 boot image with the 64-bit dex2oat\non host this CL reduces the memory used for compiling the\nmost hungry method, BatteryStats.dumpLocked(), by ~3.3MiB:\n\nBefore:\n  MEM: used: 47829200, allocated: 48769120, lost: 939920\n  Number of arenas allocated: 345,\n  Number of allocations: 815492, avg size: 58\n  ...\n  UseListNode    13744640\n  ...\nAfter:\n  MEM: used: 44393040, allocated: 45361248, lost: 968208\n  Number of arenas allocated: 319,\n  Number of allocations: 815492, avg size: 54\n  ...\n  UseListNode    10308480\n  ...\n\nNote that while we do not ship the 64-bit dex2oat to the\ndevice, the JIT compilation for 64-bit processes is using\nthe 64-bit libart-compiler.\n\nBug: 28173563\nChange-Id: I985eabd4816f845372d8aaa825a1489cf9569208\n"
    },
    {
      "commit": "7fc6350f6f1ab04b52b9cd7542e0790528296cbe",
      "tree": "26a33ef7bb2e49a9b7c7d9436194a92cb447b317",
      "parents": [
        "b7f257f353b1eb2db2732939a0404c118316891d"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Tue Feb 09 17:15:29 2016 +0000"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Fri Mar 11 12:49:27 2016 +0000"
      },
      "message": "Integrate BitwiseNegated into shared framework.\n\nShare implementation between arm and arm64.\n\nChange-Id: I0dd12e772cb23b4c181fd0b1e2a447470b1d8702\n"
    },
    {
      "commit": "9ff0d205fd60cba6753a91f613b198ca2d67f04d",
      "tree": "86689672064d66d2c473045f934f948211ba0389",
      "parents": [
        "950d063395c7cecbbe372fd607468018d661a35c"
      ],
      "author": {
        "name": "Kevin Brodsky",
        "email": "kevin.brodsky@linaro.org",
        "time": "Mon Jan 11 13:43:31 2016 +0000"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Thu Feb 25 16:26:13 2016 +0000"
      },
      "message": "Optimizing: ARM64 negated bitwise operations simplification\n\nUse negated instructions on ARM64 to replace [bitwise operation + not]\npatterns, that is:\na \u0026 ~b (BIC)\na | ~b (ORN)\na ^ ~b (EON)\n\nThe simplification only happens if the Not is only used by the bitwise\noperation. It does not happen if both inputs are Not\u0027s (this should be\nhandled by a generic simplification applying De Morgan\u0027s laws).\n\nChange-Id: I0e112b23fd8b8e10f09bfeff5994508a8ff96e9c\n"
    },
    {
      "commit": "4a0dad67867f389e01a5a6c0fe381d210f687c0d",
      "tree": "91f1e70f4a2d0bd32aa7eb51e546f5330d72f772",
      "parents": [
        "d15ede2df7d157ea5480614fd18c2bf0d37a6c2a"
      ],
      "author": {
        "name": "Artem Udovichenko",
        "email": "artem.u@samsung.com",
        "time": "Tue Jan 26 12:28:31 2016 +0300"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Feb 25 10:14:30 2016 +0000"
      },
      "message": "Revert \"Revert \"ARM/ARM64: Extend support of instruction combining.\"\"\n\nThis reverts commit 6b5afdd144d2bb3bf994240797834b5666b2cf98.\n\nChange-Id: Ic27a10f02e21109503edd64e6d73d1bb0c6a8ac6\n"
    },
    {
      "commit": "6b5afdd144d2bb3bf994240797834b5666b2cf98",
      "tree": "d536cd7b3aaf55c563e82c2c522521a91b2bb953",
      "parents": [
        "debeb98aaa8950caf1a19df490f2ac9bf563075b"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jan 22 09:31:52 2016 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jan 22 09:31:52 2016 +0000"
      },
      "message": "Revert \"ARM/ARM64: Extend support of instruction combining.\"\n\nThe test fails its checker parts.\n\nThis reverts commit debeb98aaa8950caf1a19df490f2ac9bf563075b.\n\nChange-Id: I49929e15950c7814da6c411ecd2b640d12de80df\n"
    },
    {
      "commit": "debeb98aaa8950caf1a19df490f2ac9bf563075b",
      "tree": "b2a7a7cc6fb2f56d4bcc6cecaa80035668f38dc4",
      "parents": [
        "6aadaef35ea52506db61e463910c2520b702ca5e"
      ],
      "author": {
        "name": "Ilmir Usmanov",
        "email": "i.usmanov@samsung.com",
        "time": "Fri Dec 11 11:39:44 2015 +0300"
      },
      "committer": {
        "name": "Artem Udovichenko",
        "email": "artem.u@samsung.com",
        "time": "Thu Jan 21 11:07:38 2016 +0300"
      },
      "message": "ARM/ARM64: Extend support of instruction combining.\n\nCombine multiply instructions in the following way:\nARM64:\nMUL/NEG -\u003e MNEG\nARM32 (32-bit integers only):\nMUL/ADD -\u003e MLA\nMUL/SUB -\u003e MLS\n\nChange-Id: If20f2d8fb060145ab6fbceeb5a8f1a3d02e0ecdb\n"
    },
    {
      "commit": "cd3d0fb5a4c113cfdb610454d133762a2ab0e6de",
      "tree": "482d31703326300fd8c53a2ebbfe6dbf58a74448",
      "parents": [
        "8c8e997d29fadaa9bfb4007e95a8cd6cb76d6e80"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Fri Jan 15 19:26:48 2016 +0000"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Sun Jan 17 11:58:18 2016 +0000"
      },
      "message": "Do not use HArm64IntermediateAddress with read barriers.\n\nThis ARM64 instruction simplification does not yet work\ncorrectly with the read barrier compiler instrumentation.\n\nBug: 26601270\nBug: 12687968\nChange-Id: I0c3c5d0043ebd936e00984740efbae8b3025c7ca\n"
    },
    {
      "commit": "295abc1a3aec98868544dfd4e0eeab797c3d60c2",
      "tree": "8aa181253d0ab0a3d476f1a6b53eac720a903670",
      "parents": [
        "b68748929d108a534e91645733605b35efd4edad"
      ],
      "author": {
        "name": "David Brazdil",
        "email": "dbrazdil@google.com",
        "time": "Thu Dec 31 11:06:00 2015 +0000"
      },
      "committer": {
        "name": "David Brazdil",
        "email": "dbrazdil@google.com",
        "time": "Thu Dec 31 11:06:00 2015 +0000"
      },
      "message": "ART: Set RTI of HArm64IntermediateAddress\n\nChange-Id: I2145bc249cc940d7b133fd6cbbd133cc62fee187\n"
    },
    {
      "commit": "dce90b9198d523488b8f9a04dfb3834311ff3554",
      "tree": "9f4e4ffb5fae25c4f14059fd1d772726e9d96170",
      "parents": [
        "e36ae9435da21542891ceeebb3328f5066c8301e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Dec 16 09:34:21 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Dec 16 09:34:21 2015 +0000"
      },
      "message": "Revert \"ART: Set RTI of Arm64IntermediateAddress\"\n\nThis reverts commit e36ae9435da21542891ceeebb3328f5066c8301e.\n\nChange-Id: If675b02db04bee78cc95da4ed58e545da5085da1\n"
    },
    {
      "commit": "e36ae9435da21542891ceeebb3328f5066c8301e",
      "tree": "11b827c7638935b9199b5325ba0c85867d98f115",
      "parents": [
        "795accfff05abfb69f54003ee3f096ef3ff6f1e4"
      ],
      "author": {
        "name": "David Brazdil",
        "email": "dbrazdil@google.com",
        "time": "Mon Dec 14 14:25:44 2015 +0000"
      },
      "committer": {
        "name": "David Brazdil",
        "email": "dbrazdil@google.com",
        "time": "Mon Dec 14 14:25:44 2015 +0000"
      },
      "message": "ART: Set RTI of Arm64IntermediateAddress\n\nFixes the arm64 build after I7a3aee1ff66c82d64b4846611c547af17e91d260.\n\nChange-Id: Ic2c72df59e0ddbdf2edc8519a6954d078a5ef596\n"
    },
    {
      "commit": "8626b741716390a0119ffeb88b5b9fcf08e13010",
      "tree": "28d261dbb8fa3018cba8a5d829319604508ea0a1",
      "parents": [
        "0c32fdeaeda2a1e388e280da12662d1d18c834a2"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Wed Nov 25 16:28:08 2015 +0000"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Wed Nov 25 16:28:08 2015 +0000"
      },
      "message": "ARM64: Use the shifter operands.\n\nThis introduces architecture-specific instruction simplification.\nOn ARM64 we try to merge shifts and sign-extension operations into\narithmetic and logical instructions.\n\nFor example for the Java code\n\n    int res \u003d a + (b \u003c\u003c 5);\n\nwe would generate\n\n    lsl w3, w2, #5\n    add w0, w1, w3\n\nand we now generate\n\n    add w0, w1, w2, lsl #5\n\nChange-Id: Ic03bdff44a1c12e21ddff1b0513bd32a730742b7\n"
    },
    {
      "commit": "418318f4d50e0cfc2d54330d7623ee030d4d727d",
      "tree": "46afabf57409a5208be4eebf31e1dcbf63dc8fde",
      "parents": [
        "60c4c6ad2b892bb00a6016a147b1cc089ba6bcb5"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Fri Nov 20 15:55:47 2015 +0000"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Fri Nov 20 15:55:47 2015 +0000"
      },
      "message": "ARM64: Add support for multiply-accumulate.\n\nChange-Id: I88dc313df520480f3fd16bbabda27f9435d25368\n"
    },
    {
      "commit": "e6dbf48d7a549e58a3d798bbbdc391e4d091b432",
      "tree": "e9edbb884c0143a38e0b32350119999bc11b4dee",
      "parents": [
        "45513eb694fe55cf02ca6e8f0884621a6c3f6268"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Mon Oct 19 10:10:41 2015 +0100"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Mon Oct 19 10:10:41 2015 +0100"
      },
      "message": "ARM64: Instruction simplification for array accesses.\n\nHArrayGet and HArraySet with variable indexes generate two\ninstructions on arm64, like\n\n    add temp, obj, #data_offset\n    ldr out, [temp, index LSL #shift_amount]\n\nWhen we have multiple accesses to the same array, the initial `add`\ninstruction is redundant.\n\nThis patch introduces the first instruction simplification in the\narm64-specific instruction simplification pass. It splits HArrayGet\nand HArraySet using the new arm64-specific IR HIntermediateAddress.\nAfter that we run GVN again to squash the multiple occurrences of\nHIntermediateAddress.\n\nChange-Id: I2e3d12fbb07fed07b2cb2f3f47f99f5a032f8312\n"
    },
    {
      "commit": "44b9cf937836bb33139123e15ca8b586b5853268",
      "tree": "a4fe52cb53133522069f41083d118fb6abca9336",
      "parents": [
        "32f264e67afa8654a5570d38b627515fb73fc333"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Wed Aug 19 15:39:06 2015 +0100"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Wed Aug 19 15:39:06 2015 +0100"
      },
      "message": "Put in place the ARM64 instruction simplification framework.\n\nThis commit introduces and runs the empty InstructionSimplifierArm64\npass. Further commits will introduce arm64-specific transformations in\nthat pass.\n\nChange-Id: I458f8a2b15470297b87fc1f7ff85bd52155d93ef\n"
    }
  ]
}