)]}'
{
  "log": [
    {
      "commit": "ad4450e5c3ffaa9566216cc6fafbf5c11186c467",
      "tree": "eecf36e8e9d8112e765ad8840eb2d27f8d0415ab",
      "parents": [
        "f8bdd9f3a002970e4b8fdcf6fe6730116f1626c3"
      ],
      "author": {
        "name": "Zheng Xu",
        "email": "zheng.xu@arm.com",
        "time": "Fri Apr 17 18:48:56 2015 +0800"
      },
      "committer": {
        "name": "Zheng Xu",
        "email": "zheng.xu@arm.com",
        "time": "Fri Apr 17 18:54:08 2015 +0800"
      },
      "message": "Opt compiler: Implement parallel move resolver without using swap.\n\nThe algorithm of ParallelMoveResolverNoSwap() is almost the same with\nParallelMoveResolverWithSwap(), except the way we resolve the circular\ndependency. NoSwap() uses additional scratch register to resolve the\ncircular dependency. For example, (0-\u003e1) (1-\u003e2) (2-\u003e0) will be performed\nas (2-\u003escratch) (1-\u003e2) (0-\u003e1) (scratch-\u003e0).\n\nOn architectures without swap register support, NoSwap() can reduce the\nnumber of moves from 3x(N-1) to (N+1) when there is circular dependency\nwith N moves.\n\nAnd also, NoSwap() algorithm does not depend on architecture register\nlayout information, which means it can support register pairs on arm32\nand X/W, D/S registers on arm64 without additional modification.\n\nChange-Id: Idf56bd5469bb78c0e339e43ab16387428a082318\n"
    },
    {
      "commit": "d43b3ac88cd46b8815890188c9c2b9a3f1564648",
      "tree": "6c599c3f40d57e92786bd7f41c0541d9eaa2643b",
      "parents": [
        "a109632b240f3c9355ca95500f6f48e4478e3c51"
      ],
      "author": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Wed Apr 01 14:03:04 2015 -0700"
      },
      "committer": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Wed Apr 01 14:05:13 2015 -0700"
      },
      "message": "Revert \"Revert \"Deoptimization-based bce.\"\"\n\nThis reverts commit 0ba627337274ccfb8c9cb9bf23fffb1e1b9d1430.\n\nChange-Id: I1ca10d15bbb49897a0cf541ab160431ec180a006\n"
    },
    {
      "commit": "d75948ac93a4a317feaf136cae78823071234ba5",
      "tree": "7593fb8c1ba2b67decdaa967b6348501f58d8b9d",
      "parents": [
        "b3665e3dfdd23cc7a2f17a0b53bb16205bf4151f"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Mar 27 09:53:16 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Mar 27 12:01:40 2015 +0000"
      },
      "message": "Intrinsify String.compareTo.\n\nChange-Id: Ia540df98755ac493fe61bd63f0bd94f6d97fbb57\n"
    },
    {
      "commit": "0ba627337274ccfb8c9cb9bf23fffb1e1b9d1430",
      "tree": "0e1d0813c1d8d1c7239a900c1653296975713df0",
      "parents": [
        "e295e6ec5beaea31be5d7d3c996cd8cfa2053129"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Tue Mar 24 02:39:46 2015 +0000"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Tue Mar 24 02:39:46 2015 +0000"
      },
      "message": "Revert \"Deoptimization-based bce.\"\n\nThis breaks compiling the core image:\n\n Error after BCE: art::SSAChecker: Instruction 219 in block 1 does not dominate use 221 in block 1.\n\nThis reverts commit e295e6ec5beaea31be5d7d3c996cd8cfa2053129.\n\nChange-Id: Ieeb48797d451836ed506ccb940872f1443942e4e\n"
    },
    {
      "commit": "e295e6ec5beaea31be5d7d3c996cd8cfa2053129",
      "tree": "4d8a657d23d511743ce35bee596544d7f652efdb",
      "parents": [
        "d24ba2c44c76a2b2dd13aafe8f7981c15be31a98"
      ],
      "author": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Sat Mar 07 06:37:59 2015 -0800"
      },
      "committer": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Mon Mar 23 16:39:37 2015 -0700"
      },
      "message": "Deoptimization-based bce.\n\nA mechanism is introduced that a runtime method can be called\nfrom code compiled with optimizing compiler to deoptimize into\ninterpreter. This can be used to establish invariants in the managed code\nIf the invariant does not hold at runtime, we will deoptimize and continue\nexecution in the interpreter. This allows to optimize the managed code as\nif the invariant was proven during compile time. However, the exception\nwill be thrown according to the semantics demanded by the spec.\n\nThe invariant and optimization included in this patch are based on the\nlength of an array. Given a set of array accesses with constant indices\n{c1, ..., cn}, we can optimize away all bounds checks iff all 0 \u003c\u003d min(ci) and\nmax(ci) \u003c array-length. The first can be proven statically. The second can be\nestablished with a deoptimization-based invariant. This replaces n bounds\nchecks with one invariant check (plus slow-path code).\n\nChange-Id: I8c6e34b56c85d25b91074832d13dba1db0a81569\n"
    },
    {
      "commit": "eeefa1276e83776f08704a3db4237423b0627e20",
      "tree": "d7c647ca77703f3712f567704f40b00d59a125de",
      "parents": [
        "02c0bac34c246c1bd974dbb86d292d4b52ba98e4"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Mar 13 18:52:59 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Mar 16 10:48:21 2015 +0000"
      },
      "message": "Update locations of registers after slow paths spilling.\n\nChange-Id: Id9aafcc13c1a085c17ce65d704c67b73f9de695d\n"
    },
    {
      "commit": "dc23d8318db08cb42e20f1d16dbc416798951a8b",
      "tree": "e7a883bb3263ccb971898df98bc58700604c1d1d",
      "parents": [
        "e5f5953e744060fde3b4489cea4d934d529e3e32"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Feb 16 11:15:43 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Feb 18 09:53:32 2015 +0000"
      },
      "message": "Avoid generating jmp +0.\n\nWhen a block branches to a non-following block, but blocks\nin-between do branch to it, we can avoid doing the branch.\n\nChange-Id: I9b343f662a4efc718cd4b58168f93162a24e1219\n"
    },
    {
      "commit": "2bcf9bf784a0021630d8fe63d7230d46d6891780",
      "tree": "167d773b796c5e63d84c205a8ae9a2fe3585d06a",
      "parents": [
        "61fdf5bca503c30ba1e4dcaf333a8d3299f3bde6"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Thu Jan 29 09:56:07 2015 -0800"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Mon Feb 09 13:08:39 2015 -0800"
      },
      "message": "ART: Arm intrinsics for Optimizing compiler\n\nAdd arm32 intrinsics to the optimizing compiler.\n\nChange-Id: If4aeedbf560862074d8ee08ca4484b666d6b9bf0\n"
    },
    {
      "commit": "1cf95287364948689f6a1a320567acd7728e94a3",
      "tree": "70a8b60c768894d635cf63b0a480baa5073d2bed",
      "parents": [
        "4a50662eeaa0b1a26be66e7584fb765151dabc59"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Dec 12 19:22:03 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jan 29 10:52:14 2015 +0000"
      },
      "message": "Small optimization for recursive calls: avoid dex cache.\n\nChange-Id: I044757a2f06e535cdc1480c4fc8182b89635baf6\n"
    },
    {
      "commit": "4dee636d21d9ce54386cdfbb824e5eb2a9c1af0d",
      "tree": "ee8650cc14ec18ce0d7abf089c7d2e0dfc9e079d",
      "parents": [
        "336247fa6deba2948f5ede1df806f48cf67c790a"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jan 23 18:23:14 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Sat Jan 24 14:34:01 2015 +0000"
      },
      "message": "Support callee-save registers on ARM.\n\nChange-Id: I7c519b7a828c9891b1141a8e51e12d6a8bc84118\n"
    },
    {
      "commit": "d97dc40d186aec46bfd318b6a2026a98241d7e9c",
      "tree": "5cf0257eda25e2722a1adafb9de22690c06a56d8",
      "parents": [
        "c698b78a17043d8898deb817098181595fbe734e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jan 22 13:50:01 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jan 23 09:20:42 2015 +0000"
      },
      "message": "Support callee save floating point registers on x64.\n\n- Share the computation of core_spill_mask and fpu_spill_mask\n  between backends.\n- Remove explicit stack overflow check support: we need to adjust\n  them and since they are not tested, they will easily bitrot.\n\nChange-Id: I0b619b8de4e1bdb169ea1ae7c6ede8df0d65837a\n"
    },
    {
      "commit": "988939683c26c0b1c8808fc206add6337319509a",
      "tree": "876e94428276547a29c27ccf17509a42dfe7cda1",
      "parents": [
        "59add47cabce3735ccd470cd3b5dac8b112e09ab"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 21 12:32:32 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 21 18:50:25 2015 +0000"
      },
      "message": "Enable core callee-save on x64.\n\nWill work on other architectures and FP support in other CLs.\n\nChange-Id: I8cef0343eedc7202d206f5217fdf0349035f0e4d\n"
    },
    {
      "commit": "77520bca97ec44e3758510cebd0f20e3bb4584ea",
      "tree": "2e3be6fdc182e5cf5ae390019457af5e9c1ed242",
      "parents": [
        "4d2c611bf17ff309abfa152e56c0b98a21ec8787"
      ],
      "author": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Mon Jan 12 18:45:46 2015 +0000"
      },
      "committer": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Wed Jan 21 14:26:35 2015 +0000"
      },
      "message": "Record implicit null checks at the actual invoke time.\n\nImplicitNullChecks are recorded only for instructions directly (see NB\nbelow) preceeded by NullChecks in the graph. This way we avoid recording\nredundant safepoints and minimize the code size increase.\n\nNB: ParallalelMoves might be inserted by the register allocator between\nthe NullChecks and their uses. These modify the environment and the\ncorrect action would be to reverse their modification. This will be\naddressed in a follow-up CL.\n\nChange-Id: Ie50006e5a4bd22932dcf11348f5a655d253cd898\n"
    },
    {
      "commit": "cd6dffedf1bd8e6dfb3fb0c933551f9a90f7de3f",
      "tree": "0d83e9fdf65bded684d6e836078f253e63b7e11f",
      "parents": [
        "12c03ac7575db242a6f35739bb459e8277115da4"
      ],
      "author": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Thu Jan 08 17:35:35 2015 +0000"
      },
      "committer": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Fri Jan 16 17:27:03 2015 +0000"
      },
      "message": "Add implicit null checks for the optimizing compiler\n\n- for backends: arm, arm64, x86, x86_64\n- fixed parameter passing for CodeGenerator\n- 003-omnibus-opcodes test verifies that NullPointerExceptions work as\nexpected\n\nChange-Id: I1b302acd353342504716c9169a80706cf3aba2c8\n"
    },
    {
      "commit": "c507c7f8f905f77b039e58441b2e7da20fa65342",
      "tree": "98411281496e2af2f3b001881bec8f11782131cd",
      "parents": [
        "f80dfb498451dc59e8f3375e6cf617055d3e76d1",
        "f85a9ca9859ad843dc03d3a2b600afbaf2e9bbdd"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jan 15 16:58:14 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Thu Jan 15 16:58:14 2015 +0000"
      },
      "message": "Merge \"[optimizing compiler] Compute live spill size\""
    },
    {
      "commit": "f85a9ca9859ad843dc03d3a2b600afbaf2e9bbdd",
      "tree": "a802042fa7a3a8cb820916d558e630596daaa9b4",
      "parents": [
        "8fccea249b1a6f1469eeea42c2b2cca06ce1c70d"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Tue Jan 13 09:20:58 2015 -0500"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Thu Jan 15 11:21:37 2015 -0500"
      },
      "message": "[optimizing compiler] Compute live spill size\n\nThe current stack frame calculation assumes that each live register to\nbe saved/restored has the word size of the machine.  This fails for X86,\nwhere a double in an XMM register takes up 8 bytes.  Change the\ncalculation to keep track of the number of core registers and number of\nfp registers to handle this distinction.\n\nThis is slightly pessimal, as the registers may not be active at the\nsame time, but the only way to handle this would be to allocate both\nclasses of registers simultaneously, or remember all the active\nintervals, matching them up and compute the size of each safepoint\ninterval.\n\nChange-Id: If7860aa319b625c214775347728cdf49a56946eb\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "69c15d340e7e76821bbc5d4494d4cef383774dee",
      "tree": "afea69c321ffa55e0af63a83be62eedd2b378d2f",
      "parents": [
        "603104b5b5c3759b0bc2733bda2f972686a775a3"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Jan 13 11:42:13 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Jan 13 18:11:24 2015 +0000"
      },
      "message": "Skip r1 on arm if first parameter is a long.\n\nChange-Id: I16d927ee0a0b55031ade4c92c0095fd74e18ed5b\n"
    },
    {
      "commit": "840e5461a85f8908f51e7f6cd562a9129ff0e7ce",
      "tree": "ea8b4cbc5a0e3dea96fefcd9247e6c06b17ac518",
      "parents": [
        "893e8881e31180721512c1b9e5ffacb03aad2e45"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 07 16:01:24 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jan 08 13:57:51 2015 +0000"
      },
      "message": "Implement double and float support for arm in register allocator.\n\nThe basic approach is:\n- An instruction that needs two registers gets two intervals.\n- When allocating the low part, we also allocate the high part.\n- When splitting a low (or high) interval, we also split the high\n  (or low) equivalent.\n- Allocation follows the (S/D register) requirement that low\n  registers are always even and the high equivalent is low + 1.\n\nChange-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797\n"
    },
    {
      "commit": "3416601a9e9be81bb7494864287fd3602d18ef13",
      "tree": "dd228519bfb9733aa7627b9cea81ecb28974a1ab",
      "parents": [
        "8558375377946aabbbda6ab584e13f754590bd89"
      ],
      "author": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Fri Dec 19 17:22:29 2014 +0000"
      },
      "committer": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Mon Jan 05 16:25:59 2015 +0000"
      },
      "message": "Look at instruction set features when generating volatiles code\n\nChange-Id: Ia882405719fdd60b63e4102af7e085f7cbe0bb2a\n"
    },
    {
      "commit": "52c489645b6e9ae33623f1ec24143cde5444906e",
      "tree": "a39667aa354645bd42a7a061d08ca82df3004143",
      "parents": [
        "193c7a94822f765b0b6b0cecd54c9f08dfd26425"
      ],
      "author": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Tue Dec 16 17:02:57 2014 +0000"
      },
      "committer": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Fri Dec 19 09:58:27 2014 +0000"
      },
      "message": "[optimizing compiler] Add support for volatile\n\n- for backends: arm, x86, x86_64\n- added necessary instructions to assemblies\n- clean up code gen for field set/get\n- fixed InstructionDataEquals for some instructions\n- fixed comments in compiler_enums\n\n* 003-opcode test verifies basic volatile functionality\n\nChange-Id: I144393efa312dfb2c332cb84056b00edffee338a\n"
    },
    {
      "commit": "9aec02fc5df5518c16f1e5a9b6cb198a192db973",
      "tree": "fe924b37f395af1bb50f55ee6c87c66b727f00af",
      "parents": [
        "20032e512c003a8f42735c4e1eca19c1472bb95e"
      ],
      "author": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Tue Nov 18 23:06:35 2014 +0000"
      },
      "committer": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Mon Nov 24 16:06:55 2014 +0000"
      },
      "message": "[optimizing compiler] Add shifts\n\nAdded SHL, SHR, USHR for arm, x86, x86_64.\n\nChange-Id: I971f594e270179457e6958acf1401ff7630df07e\n"
    },
    {
      "commit": "86a8d7afc7f00ff0f5ea7b8aaf4d50514250a4e6",
      "tree": "3db61320369973e463f67927a8983d7eb0d9f860",
      "parents": [
        "255a5bde2f0014dc86a564555106a4291c0867b4"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 19 08:47:18 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 19 08:47:18 2014 +0000"
      },
      "message": "Consistently use k{InstructionSet}WordSize.\n\nThese constants were defined prior to k{InstructionSet}PointerSize. So\nuse them consistently in optimizing as a first step. We can discuss\nwhether we should remove them in a second step.\n\nChange-Id: If129de1a3bb8b65f8d9c816a8ad466815fb202e6\n"
    },
    {
      "commit": "a3279c80b4f92e0cc96902cf069c09424ed94ed0",
      "tree": "2d566e00a4976fe72c54663192715f919d3fa1dd",
      "parents": [
        "a1af1b59256820dde25ec21581e9e64f698e182f",
        "f0e3937b87453234d0d7970b8712082062709b8d"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Nov 13 09:58:56 2014 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Thu Nov 13 09:58:57 2014 +0000"
      },
      "message": "Merge \"Do a parallel move in BoundsCheckSlowPath.\""
    },
    {
      "commit": "f0e3937b87453234d0d7970b8712082062709b8d",
      "tree": "e552c1173ee90fea1d2ba11cc08878efe65ba0be",
      "parents": [
        "59321e0e10ea09694efecf6154704e2743b9bffd"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 12 17:50:07 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 12 17:55:24 2014 +0000"
      },
      "message": "Do a parallel move in BoundsCheckSlowPath.\n\nThe two locations of the index and length could overlap,\nso we need a parallel move. Also factorize the code for\ndoing a parallel move based on two locations.\n\nChange-Id: Iee8b3459e2eed6704d45e9a564fb2cd050741ea4\n"
    },
    {
      "commit": "9574c4b5f5ef039d694ac12c97e25ca02eca83c0",
      "tree": "2ad3cb7ffaf3579b9ca2a7bb0d7d7e99b3c758b6",
      "parents": [
        "59321e0e10ea09694efecf6154704e2743b9bffd"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 12 13:19:37 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 12 13:55:36 2014 +0000"
      },
      "message": "Implement and/or/xor in optimizing.\n\nChange-Id: I7cf6da1fd334a7177a5580931b8f174dd40b7cec\n"
    },
    {
      "commit": "de58ab2c03ff8112b07ab827c8fa38f670dfc656",
      "tree": "c872bfbcad1e90845008140bbddcc43e56dc19d2",
      "parents": [
        "3ed86e4e98dfe1b05c9a03aa2aee42c145a018c3"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 05 12:46:03 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Nov 06 16:49:52 2014 +0000"
      },
      "message": "Implement try/catch/throw in optimizing.\n\n- We currently don\u0027t run optimizations in the presence of a try/catch.\n- We therefore implement Quick\u0027s mapping table.\n- Also fix a missing null check on array-length.\n\nChange-Id: I6917dfcb868e75c1cf6eff32b7cbb60b6cfbd68f\n"
    },
    {
      "commit": "424f676379f2f872acd1478672022f19f3240fc1",
      "tree": "bdd8fbb9c2401465d9a0536e94dec74acc8b4f3b",
      "parents": [
        "793d1023785f81eb8e29a3eb67fec17d7ee7dcbe"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Nov 03 14:51:25 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Nov 04 11:23:08 2014 +0000"
      },
      "message": "Implement CONST_CLASS in optimizing compiler.\n\nChange-Id: Ia8c8dfbef87cb2f7893bfb6e178466154eec9efd\n"
    },
    {
      "commit": "19a19cffd197a28ae4c9c3e59eff6352fd392241",
      "tree": "265b971afd0e33afc8986317aea2f5a6fe817aec",
      "parents": [
        "7c049c1f34220b0dc1a7f68f3b30f388bae7bdb9"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Oct 22 16:07:05 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Oct 29 13:01:48 2014 +0000"
      },
      "message": "Add support for static fields in optimizing compiler.\n\nChange-Id: Id2f010589e2bd6faf42c05bb33abf6816ebe9fa9\n"
    },
    {
      "commit": "1ba0f596e9e4ddd778ab431237d11baa85594eba",
      "tree": "c1d51616adf4d98aab3ebccf47ad5146635cb87f",
      "parents": [
        "1ef3495abfa2a858b3cc7a1844383c8e7dff0b60"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Oct 27 15:14:55 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Oct 27 17:20:35 2014 +0000"
      },
      "message": "Support hard float on arm in optimizing compiler.\n\nAlso bump oat version, needed after latest hard float switch.\n\nChange-Id: Idf5acfb36c07e74acff00edab998419a3c6b2965\n"
    },
    {
      "commit": "102cbed1e52b7c5f09458b44903fe97bb3e14d5f",
      "tree": "cb0a433c8f284021298c8a0c4dd0da97ca9d198a",
      "parents": [
        "07f5c5edb7ef24ac35364e6ef9a8107a44e6564e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Oct 15 18:31:05 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Oct 21 16:03:51 2014 +0100"
      },
      "message": "Implement register allocator for floating point registers.\n\nAlso:\n- Fix misuses of emitting the rex prefix in the x86_64 assembler.\n- Fix movaps code generation in the x86_64 assembler.\n\nChange-Id: Ib6dcf6e7c4a9c43368cfc46b02ba50f69ae69cbe\n"
    },
    {
      "commit": "34bacdf7eb46c0ffbf24ba7aa14a904bc9176fb2",
      "tree": "e8ed8e40c5f7896a9ac01bf7dcc2e56f40cfc804",
      "parents": [
        "7f758228f7904d2f65f06bfbd2b8ecbb8e8c6a9d"
      ],
      "author": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Tue Oct 07 20:23:36 2014 +0100"
      },
      "committer": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Fri Oct 17 11:46:45 2014 +0100"
      },
      "message": "Add multiplication for integral types\n\nThis also fixes an issue where we could allocate a pair register even if\none of its parts was already blocked.\n\nChange-Id: I4869175933409add2a56f1ccfb369c3d3dd3cb01\n"
    },
    {
      "commit": "92a73aef279be78e3c2b04db1713076183933436",
      "tree": "e73b214fb7d740588f5d065b2e4ff3eb8c527e34",
      "parents": [
        "5c5efc253507eb43265997c9afcd778f72b6cef4"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Oct 16 11:12:52 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Oct 16 15:17:44 2014 +0100"
      },
      "message": "Don\u0027t use assembler classes in code_generator.h.\n\nThe arm64 backend uses its own assembler and does not share\nthe same classes as the other backends. To avoid conflicts\nor unnecessary mappings, just don\u0027t use those classes in the\nshared part of the code generator.\n\nChange-Id: I9e5fa40c1021d2e83a4ef14c52cd1ccd03f2f73d\n"
    },
    {
      "commit": "71175b7f19a4f6cf9cc264feafd820dbafa371fb",
      "tree": "5370e7c7c9f7d1edf148a00548cb1334d5118f8d",
      "parents": [
        "b76c5495c4879fcfa0866b1490031a3123baf9ee"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Oct 09 22:13:55 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Oct 10 11:36:03 2014 +0000"
      },
      "message": "Cleanup baseline register allocator.\n\n- Use three arrays for blocking regsters instead of\n  one and computing offsets in that array.]\n- Don\u0027t pass blocked_registers_ to methods, just use the field.\n\nChange-Id: Ib698564c31127c59b5a64c80f4262394b8394dc6\n"
    },
    {
      "commit": "360231a056e796c36ffe62348507e904dc9efb9b",
      "tree": "a62ff73c11eaa6694649c98e4c2d872e89149b0c",
      "parents": [
        "2072c465cfff077da257bdf14f1f1b2690c946c8"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Oct 08 21:07:48 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Oct 09 15:21:57 2014 +0100"
      },
      "message": "Fix code generation of materialized conditions.\n\nMove the logic for knowing if a condition needs to be materialized\nin an optimization pass (so that the information does not change\nas a side effect of another optimization).\n\nAlso clean-up arm and x86_64 codegen:\n- arm: ldr and str are for power-users when a constant is\n  in play. We should use LoadFromOffset and StoreToOffset.\n- x86_64: fix misuses of movq instead of movl.\n\nChange-Id: I01a03b91803624be2281a344a13ad5efbf4f3ef3\n"
    },
    {
      "commit": "56b9ee6fe1d6880c5fca0e7feb28b25a1ded2e2f",
      "tree": "34e5163967f59a98e64f2c89489ed7b76334b48a",
      "parents": [
        "a3c4d72210de174552f47b2d117b1946f274af1e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Oct 09 11:47:51 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Oct 09 14:42:13 2014 +0100"
      },
      "message": "Stop converting from Location to ManagedRegister.\n\nNow the source of truth is the Location object that knows\nwhich register (core, pair, fpu) it needs to refer to.\n\nChange-Id: I62401343d7479ecfb24b5ed161ec7829cda5a0b1\n"
    },
    {
      "commit": "7fb49da8ec62e8a10ed9419ade9f32c6b1174687",
      "tree": "8b1bec67452b84809cecd5645543e1f885ccbd44",
      "parents": [
        "4a1b4679cda2f0d2893b8e3f910c21231849291c"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Oct 06 09:12:41 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Oct 07 20:19:47 2014 +0100"
      },
      "message": "Add support for floats and doubles.\n\n- Follows Quick conventions.\n- Currently only works with baseline register allocator.\n\nChange-Id: Ie4b8e298f4f5e1cd82364da83e4344d4fc3621a3\n"
    },
    {
      "commit": "a72cb229d555a8ca86dca748733ea3791eaeec14",
      "tree": "b051a0f2d10c126a83d22ff45f2feecf0365aca3",
      "parents": [
        "d7e2f329ddacd2294ba94cd5acde026677d32e0d",
        "3c04974a90b0e03f4b509010bff49f0b2a3da57f"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Sep 25 13:37:06 2014 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Thu Sep 25 13:37:06 2014 +0000"
      },
      "message": "Merge \"Optimize suspend checks in optimizing compiler.\""
    },
    {
      "commit": "5799fc0754da7ff2b50b472e05c65cd4ba32dda2",
      "tree": "38a4189bc2e667dfd0537b02b24a8563907898d4",
      "parents": [
        "f2476d524281c6d649f5deb6d1ccccc92380c1ed"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Thu Sep 25 12:15:20 2014 +0100"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Thu Sep 25 13:06:17 2014 +0100"
      },
      "message": "Optimizing compiler: remove unnecessary `explicit\u0027 keywords.\n\nChange-Id: I5927fd92d53308c81e14edbd6e7d1c943bfa085b\n"
    },
    {
      "commit": "3c04974a90b0e03f4b509010bff49f0b2a3da57f",
      "tree": "52649104e3e80272c3774793350f4d9f260ae732",
      "parents": [
        "c0d36abb12cdbb9469039c1dc153a586bd984015"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Sep 24 18:10:46 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Sep 25 12:23:40 2014 +0100"
      },
      "message": "Optimize suspend checks in optimizing compiler.\n\n- Remove the ones added during graph build (they were added\n  for the baseline code generator).\n- Emit them at loop back edges after phi moves, so that the test\n  can directly jump to the loop header.\n- Fix x86 and x86_64 suspend check by using cmpw instead of cmpl.\n\nChange-Id: I6fad5795a55705d86c9e1cb85bf5d63dadfafa2a\n"
    },
    {
      "commit": "3bca0df855f0e575c6ee020ed016999fc8f14122",
      "tree": "15e15c8290ad314c29ca608f51d89d4db68fd9ba",
      "parents": [
        "d41491adb23764f28a80cbb7f2bd7af6491cd892"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Sep 19 11:01:00 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Sep 23 13:57:30 2014 +0100"
      },
      "message": "Support for saving and restoring live registers in a slow path.\n\nAnd use it in suspend check slow paths.\n\nChange-Id: I79caf28f334c145a36180c79a6e2fceae3990c31\n"
    },
    {
      "commit": "e982f0b8e809cece6f460fa2d8df25873aa69de4",
      "tree": "df729d47439f7243b498dd4503a5f7aa41a4818b",
      "parents": [
        "f031724abf4f215e1627ff837f87cad5d7a25165"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Aug 13 02:11:24 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Sep 17 09:53:50 2014 +0100"
      },
      "message": "Implement invoke virtual in optimizing compiler.\n\nAlso refactor 004 tests to make them work with both Quick and\nOptimizing.\n\nChange-Id: I87e275cb0ae0258fc3bb32b612140000b1d2adf8\n"
    },
    {
      "commit": "8a16d97fb8f031822b206e65f9109a071da40563",
      "tree": "9dbbf5feaac15d2e4f54fbfc3c204fcdd6e8317a",
      "parents": [
        "c7f6b86c269727fe031146b9c18652d40916d46f"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Sep 11 10:30:02 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Sep 11 10:32:12 2014 +0100"
      },
      "message": "Fix valgrind errors.\n\nFor now just stack allocate the code generator. Will think\nabout cleaning up the root problem later (CodeGenerator being an\narena object).\n\nChange-Id: I161a6f61c5f27ea88851b446f3c1e12ee9c594d7\n"
    },
    {
      "commit": "3c7bb98698f77af10372cf31824d3bb115d9bf0f",
      "tree": "1cd4cc18babfbb16ab908f23929fa88d7678f06b",
      "parents": [
        "98cc1e552c2ccbe5d51bc81d49e79119280f5416"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jul 23 16:04:16 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Jul 28 15:44:28 2014 +0100"
      },
      "message": "Implement array get and array put in optimizing.\n\nAlso fix a couple of assembler/disassembler issues.\n\nChange-Id: I705c8572988c1a9c4df3172b304678529636d5f6\n"
    },
    {
      "commit": "96f89a290eb67d7bf4b1636798fa28df14309cc7",
      "tree": "ca2b484a18107f8253aa7774cde304586a31bc60",
      "parents": [
        "4436e926aa8e64ac7e4c4afb81f2a59b2477045a"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jul 11 10:57:49 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Jul 21 09:54:20 2014 +0100"
      },
      "message": "Add assembly operations with constants in optimizing compiler.\n\nChange-Id: I5bcc35ab50d4457186effef5592a75d7f4e5b65f\n"
    },
    {
      "commit": "8d486731559ba0c5e12c27b4a507181333702b7e",
      "tree": "78d19970d33511d6a1c54560801d5c5dcc0c47af",
      "parents": [
        "fbde4dd1cb6db729e3f3ee5bdae0cdd824d73054"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jul 16 16:23:40 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jul 16 17:55:38 2014 +0100"
      },
      "message": "Use the thumb2 assembler for the optimizing compiler.\n\nChange-Id: I2b058f4433504dc3299c06f5cb0b5ab12f34aa82\n"
    },
    {
      "commit": "ab032bc1ff57831106fdac6a91a136293609401f",
      "tree": "5891daefe635283443a255a811ab6a3f3b8a62cd",
      "parents": [
        "635561b86ac03f5562bdb779baa6db12f31b3cae"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Jul 15 12:55:21 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Jul 15 12:58:29 2014 +0100"
      },
      "message": "Fix a braino in the stack layout.\n\nAlso do some refactoring to have this code be just in CodeGenerator.\n\nChange-Id: I88de109889138af8d60027973c12a64bee813cb7\n"
    },
    {
      "commit": "e50383288a75244255d3ecedcc79ffe9caf774cb",
      "tree": "8858489463a57c7b50f7db4d972abec21302b7a7",
      "parents": [
        "cf90ba7ebe00346651f3b7ce1e5b1f785f7caabd"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jul 04 09:41:32 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Jul 14 10:06:11 2014 +0100"
      },
      "message": "Support fields in optimizing compiler.\n\n- Required support for temporaries, to be only used by baseline compiler.\n- Also fixed a few invalid assumptions around locations and instructions\n  that don\u0027t need materialization. These instructions should not have an Out.\n\nChange-Id: Idc4a30dd95dd18015137300d36bec55fc024cf62\n"
    },
    {
      "commit": "412f10cfed002ab617c78f2621d68446ca4dd8bd",
      "tree": "bbd9dddd0436da566365ada5deb1840e315e1b11",
      "parents": [
        "d6ab04646d8eec6f24b200f8649f3d942d9ad17e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 19 10:00:34 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jul 02 16:00:32 2014 +0100"
      },
      "message": "Support longs in the register allocator for x86_64.\n\nChange-Id: I7fb6dfb761bc5cf9e5705682032855a0a70ca867\n"
    },
    {
      "commit": "f61b5377068f22c0be7b2f6e62961e620408beb2",
      "tree": "15971fe1cf0797fa0b8ac0507b1a88c206f6c22e",
      "parents": [
        "fe6bfba3153ab55dab3ec0d644d628136e5ff0a4"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jun 25 14:35:34 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 26 09:27:37 2014 +0100"
      },
      "message": "Re-enable tests with the optimizing compiler.\n\nTests run ok on my host/target. I reverted the move to\nusing thumb2, because tests were crashing. But I could not\nreproduce file limits issues.\n\nMake SignalTest as crashing for optimizing. We need to implement\nstack overflow checks.\n\nChange-Id: Ieda575501eaf30af7aaa2c44e71544c9c467c24f\n"
    },
    {
      "commit": "e61fd353c06f51f1b8ca5af69997d0185b7659b2",
      "tree": "984d0609bf71e7705117e19eb836ddf203be6d01",
      "parents": [
        "20550910e608ed7d86db97927d2ce9d2191061a4"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jun 25 14:15:06 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jun 25 14:15:06 2014 +0000"
      },
      "message": "Revert \"Re-enable tests with the optimizing compiler.\"\n\nThis reverts commit 20550910e608ed7d86db97927d2ce9d2191061a4.\n\nChange-Id: Ic28b719946c795378838a18162a2a2b2cf41a0e8\n"
    },
    {
      "commit": "20550910e608ed7d86db97927d2ce9d2191061a4",
      "tree": "685b5ede42c3583c0152f784567026b1afc8e55d",
      "parents": [
        "ae43e2b11cc5af5b632700a9e4e4d9ed436b24dc"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jun 25 14:35:34 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jun 25 14:35:34 2014 +0100"
      },
      "message": "Re-enable tests with the optimizing compiler.\n\nTests run ok on my host/target. I reverted the move to\nusing thumb2, because tests were crashing. But I could not\nreproduce file limits issues.\n\nChange-Id: I26bc4ec1eb6c227750d11210e012d9d3b1d824af\n"
    },
    {
      "commit": "20dfc797dc631bf8d655dcf123f46f13332d3074",
      "tree": "c1d4e4f919d54f39a6d39d9d769ed5a844afb22b",
      "parents": [
        "cbb0e809c0a4e8a4e8b7f5d3768a1864cfb381bb"
      ],
      "author": {
        "name": "Dave Allison",
        "email": "dallison@google.com",
        "time": "Mon Jun 16 20:44:29 2014 -0700"
      },
      "committer": {
        "name": "Dave Allison",
        "email": "dallison@google.com",
        "time": "Tue Jun 24 09:05:27 2014 -0700"
      },
      "message": "Add some more instruction support to optimizing compiler.\n\nThis adds a few more DEX instructions to the optimizing compiler\u0027s\nbuilder (constants, moves, if_xx, etc).\n\nAlso:\n* Changes the codegen for IF_XX instructions to use a condition\n  rather than comparing a value against 0.\n* Fixes some instructions in the ARM disassembler.\n* Fixes PushList and PopList in the thumb2 assembler.\n* Switches the assembler for the optimizing compiler to thumb2\n  rather than ARM.\n\nChange-Id: Iaafcd02243ccc5b03a054ef7a15285b84c06740f\n"
    },
    {
      "commit": "e27f31a81636ad74bd3376ee39cf215941b85c0e",
      "tree": "12dd6a1153b78b831c887f65f0bcef715e89719d",
      "parents": [
        "dfc2091d2fb8a7694f69acf8bd39ce4953e026c2"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 12 17:53:14 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 12 18:05:00 2014 +0100"
      },
      "message": "Enable the register allocator on ARM.\n\n- Also fixes a few bugs/wrong assumptions in code not hit by x86.\n- We need to differentiate between moves due to connecting siblings within\n  a block, and moves due to control flow resolution.\n\nChange-Id: Idd05cf138a71c8f36f5531c473de613c0166fe38\n"
    },
    {
      "commit": "86dbb9a12119273039ce272b41c809fa548b37b6",
      "tree": "a4626e21ae16a9a5e133ea3e5e95b58d2ea4d8e5",
      "parents": [
        "c936622863a50bdda9b10062515dfc02a8c8b652"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jun 04 11:12:39 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 12 10:02:06 2014 +0100"
      },
      "message": "Final CL to enable register allocation on x86.\n\nThis CL implements:\n1) Resolution after allocation: connecting the locations\n   allocated to an interval within a block and between blocks.\n2) Handling of fixed registers: some instructions require\n   inputs/output to be at a specific location, and the allocator\n   needs to deal with them in a special way.\n3) ParallelMoveResolver::EmitNativeCode for x86.\n\nChange-Id: I0da6bd7eb66877987148b87c3be6a983b4e3f858\n"
    },
    {
      "commit": "65fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7",
      "tree": "fc0ce77d446477be37f0ec8c86d67df4941cac9b",
      "parents": [
        "e3b5cb502371aff7e7b7291facfc27b092e7803e"
      ],
      "author": {
        "name": "Dave Allison",
        "email": "dallison@google.com",
        "time": "Mon Apr 28 13:45:27 2014 -0700"
      },
      "committer": {
        "name": "Dave Allison",
        "email": "dallison@google.com",
        "time": "Thu Jun 05 12:45:20 2014 -0700"
      },
      "message": "Thumb2 assembler for JNI compiler and optimizing compiler\n\nThis provides a programmatic assembler for the thumb2 instruction set for\nARM.  The interface is the same as the ARM assembler and the ARM assembler has\nbeen moved into Arm32Assembler.  The assembler handles most 16 and 32 bit instructions\nand also allows relocations due to branch expansion.  It will also rewrite cbz/cbnz\ninstructions if they go out of range.\n\nIt also changes the JNI compiler to use the thumb2 assembler as opposed\nto forcing it to use ARM32.  The trampoline compiler still uses ARM due to the\nway it returns the address of its generated code.  A trampoline in thumb2 is the\nsame size as that in ARM anyway (8 bytes).\n\nProvides gtest for testing the thumb2 instruction output.  This gtest only runs\non the host as it uses arm-eabi-objdump to disassemble the generated code.  On the\ntarget the output is not checked but the assembler will still be run to perform\nall its checks.\n\nChange-Id: Icd9742b6f13541bec5b23097896727392e3a6fb6\n"
    },
    {
      "commit": "a7062e05e6048c7f817d784a5b94e3122e25b1ec",
      "tree": "a5d6b64ae6d5352f761fc2547bda863281adbe40",
      "parents": [
        "8b5b1e5593ffa77c393e4172b71a3d5a821d2ed8"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu May 22 12:50:17 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon May 26 11:31:38 2014 +0100"
      },
      "message": "Add a linear scan register allocator to the optimizing compiler.\n\nThis is a \"by-the-book\" implementation. It currently only deals\nwith allocating registers, with no hint optimizations.\n\nThe changes remaining to make it functional are:\n- Allocate spill slots.\n- Resolution and placements of Move instructions.\n- Connect it to the code generator.\n\nChange-Id: Ie0b2f6ba1b98da85425be721ce4afecd6b4012a4\n"
    },
    {
      "commit": "a7aca370a7d62ca04a1e24423d90e8020d6f1a58",
      "tree": "65d501b0f9711abddbea1a9d06623baafa4ae2b3",
      "parents": [
        "5dee5df89aa2cefef6c886d5b9b642cc6f1c595b"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Apr 28 17:47:12 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Apr 29 10:55:30 2014 +0100"
      },
      "message": "Setup policies for register allocation.\n\nChange-Id: I857e77530fca3e2fb872fc142a916af1b48400dc\n"
    },
    {
      "commit": "a747a392fb5f88d2ecc4c6021edf9f1f6615ba16",
      "tree": "fc5f08b127f3cf6bfb933504070109d46a455bb9",
      "parents": [
        "c2b2bbf1bbdf6273298b79d6006611593ed9f3a0"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Apr 17 14:56:23 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Apr 17 15:16:00 2014 +0100"
      },
      "message": "Code cleanup in preparation for x64 backend.\n\n- Use InvokeDexCallingConventionVisitor for setting\n  up HParameterValues\n- Use kVregSize instead of kX86WordSize when dealing with\n  virtual registers.\n\nChange-Id: Ia520223010194c70a3ff0ed659077f55cec4e7d8\n"
    },
    {
      "commit": "01bc96d007b67fdb7fe349232a83e4b354ce3d08",
      "tree": "1ed36c2d7c0fb204e6f276bd9853153d9350ad1d",
      "parents": [
        "2be6fc74bce10ac68d3d1b39a5019f520ad170ea"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Apr 11 17:43:50 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Apr 16 14:21:12 2014 +0100"
      },
      "message": "Long support in optimizing compiler.\n\n- Add stack locations to the Location class.\n- Change logic of parameter passing/setup by setting the\n  location of such instructions the ones for the calling\n  convention.\n\nChange-Id: I4730ad58732813dcb9c238f44f55dfc0baa18799\n"
    },
    {
      "commit": "707c809f661554713edfacf338365adca8dfd3a3",
      "tree": "21aaa53a3beb7d73fb2af9ab55bee7a538254fcb",
      "parents": [
        "7efad5d3a806a15166109837439f2e149031feef"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Apr 04 10:50:14 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Apr 04 10:50:14 2014 +0100"
      },
      "message": "Use target-specific word instead of runtime word.\n\nChange-Id: Ia11dc3cc520a1a5c7bd017013e5699af9570ce91\n"
    },
    {
      "commit": "4a34a428c6a2588e0857ef6baf88f1b73ce65958",
      "tree": "a9f025c17752a175c4e6a203c01e935cb438efb1",
      "parents": [
        "8549cf9d83688f7decbbea2a8de761ce29e95f3c"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Apr 03 10:38:37 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Apr 03 17:09:22 2014 +0100"
      },
      "message": "Support passing arguments to invoke-static* instructions.\n\n- Stop using the frame pointer for accessing locals.\n- Stop emulating a stack when doing code generation. Instead,\n  rely on dex register model, where instructions only reference\n  registers.\n\nChange-Id: Id51bd7d33ac430cb87a53c9f4b0c864eeb1006f9\n"
    },
    {
      "commit": "8ccc3f5d06fd217cdaabd37e743adab2031d3720",
      "tree": "ec8c904baafb4d9b9bfd582245e2d780bcdfaade",
      "parents": [
        "ad174d1b54bf2fa477bec71a0ca93595f54b8fe9"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Mar 19 10:34:11 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Mar 31 09:44:40 2014 +0100"
      },
      "message": "Add support for invoke-static in optimizing compiler.\n\nSupport is limited to calls without parameters and returning\nvoid. For simplicity, we currently follow the Quick ABI.\n\nChange-Id: I54805161141b7eac5959f1cae0dc138dd0b2e8a5\n"
    },
    {
      "commit": "787c3076635cf117eb646c5a89a9014b2072fb44",
      "tree": "3c9c6c6d56e3900cf2255a5d1ade008ec6a40681",
      "parents": [
        "b9d50a9829b795932eac4cc50a99b4ce80b0ecb4"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Mar 17 10:20:19 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Mar 18 11:20:20 2014 +0000"
      },
      "message": "Plug new optimizing compiler in compilation pipeline.\n\nAlso rename accessors to ART\u0027s conventions.\n\nChange-Id: I344807055b98aa4b27215704ec362191464acecc\n"
    },
    {
      "commit": "bab4ed7057799a4fadc6283108ab56f389d117d4",
      "tree": "ea1bf495458fd9f7a3ffbed0ea4e1dda5a0b8184",
      "parents": [
        "37d4c1db4d705f5a28001f65afdd68d0527948d8"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Mar 11 17:53:17 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Mar 13 09:23:12 2014 +0000"
      },
      "message": "More code generation for the optimizing compiler.\n\n- Add HReturn instruction\n- Generate code for locals/if/return\n- Setup infrastructure for register allocation. Currently\n  emulate a stack.\n\nChange-Id: Ib28c2dba80f6c526177ed9a7b09c0689ac8122fb\n"
    },
    {
      "commit": "d4dd255db1d110ceb5551f6d95ff31fb57420994",
      "tree": "93c9dfff8d16f2b9675c35477cc4bcd8ea3f630c",
      "parents": [
        "b565506a63e75dac4a8bb9dd54dabf5259e5b95f"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Feb 28 10:23:58 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Mar 04 16:19:11 2014 +0000"
      },
      "message": "Add codegen support to the optimizing compiler.\n\nChange-Id: I9aae76908ff1d6e64fb71a6718fc1426b67a5c28\n"
    }
  ]
}