)]}'
{
  "log": [
    {
      "commit": "077188411c692f82b0785597fee030810a2a5841",
      "tree": "f74ced58d91dcb215601175dc7d29854d46aee0d",
      "parents": [
        "1715efa0b46d57d587237829d1c0695aaca2c344"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Mon Feb 24 18:51:42 2020 +0000"
      },
      "committer": {
        "name": "Ulyana Trafimovich",
        "email": "skvadrik@google.com",
        "time": "Tue Jun 09 13:11:45 2020 +0000"
      },
      "message": "ART: Introduce predicated vector instructions.\n\nThis CL introduces a minimal changes to the IR to support\nautovectorization with use of predicated execution of SIMD\ninstructions (e.g. Arm SVE).\n\nTest: test-art-target, test-art-host.\nChange-Id: Ibb7c5520fec6b858fb29f0dde19ec65501831a3a\n"
    },
    {
      "commit": "d71f1dc15e264f9d2122c427a4d99d49b525bfd3",
      "tree": "9bb30ad7c9420e738ec84f55d6c01b2f3a754ff7",
      "parents": [
        "c124d1dd977a2ddcd6e4928cfe6c0698f44d6523"
      ],
      "author": {
        "name": "xueliang.zhong",
        "email": "xueliang.zhong@linaro.org",
        "time": "Wed Jan 24 17:24:16 2018 +0000"
      },
      "committer": {
        "name": "Treehugger Robot",
        "email": "treehugger-gerrit@google.com",
        "time": "Tue Jan 28 17:10:34 2020 +0000"
      },
      "message": "Enable support of VecLoad/VecStore in LSE\n\nChanges:\n- Enable VecLoad and VecStore support in LSE.\n- This CL is based on Mingyao\u0027s CL: More general store elimination.\n- The new gtest load_store_elimination_test is to test some corner cases\n  where ArrayGet/ArraySet/VecLoad/VecStore are mixed and overlap.\n- The new java 530-checker-lse-simd.\n\nTest: test.py --host --optimizing --jit --gtest\nTest: test.py --target --optimizing --jit\nTest: run-gtests.sh\nTest: load_store_elimination_test\nTest: 530-checker-lse-simd\nTest: ./art/test/run-test --optimizing --64 --gcstress 667-checker-simd-alignment\nTest: m -j80 art-check-testing-apex-gen\n\nChange-Id: I2d2024ec75a2aaef56b527db98abb40c5f16be79\n"
    },
    {
      "commit": "0a51605ddd81635135463dab08b6f7c21b58ffb0",
      "tree": "820f338333010f4d6e4b543ffea47e9ff7d2dd3f",
      "parents": [
        "e2727154f25e0db9a5bb92af494d8e47b181dfcf"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Oct 14 13:00:44 2019 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Oct 14 13:00:44 2019 +0000"
      },
      "message": "Revert \"Make compiler/optimizing/ symbols hidden.\"\n\nThis reverts commit e2727154f25e0db9a5bb92af494d8e47b181dfcf.\n\nReason for revert: Breaks ASAN tests (ODR violation).\nBug: 142365358\n\nChange-Id: I38103d74a1297256c81d90872b6902ff1e9ef7a4\n"
    },
    {
      "commit": "e2727154f25e0db9a5bb92af494d8e47b181dfcf",
      "tree": "0ddc6eec3ad9508d7eb1f2b941786dd0ed7d2cd8",
      "parents": [
        "c78860b91ae07eed92f86876e7a03132adea6fcd"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Oct 10 10:46:42 2019 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Oct 14 08:22:00 2019 +0000"
      },
      "message": "Make compiler/optimizing/ symbols hidden.\n\nMake symbols in compiler/optimizing hidden by a namespace\nattribute. The unit intrinsic_objects.{h,cc} is excluded as\nit is needed by dex2oat.\n\nAs the symbols are no longer exported, gtests are now linked\nwith the static version of the libartd-compiler library.\n\nlibart-compiler.so size:\n  - before:\n    arm: 2396152\n    arm64: 3345280\n  - after:\n    arm: 2016176 (-371KiB, -15.9%)\n    arm64: 2874480 (-460KiB, -14.1%)\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nBug: 142365358\nChange-Id: I1fb04a33351f53f00b389a1642e81a68e40912a8\n"
    },
    {
      "commit": "3db70689e3e1c92344d436a8ea4265046bdef449",
      "tree": "3db08743e968062ed5bdc143233cdb3c4564696b",
      "parents": [
        "1650dafad62578a1766bd617d78458a4cf1e2a9a"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Wed Dec 26 15:12:03 2018 -0800"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Thu Dec 27 12:56:39 2018 -0800"
      },
      "message": "ART: Refactor for bugprone-argument-comment\n\nHandles compiler.\n\nBug: 116054210\nTest: WITH_TIDY\u003d1 mmma art\nChange-Id: I5cdfe73c31ac39144838a2736146b71de037425e\n"
    },
    {
      "commit": "4e3734a53614a1db710ea34b81f1cc2260790e7a",
      "tree": "2d1c5afdff2a46e71d6c576da2d0da0eb7e44f04",
      "parents": [
        "8786fd93e01b9c88f708c14743925489f8db8c28"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Nov 14 15:45:28 2018 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Nov 14 18:44:19 2018 +0000"
      },
      "message": "Rename HVecReduce::GetKind() to GetReductionKind().\n\nAvoid hiding HInstruction::GetKind().\n\nTest: m test-art-host-gtest\nChange-Id: If7334af437d0a6d93b8228763451c80876aa4d00\n"
    },
    {
      "commit": "aaac0e3cbfe72217cad204d0122f2b73a602d2dd",
      "tree": "d148274452b3a409c9d6b8ef749c34185375d2ea",
      "parents": [
        "7dca45b9677c16a54347cdc0d08bfa2bdd94b464"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Tue Aug 07 00:52:22 2018 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Tue Sep 25 14:47:48 2018 +0100"
      },
      "message": "ART: ARM64: Support DotProd SIMD idiom.\n\nImplement support for vectorization idiom which performs dot\nproduct of two vectors and adds the result to wider precision\ncomponents in the accumulator.\n\nviz. DOT_PRODUCT([ a1, .. , am], [ x1, .. , xn ], [ y1, .. , yn ]) \u003d\n                 [ a1 + sum(xi * yi), .. , am + sum(xj * yj) ],\n     for m \u003c\u003d n, non-overlapping sums,\n     for either both signed or both unsigned operands x, y.\n\nThe patch shows up to 7x performance improvement on a micro\nbenchmark on Cortex-A57.\n\nTest: 684-checker-simd-dotprod.\nTest: test-art-host, test-art-target.\n\nChange-Id: Ibab0d51f537fdecd1d84033197be3ebf5ec4e455\n"
    },
    {
      "commit": "bbc6e7edb5fca4a61ac53dd9bce79cb4f0bb3403",
      "tree": "0fbce767bc383358cf4cd65aafc74140e1850982",
      "parents": [
        "19379b58bd433da91230e4fe6cd96e7416d16adc"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Fri Aug 24 16:58:47 2018 +0100"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Tue Aug 28 11:06:07 2018 +0100"
      },
      "message": "Use \u0027final\u0027 and \u0027override\u0027 specifiers directly in ART.\n\nRemove all uses of macros \u0027FINAL\u0027 and \u0027OVERRIDE\u0027 and replace them with\n\u0027final\u0027 and \u0027override\u0027 specifiers. Remove all definitions of these\nmacros as well, which were located in these files:\n- libartbase/base/macros.h\n- test/913-heaps/heaps.cc\n- test/ti-agent/ti_macros.h\n\nART is now using C++14; the \u0027final\u0027 and \u0027override\u0027 specifiers have\nbeen introduced in C++11.\n\nTest: mmma art\nChange-Id: I256c7758155a71a2940ef2574925a44076feeebf\n"
    },
    {
      "commit": "9434487f640d4a4c247e916e30137b9359f50eed",
      "tree": "4edc7e4811cc570cf29ac0ec47b04cfd2b5383f1",
      "parents": [
        "cdfc942e60032622b5a4379d0dd5ca914ba6393a"
      ],
      "author": {
        "name": "Hans Boehm",
        "email": "hboehm@google.com",
        "time": "Fri Jul 13 09:57:50 2018 -0700"
      },
      "committer": {
        "name": "Hans Boehm",
        "email": "hboehm@google.com",
        "time": "Fri Jul 13 13:10:40 2018 -0700"
      },
      "message": "Expand comment for HVecMultiplyAccumulate\n\nState explicitly that fused multiply-add may not be used, since this\nwas a source of prior confusion. Add a DCHECK to draw developers\nattention to this, if they try to add a floating point multiply-add.\n\nSee https://android-review.googlesource.com/c/platform/art/+/716505 .\n\nTest: Treehugger\nChange-Id: I1331be120a0a54baeb4da92e9211407b08892e98\n"
    },
    {
      "commit": "f5f56c791c5853f43a2a9781c98d5776c7dd5a59",
      "tree": "ed8270e3a5d0161ebe5bec0606a24cd5e3123e59",
      "parents": [
        "61908880e6565acfadbafe93fa64de000014f1a6"
      ],
      "author": {
        "name": "Hans Boehm",
        "email": "hboehm@google.com",
        "time": "Fri Jul 13 00:05:27 2018 +0000"
      },
      "committer": {
        "name": "Hans Boehm",
        "email": "hboehm@google.com",
        "time": "Fri Jul 13 00:05:27 2018 +0000"
      },
      "message": "Revert \"Emit vector mulitply and accumulate instructions for x86.\"\n\nThis reverts commit 61908880e6565acfadbafe93fa64de000014f1a6.\n\nReason for revert: By failing to round multiply results, it does not follow Java rounding rules.\n\nChange-Id: Ic0ef08691bef266c9f8d91973e596e09ff3307c6\n"
    },
    {
      "commit": "61908880e6565acfadbafe93fa64de000014f1a6",
      "tree": "40b535db9175f3d959364d5bc30eaab4e2c4b4c4",
      "parents": [
        "b5271dd44a30f498689e503340d3c8d01bf31f07"
      ],
      "author": {
        "name": "Gupta Kumar, Sanjiv",
        "email": "sanjiv.kumar.gupta@intel.com",
        "time": "Fri Jun 29 13:06:35 2018 +0530"
      },
      "committer": {
        "name": "Gupta Kumar, Sanjiv",
        "email": "sanjiv.kumar.gupta@intel.com",
        "time": "Mon Jul 02 15:37:38 2018 +0530"
      },
      "message": "Emit vector mulitply and accumulate instructions for x86.\n\nThis patch adds a new cpu vaiant named kabylake and performs\ninstruction simplification to generate VectorMulitplyAccumulate.\n\nTest: ./test.py --host --64\n\nChange-Id: Ie6cc882dadf1322dd4d3ae49bfdb600b0c447765\nSigned-off-by: Gupta Kumar, Sanjiv \u003csanjiv.kumar.gupta@intel.com\u003e\n"
    },
    {
      "commit": "bd78567cef305e35481734b7fc24f68ded031439",
      "tree": "e3873b73e3631c5cd70c1a3f8f38e79dad25d890",
      "parents": [
        "9926e4615d75cb6c9371e1766a14b0a80089ae18"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu May 03 17:09:09 2018 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue May 08 11:36:11 2018 +0100"
      },
      "message": "Store HIR type in HInstruction::packed_field_.\n\nThis is similar to\n    https://android-review.googlesource.com/609566\nthough the performance impact has not been measured.\nHowever, avoiding a virtual call reduces pressure on the\nbranch predictor and provides better optimization\nopportunities for the C++ compiler.\n\nAs there is now no difference between HTemplateInstruction\u003c\u003e\nand HExpression\u003c\u003e (the type is stored in HInstruction), we\nremove the former and use HExpression\u003c\u003e for all instructions\nthat have a fixed number of inputs.\n\nTest: Rely on TreeHugger.\nChange-Id: Ib3fd111048b0ac38ee65386a7e5af70c5ccc98de\n"
    },
    {
      "commit": "3f8e02c3603cf48c7a656b2dd8781e11481fe34b",
      "tree": "04c1722c0477342dcc6b6d45329c799d99120e81",
      "parents": [
        "8d2e70ae234d53f825f6876f5b5e75bdfe6729b5"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Apr 10 11:55:00 2018 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Apr 13 10:01:41 2018 -0700"
      },
      "message": "Bug fix in SIMD result detection.\n\nRationale:\nOnly 2-way phis are currently used in reductions\nto carry SIMD results. Note that this will go away\nwhen we introduce proper SIMD types.\n\nNote:\nSo far I have not been able to make a small regression\ntest for this. Any pointers on how to set up a catch phi?\n\nTest: test-art-host,target\n\nBug: b/77725987\nChange-Id: I8f8b2dbec35e906878b7f7ed62690c3234db4211\n"
    },
    {
      "commit": "5a0eb0cbeeabda48bfef05df9f59a6fd607e1a1e",
      "tree": "357b3a1a998107de6ec036fc107f897488d24a82",
      "parents": [
        "aae3435b642dbf3196ef47e8ec48ec3ca2a84d4b"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Mar 16 15:00:19 2018 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Mar 16 15:00:19 2018 -0700"
      },
      "message": "Minor DCHECK bug fix.\n\nRationale:\nShould use the utility to test for SIMD result,\nnot a hard is vector test.\n\nTest: 623 is regression test for DCHECK fail\nChange-Id: I1d7949fa25139f8a3734986d5de7989ed32ff2bd\n"
    },
    {
      "commit": "29aa08219ff72409e9f10ae2a5da4e6e604baad1",
      "tree": "2ccde97263f82b6a2f1a83d5b674f46c412c2909",
      "parents": [
        "8e68c6c85ad188e306cd66f8b620350f996fe242"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Mar 08 11:28:00 2018 -0800"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Mar 15 09:49:18 2018 -0700"
      },
      "message": "Vectorization of saturation arithmetic.\n\nRationale:\nBecause faster is better.\n\nBug: b/74026074\n\nTest: test-art-host,target\n\nChange-Id: Ifa970a62cef1c0b8bb1c593f629d8c724f1ffe0e\n"
    },
    {
      "commit": "d9e4d73b20d68aa387f5837e1535b6fc26b2859a",
      "tree": "b55a96e66f2db1482571788b33c6d3055cb47396",
      "parents": [
        "8dbb4ba7ffdf42cf08c55b117370efc0ec5357e8"
      ],
      "author": {
        "name": "Gupta Kumar, Sanjiv",
        "email": "sanjiv.kumar.gupta@intel.com",
        "time": "Mon Feb 05 13:35:03 2018 +0530"
      },
      "committer": {
        "name": "Gupta Kumar, Sanjiv",
        "email": "sanjiv.kumar.gupta@intel.com",
        "time": "Wed Feb 21 14:56:13 2018 +0530"
      },
      "message": "Fix iCache misses for GetKind on x86,x86_64\n\nGetKind() takes about 2.6% of total compilation time on x86_64.\nThe primary reason is that the target call GetKindInternal() is often\nbeyond the page boundary causing frequent i-cache misses.\nThis patch removes the virtual call to GetKindInternal () and instead\nkeeps the InstructionKind into each constructed instruction.\nSince we have about 121 instructions in total as of now,\nit takes about 7 extra bits in each instruction.\ndex2oat runs about 12% faster with --compiler-filter\u003deverything on an\nAPK of 25MB.\n\nTest: Tested the patch by running host art tests.\n\nRebased.\n\nChange-Id: Ia7bbcd67180151e4565507164a718acbb6284885\nSigned-off-by: Gupta Kumar, Sanjiv \u003csanjiv.kumar.gupta@intel.com\u003e\n"
    },
    {
      "commit": "66c158ef6b2a16257f1590b3ace78848a7c2407b",
      "tree": "f17f7eee70aa43711c7eb764c1789f4ec17aef37",
      "parents": [
        "92d0c8b68c24a2fa21f95d63a1ff2fb00fdb9aaf"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Jan 31 12:55:04 2018 -0800"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Feb 01 13:26:03 2018 -0800"
      },
      "message": "Clean up signed/unsigned in vectorizer.\n\nRationale:\nCurrently we have some remaining ugliness around signed and unsigned\nSIMD operations due to lack of kUint32 and kUint64 in the HIR. By\n\"softly\" introducing these types, ABS/MIN/MAX/HALVING_ADD/SAD_ACCUMULATE\noperations can solely rely on the packed data types to distinguish\nbetween signed and unsigned operations. Cleaner, and also allows for\nsome code removal in the current loop optimizer.\n\nBug: 72709770\n\nTest: test-art-host test-art-target\nChange-Id: I68e4cdfba325f622a7256adbe649735569cab2a3\n"
    },
    {
      "commit": "89ff8b23f7c4189ba82407d95c3100c2f397cf19",
      "tree": "95a49416c9231eea98c927e8777b7721b24974a3",
      "parents": [
        "03376f4c4de8e419402bf40fdff4135728ffb21e"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Mon Nov 20 11:51:05 2017 +0000"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Wed Dec 13 15:33:29 2017 +0000"
      },
      "message": "ARM64: Workaround for the callee saved FP registers and SIMD.\n\nTreat as scheduling barriers those vector instructions whose live\nranges exceed the vectorized loop boundaries. This is a workaround\nfor the lack of notion of SIMD register in the compiler; around a\ncall we have to save/restore all live SIMD\u0026FP registers (only\nlower 64 bits of SIMD\u0026FP registers are callee saved) so don\u0027t\nreorder such vector instructions.\n\nTest: 706-checker-scheduler, test-art-host, test-art-target\nBug: 69667779\n\nChange-Id: I31e57518339d41545a0c519f7299afe381a8286c\n"
    },
    {
      "commit": "2dd7b672ea0afd7ea4448b43d24829e9886de3af",
      "tree": "fd7e3c48f5ac17fc238bff68bf33e5868d1386dc",
      "parents": [
        "718173b7705ebc7f4a15aaaa4c074f9e5d907b31"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Dec 07 11:11:22 2017 -0800"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Dec 07 15:43:33 2017 -0800"
      },
      "message": "Fixed spilling bug (visible on ARM64): missed SIMD type.\n\nTest: test-art-host test-art-target\nChange-Id: I6f321446f54943e02f250732ec9da729f633c3a9\n"
    },
    {
      "commit": "cced8ba4245a061ab047a0a6882468d75d619dd9",
      "tree": "b379abfa48689c108e1cacedd2b13d4b5394baf2",
      "parents": [
        "96c76457d5c5af2d4243c78d74ada77de3223d88"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Wed Jul 19 18:18:09 2017 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Tue Nov 07 12:56:17 2017 +0000"
      },
      "message": "ART: Introduce individual HInstruction cloning.\n\nIntroduce API for HInstruction cloning, support it for a few\ninstructions. add a gtest.\n\nTest: cloner_test.cc, test-art-target, test-art-host.\n\nChange-Id: I8b6299be5d04a26390d9ef13a20ce82ee5ae4afe\n"
    },
    {
      "commit": "4d1a9d4b01ef0bbea3b7dfa9f31420d6e1d0ac83",
      "tree": "dd60bed0d302987c2a8f766d58fc855f510183c5",
      "parents": [
        "758aeab86b79369f9dfc6ae5d3bd98232f5b9c40"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Oct 19 14:40:55 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Oct 20 11:10:52 2017 -0700"
      },
      "message": "Improve sign and zero extension analysis.\n\nRationale:\nThis was needed to fix the regression introduced by\na prior type based cl. With the new type system ramping\nup, however, this is actually more  simplification (remove\nthe And recognition for example) than new code!\n\nTest: test-art-host test-art-target\n\nBug: 67935418\nChange-Id: I4284f8f29f3d26e4033a3014d0c697677cc0d795\n"
    },
    {
      "commit": "61b922847403ac0e74b6477114c81a28ac2e01a0",
      "tree": "02674602fb2592f758f51389b3c7b276ab4df3ee",
      "parents": [
        "6783118d2ad9d759f0617b1219a9e29a10a569f7"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Oct 11 13:23:17 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Oct 18 15:52:51 2017 +0100"
      },
      "message": "ART: Introduce Uint8 loads in compiled code.\n\nSome vectorization patterns are not recognized anymore.\nThis shall be fixed later.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: testrunner.py --target --optimizing on Nexus 5X\nTest: Nexus 5X boots.\nBug: 23964345\nBug: 67935418\nChange-Id: I587a328d4799529949c86fa8045c6df21e3a8617\n"
    },
    {
      "commit": "e764d2e50c544c2cb98ee61a15d613161ac6bd17",
      "tree": "112aa7ca459d2edb4f800897060a2407fcc622c7",
      "parents": [
        "ca6fff898afcb62491458ae8bcd428bfb3043da1"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Oct 05 14:35:55 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Oct 09 10:39:22 2017 +0100"
      },
      "message": "Use ScopedArenaAllocator for register allocation.\n\nMemory needed to compile the two most expensive methods for\naosp_angler-userdebug boot image:\n  BatteryStats.dumpCheckinLocked() : 25.1MiB -\u003e 21.1MiB\n  BatteryStats.dumpLocked(): 49.6MiB -\u003e 42.0MiB\nThis is because all the memory previously used by Scheduler\nis reused by the register allocator; the register allocator\nhas a higher peak usage of the ArenaStack.\n\nAnd continue the \"arena\"-\u003e\"allocator\" renaming.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nBug: 64312607\nChange-Id: Idfd79a9901552b5147ec0bf591cb38120de86b01\n"
    },
    {
      "commit": "46b6dbcd18df0cb5915ca906fefd9f0b0a1af6a2",
      "tree": "723856081b9d0abcc017b323672e4b1cc99cad16",
      "parents": [
        "844a4edc7f72e33a3b328c3d53ef710909d2273d"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Oct 03 11:37:37 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Oct 05 10:42:13 2017 -0700"
      },
      "message": "Try to preserve dex pc better in vector code.\n\nAlso improves a few comment and uses new data\ntype method to test type consistency.\n\nTest: test-art-host\n\nChange-Id: I4a17f9d5bc458a091a259dd45ebcdc6531abbf84\n"
    },
    {
      "commit": "d5d2f2ce627aa0f6920d7ae05197abd1a396e035",
      "tree": "e8e780780c832e3614a22438a23fb60ee4960ca3",
      "parents": [
        "efac0df8c738764823c637deeca1f3be33912064"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Sep 26 12:37:26 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Oct 03 10:40:51 2017 +0100"
      },
      "message": "ART: Introduce Uint8 compiler data type.\n\nThis CL adds all the necessary codegen for the Uint8 type\nbut does not add code transformations that use that code.\nVectorization codegens are modified to use Uint8 as the\npacked type when appropriate. The side effects are now\ndisconnected from the instruction\u0027s type after the graph has\nbeen built to allow changing HArrayGet/H*FieldGet/HVecLoad\nto use a type different from the underlying field or array.\n\nNote: HArrayGet for String.charAt() is modified to have\nno side effects whatsoever; Strings are immutable.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: testrunner.py --target --optimizing on Nexus 6P\nTest: Nexus 6P boots.\nBug: 23964345\nChange-Id: If2dfffedcfb1f50db24570a1e9bd517b3f17bfd0\n"
    },
    {
      "commit": "0ebe0d83138bba1996e9c8007969b5381d972b32",
      "tree": "a5ee66ebc5b587ade97e56ac8fc7d832fbbed4af",
      "parents": [
        "e1e347dace0ded83774999bb26c37527dcdb1d5a"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Sep 21 22:50:39 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Sep 25 15:45:01 2017 +0100"
      },
      "message": "ART: Introduce compiler data type.\n\nReplace most uses of the runtime\u0027s Primitive in compiler\nwith a new class DataType. This prepares for introducing\nnew types, such as Uint8, that the runtime does not need\nto know about.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nBug: 23964345\nChange-Id: Iec2ad82454eec678fffcd8279a9746b90feb9b0c\n"
    },
    {
      "commit": "dbbac8f812a866b1b53f3007721f66038d208549",
      "tree": "05cecd927afccd33fc1c14b39ada47e86873f560",
      "parents": [
        "2406bf17998e15bd40677a907beb3e9c41facce4"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Sep 01 13:06:08 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Sep 21 10:20:55 2017 -0700"
      },
      "message": "Implement Sum-of-Abs-Differences idiom recognition.\n\nRationale:\nCurrently just on ARM64 (x86 lacks proper support),\nusing the SAD idiom yields great speedup on loops\nthat compute the sum-of-abs-difference operation.\nAlso includes some refinements around type conversions.\n\nSpeedup ExoPlayerAudio (golem run):\n1.3x on ARM64\n1.1x on x86\n\nTest: test-art-host test-art-target\n\nBug: 64091002\n\nChange-Id: Ia2b711d2bc23609a2ed50493dfe6719eedfe0130\n"
    },
    {
      "commit": "5e3afa950f05bca470ef6b92460940f37831c27f",
      "tree": "3656fb1d9153a87b55b56c71a93833da49c112d4",
      "parents": [
        "b407afe983f8b106a5007d07aa2523ffc6525018"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Sep 20 14:11:11 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Sep 20 14:11:11 2017 -0700"
      },
      "message": "Ensure extract is seen as having scalar result.\n\nRationale:\nExtracting from a vector yields a scalar, yet\nour parallel mover and one DCHECK did not account\nfor that fact (note that moving towards a vector\ntype system will prevent such errors).\n\nRegression test for this is part of the SAD CL.\n\nTest: test-art-host test-art-target\n\nBug: 64091002\nChange-Id: Id154edd1a069c54e7d8da069c368dea0a8f973f4\n"
    },
    {
      "commit": "0148de41a5c77c2f61252c219f1a02413c7c4a32",
      "tree": "91736a82a7e98721a44879b6597b5aea386e8e3b",
      "parents": [
        "c101222c854a0c476f5b6ae64e20adbd38126a3c"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Sep 05 09:25:01 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Sep 05 10:20:09 2017 -0700"
      },
      "message": "Basic SIMD reduction support.\n\nRationale:\nEnables vectorization of x +\u003d .... for very basic (simple, same-type)\nconstructs. Paves the way for more complex (narrower and/or mixed-type)\nconstructs, which will be handled by the next CL.\n\nThis is  a revert   of Icb5d6c805516db0a1d911c3ede9a246ccef89a22\nand thus a revert^2 of I2454778dd0ef1da915c178c7274e1cf33e271d0f\nand thus a revert^3 of I1c1c87b6323e01442e8fbd94869ddc9e760ea1fc\nand thus a revert^4 of I7880c135aee3ed0a39da9ae5b468cbf80e613766\n\nPS1-2 shows what needed to change\n\nTest: test-art-host test-art-target\n\nBug: 64091002\nChange-Id: I647889e0da0959ca405b70081b79c7d3c9bcb2e9\n"
    },
    {
      "commit": "982334cef17d47ef2477d88a97203a9587a4b86f",
      "tree": "7e65d03a4533f21286cf68e66696bd0a7a54ef54",
      "parents": [
        "cfa59b49cde265dc5329a7e6956445f9f7a75f15"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Sat Sep 02 12:54:16 2017 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Sat Sep 02 12:54:16 2017 +0000"
      },
      "message": "Revert \"Basic SIMD reduction support.\"\n\nFails 530-checker-lse on arm64.\n\nBug: 64091002, 65212948\n\nThis reverts commit cfa59b49cde265dc5329a7e6956445f9f7a75f15.\n\nChange-Id: Icb5d6c805516db0a1d911c3ede9a246ccef89a22\n"
    },
    {
      "commit": "cfa59b49cde265dc5329a7e6956445f9f7a75f15",
      "tree": "eed953f62e796f7e64252520a40d7e77d1f117af",
      "parents": [
        "82a63734d3067ea0c96f8ba15bc40caaf798c625"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Aug 31 09:08:13 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Sep 01 10:32:50 2017 -0700"
      },
      "message": "Basic SIMD reduction support.\n\nRationale:\nEnables vectorization of x +\u003d .... for very basic (simple, same-type)\nconstructs. Paves the way for more complex (narrower and/or mixed-type)\nconstructs, which will be handled by the next CL.\n\nThis is a revert^2 of I7880c135aee3ed0a39da9ae5b468cbf80e613766\nand thus a revert  of I1c1c87b6323e01442e8fbd94869ddc9e760ea1fc\n\nPS1-2 shows what needed to change, with regression tests\n\nTest: test-art-host test-art-target\n\nBug: 64091002, 65212948\nChange-Id: I2454778dd0ef1da915c178c7274e1cf33e271d0f\n"
    },
    {
      "commit": "a57b4ee7b15ce6abfb5fa88c8dc8a516fe40e0d9",
      "tree": "c7ed7e8cb7439a8e689e399e34559aa46a97cdbd",
      "parents": [
        "9879d0eac8fe2aae19ca6a4a2a83222d6383afc2"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Aug 30 21:21:41 2017 +0000"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Aug 30 21:21:41 2017 +0000"
      },
      "message": "Revert \"Basic SIMD reduction support.\"\n\nThis reverts commit 9879d0eac8fe2aae19ca6a4a2a83222d6383afc2.\n\nGetting these type check failures in some builds. Need time to look at this better, so reverting for now :-(\n\n\ndex2oatd F 08-30 21:14:29 210122 226218 \ncode_generator.cc:115] Check failed: CheckType(instruction-\u003eGetType(), locations-\u003eInAt(0)) PrimDouble C\n\nChange-Id: I1c1c87b6323e01442e8fbd94869ddc9e760ea1fc\n"
    },
    {
      "commit": "9879d0eac8fe2aae19ca6a4a2a83222d6383afc2",
      "tree": "c75ab69be15630f86824bb202577eaa1ff91c4ee",
      "parents": [
        "60f734443d54d48fad86dce6d80d8cef22a134d0"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Aug 15 10:51:25 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Aug 30 09:10:40 2017 -0700"
      },
      "message": "Basic SIMD reduction support.\n\nRationale:\nEnables vectorization of x +\u003d .... for very basic (simple, same-type)\nconstructs. Paves the way for more complex (narrower and/or mixed-type)\nconstructs, which will be handled by the next CL.\n\nTest: test-art-host test-art-target\n\nBug: 64091002\n\nChange-Id: I7880c135aee3ed0a39da9ae5b468cbf80e613766\n"
    },
    {
      "commit": "b79f4ac55c0bb177f541937d0678f2aa777e1c9a",
      "tree": "7c331aa30d3c38b4448070527ac02fdbd848f284",
      "parents": [
        "51e74b47f240187d336d9e688f5d7538366f2edf"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Jul 10 10:10:37 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Jul 13 16:50:03 2017 -0700"
      },
      "message": "Added GVN related attributes to vector nodes.\n\nRationale: enables better GVNing of vector operations,\nalso pays off some technical debt by adding unit tests\nfor vector nodes.\n\nThis is a revert^2 of a79f0b5deb932aa44e227c94c4ad09082b3ab4c7\n(failed some of the existing checker test due to\nmoving scalar replication; fix was setting can-be-moved\nattribute correctly on that node).\n\nBug: 63538372\n\nTest: test-art-host, test-art-target\n\nChange-Id: I2f29c317354b5e4bf520829232aef17931305ea6\n"
    },
    {
      "commit": "9858bf70c9af425f5f712caca7b51b49c806b271",
      "tree": "e70e88c83c8260fbea01b258d3d221cc31d38d8d",
      "parents": [
        "a79f0b5deb932aa44e227c94c4ad09082b3ab4c7"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Sat Jul 08 12:34:55 2017 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Sat Jul 08 12:34:55 2017 +0000"
      },
      "message": "Revert \"Added GVN related attributes to vector nodes.\"\n\nFails armv8 checker tests.\n\nThis reverts commit a79f0b5deb932aa44e227c94c4ad09082b3ab4c7.\n\nChange-Id: I8913743f241febbbb24c0662af76397e87e59cd1\n"
    },
    {
      "commit": "a79f0b5deb932aa44e227c94c4ad09082b3ab4c7",
      "tree": "2d16c2876f6ccbc8ca1b9f6bf7fe43523a4132e3",
      "parents": [
        "4c4d9df7c79747978d2f927994a7b3c11a079075"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Jul 05 17:19:41 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Jul 06 11:58:20 2017 -0700"
      },
      "message": "Added GVN related attributes to vector nodes.\n\nRationale: enables better GVNing of vector operations,\nalso pays off some technical debt by adding unit tests\nfor vector nodes.\n\nTest: test-art-host, test-art-target\n\nChange-Id: I2aa886b894bb6a0961823ae309cf8cf44984cf4a\n"
    },
    {
      "commit": "a1633a7077781d9c64a77b27deb1707d1a56906d",
      "tree": "505f2560cfd247b2e1aab86d3ab96e5c399cb05d",
      "parents": [
        "a774575ae3af3d46955f941ddd08a79caf2aaa94",
        "c8e93c736c149ce41be073dd24324fb08afb9ae4"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue May 16 15:56:01 2017 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Tue May 16 15:56:04 2017 +0000"
      },
      "message": "Merge \"Min/max SIMDization support.\""
    },
    {
      "commit": "c8e93c736c149ce41be073dd24324fb08afb9ae4",
      "tree": "8e7154cf1bbcee8f5837ee9cb930174e2516ac03",
      "parents": [
        "92f4672f811a4eccdc596f7c2235804abd196fde"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@ajcbik2.mtv.corp.google.com",
        "time": "Wed May 10 10:49:22 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon May 15 11:44:58 2017 -0700"
      },
      "message": "Min/max SIMDization support.\n\nRationale:\nThe more vectorized, the better!\n\nTest: test-art-target, test-art-host\n\nChange-Id: I758becca5beaa5b97fab2ab70f2e00cb53458703\n"
    },
    {
      "commit": "e1811ed6b57a54dc8ebd327e4bd2c4422092a3a0",
      "tree": "e3ce48e66190c11a8b5342f4ec0d1046ba28d788",
      "parents": [
        "7113885fcd983b33ee1e350865d21517d6297843"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu Apr 27 16:50:47 2017 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu May 11 10:06:04 2017 +0100"
      },
      "message": "ARM64: Share address computation across SIMD LDRs/STRs.\n\nFor array accesses the element address has the following structure:\nAddress \u003d CONST_OFFSET + base_addr + index \u003c\u003c ELEM_SHIFT\n\nTaking into account ARM64 LDR/STR addressing modes address part\n(CONST_OFFSET + index \u003c\u003c ELEM_SHIFT) can be shared across array\naccess with the same data type and index.\n\nFor example, for the following loop 5 accesses can share address\ncomputation:\n\nvoid foo(int[] a, int[] b, int[] c) {\n  for (i...) {\n    a[i] \u003d a[i] + 5;\n    b[i] \u003d b[i] + c[i];\n  }\n}\n\nTest: test-art-host, test-art-target\n\nChange-Id: I46af3b4e4a55004336672cdba3296b7622d815ca\n"
    },
    {
      "commit": "d58bc3212a968fe5a2e1fba51df9a7efedcf1b60",
      "tree": "62d442542629674b503d7005977e73c99b3d5d37",
      "parents": [
        "18df7714111bdd3c5737f1ef2fa587d9957f8a2f"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon May 01 14:49:18 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon May 01 15:14:27 2017 -0700"
      },
      "message": "Allow same-length integral type mixing in SIMD.\n\nRationale:\nJust like the incoming sequential code, the SIMD\ncode allows for some type matching, as long as\nit is integral and same length.\n\nBug: 37764324\nTest: test-art-target, test-art-host\nChange-Id: Ide1c5403e0f3b8c5372e8ac6dd282d8211ca8f1b\n"
    },
    {
      "commit": "db14fcf45effb7dd4b3febd697ff5f0541119835",
      "tree": "4197a7be031e7206b1c4f55a51821e9b273b1b36",
      "parents": [
        "06660db82d6b3d59080584431addf3797a468a70"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Apr 25 15:53:58 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Apr 25 16:13:55 2017 -0700"
      },
      "message": "Pack booleans in the already existing bit field.\n\nAlso adds is_string_char_at boolean in preparation of\n[un]compressed string vectorization support.\n\nTest: test-art-target, test-art-host\nChange-Id: Ia99b28564727bf91b3d5cfc49f6d40a4dd1ffd3b\n"
    },
    {
      "commit": "8de5916666ab5d146ac1bdac7d7748e197ae347e",
      "tree": "87a7cfda1a91ef4335f78a59edf2d5fcca6e8e46",
      "parents": [
        "f99f62f8e04aecbbe1615e242a19ac475f66e565"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Apr 21 09:42:01 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Apr 21 11:00:26 2017 -0700"
      },
      "message": "Factor vector unary/binary shared code out into superclass.\n\nTest: test-art-target, test-art-host\nChange-Id: I42770d9a9142f2e53d3b5bd60bd25593b2154a7c\n"
    },
    {
      "commit": "f34dd206d0073fb3949be872224420a8488f551f",
      "tree": "b24b451af6efdd9f67c4cbd5c37ebb4ec6a4aaad",
      "parents": [
        "1f56cb5c594f5757085820b1042988d10f02bb0b"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Mon Apr 10 17:41:46 2017 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu Apr 20 00:21:29 2017 +0100"
      },
      "message": "ARM64: Support MultiplyAccumulate for SIMD.\n\nTest: test-art-host, test-art-target.\n\nChange-Id: I06af8415e15352d09d176cae828163cbe99ae7a7\n"
    },
    {
      "commit": "f3e61ee363fe7f82ef56704f06d753e2034a67dd",
      "tree": "a00f1fce4a2e284b0a03f941f530afc5b5c56b59",
      "parents": [
        "741a81af441cbcb7255229bf250bc009d2894e92"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Apr 12 17:09:20 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Apr 19 10:30:57 2017 -0700"
      },
      "message": "Implement halving add idiom (with checker tests).\n\nRationale:\nFirst of several idioms that map to very efficient SIMD instructions.\nNote that the is-zero-ext and is-sign-ext are general-purpose utilities\nthat will be widely used in the vectorizer to detect low precision\nidioms, so expect that code to be shared with many CLs to come.\n\nTest: test-art-host, test-art-target\nChange-Id: If7dc2926c72a2e4b5cea15c44ef68cf5503e9be9\n"
    },
    {
      "commit": "6daebeba6ceab4e7dff5a3d65929eeac9a334004",
      "tree": "6aa2948896c6a731531451840a9a8bb26854cdd8",
      "parents": [
        "7cd18fb5a7ce83d98b1bbc3c55583fc5f93dc16f"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Apr 03 14:35:41 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Apr 05 09:24:01 2017 -0700"
      },
      "message": "Implemented ABS vectorization.\n\nRationale:\nThis CL adds the concept of vectorizing intrinsics\nto the ART vectorizer. More can follow (MIN, MAX, etc).\n\nTest: test-art-host, test-art-target (angler)\nChange-Id: Ieed8aa83ec64c1250ac0578570249cce338b5d36\n"
    },
    {
      "commit": "f8f5a16ed7bad1e18179e38453e59c96a944de10",
      "tree": "53369083a97103563467cc5910a439a1864dd0b1",
      "parents": [
        "7298b1ae3e9af5fdb46d168302a26cfbf5d475f5"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Feb 06 15:35:29 2017 -0800"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Mar 31 10:58:11 2017 -0700"
      },
      "message": "ART vectorizer.\n\nRationale:\nMake SIMD great again with a retargetable and easily extendable vectorizer.\n\nProvides a full x86/x86_64 and a proof-of-concept ARM implementation. Sample\nimprovement (without any perf tuning yet) for Linpack on x86 is about 20% to 50%.\n\nTest: test-art-host, test-art-target (angler)\nBug: 34083438, 30933338\n\nChange-Id: Ifb77a0f25f690a87cd65bf3d5e9f6be7ea71d6c1\n"
    }
  ]
}