)]}' { "log": [ { "commit": "95e7ffc28ea4d6deba356e636b16120ae49b62e2", "tree": "f365f762a4ff46042871b86b96c112d6f1c8d624", "parents": [ "c24b8df48be848af1f4cb54e9caef2b7d6afe680" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jan 22 11:57:25 2016 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jan 22 11:57:25 2016 +0000" }, "message": "Improve documentation and assertions of read barrier instrumentation.\n\nFor ARM, x86, x86-64 back ends. The case of the ARM64 back\nend is already handled in\nhttps://android-review.googlesource.com/#/c/197870/.\n\nBug: 12687968\nChange-Id: I6df1128cc100cbdb89020876e1a54de719508be3\n" }, { "commit": "6b5afdd144d2bb3bf994240797834b5666b2cf98", "tree": "d536cd7b3aaf55c563e82c2c522521a91b2bb953", "parents": [ "debeb98aaa8950caf1a19df490f2ac9bf563075b" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 22 09:31:52 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 22 09:31:52 2016 +0000" }, "message": "Revert \"ARM/ARM64: Extend support of instruction combining.\"\n\nThe test fails its checker parts.\n\nThis reverts commit debeb98aaa8950caf1a19df490f2ac9bf563075b.\n\nChange-Id: I49929e15950c7814da6c411ecd2b640d12de80df\n" }, { "commit": "debeb98aaa8950caf1a19df490f2ac9bf563075b", "tree": "b2a7a7cc6fb2f56d4bcc6cecaa80035668f38dc4", "parents": [ "6aadaef35ea52506db61e463910c2520b702ca5e" ], "author": { "name": "Ilmir Usmanov", "email": "i.usmanov@samsung.com", "time": "Fri Dec 11 11:39:44 2015 +0300" }, "committer": { "name": "Artem Udovichenko", "email": "artem.u@samsung.com", "time": "Thu Jan 21 11:07:38 2016 +0300" }, "message": "ARM/ARM64: Extend support of instruction combining.\n\nCombine multiply instructions in the following way:\nARM64:\nMUL/NEG -\u003e MNEG\nARM32 (32-bit integers only):\nMUL/ADD -\u003e MLA\nMUL/SUB -\u003e MLS\n\nChange-Id: If20f2d8fb060145ab6fbceeb5a8f1a3d02e0ecdb\n" }, { "commit": "e3f43ac79e50a4693ea4d46acf5cffca64910cee", "tree": "848caf115a3251ffc3c9fc60290549a52765801a", "parents": [ "17ccfff2de292fd2b4a78aef87d79b662381f920" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jan 19 15:07:47 2016 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jan 19 15:07:47 2016 +0000" }, "message": "Some read barrier clean-up in Optimizing.\n\nThese changes make the read barrier compiler instrumentation\ncode more uniform among the ARM, ARM64, x86 and x86-64 back\nends.\n\nBug: 12687968\nChange-Id: I6b1c0cf2bc22ed6cd6b14754136bef4a2a036ea5\n" }, { "commit": "58282f4510961317b8d5a364a6f740a78926716f", "tree": "5d97c0db9fe01dd6e8df2357ef11f614abb853e8", "parents": [ "b8bb9f6d0b59be125066f604f134155f8998f5ae" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Jan 14 12:45:10 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Jan 18 16:39:30 2016 +0000" }, "message": "ART: Remove Baseline compiler\n\nWe don\u0027t need Baseline any more and it hasn\u0027t been maintained for\na while anyway. Let\u0027s remove it.\n\nChange-Id: I442ed26855527be2df3c79935403a25b1ee55df6\n" }, { "commit": "42249c3602c3d0243396ee3627ffb5906aa77c1e", "tree": "1e822a21c87331246cbde3923eac88fa315fa2cc", "parents": [ "922698ded1e80cad1ecce4c2172a88c76a216373" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Jan 07 15:33:50 2016 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Jan 12 16:39:20 2016 -0800" }, "message": "Reduce code size by sharing slow paths.\n\nRationale:\nSharing identical slow path code reduces code size.\n\nBackground:\nCurrently, slow paths with the same dex-pc, same physical register\nspilling code, and identical stack maps are shared (making this\nonly useful for deopt slow paths). The newly introduced mechanism\nis sufficiently general to allow future improvements by e.g.\nallowing different dex-pc (by passing this to runtime) or even\nthe kind of slow paths (by passing runtime addresses to the slowpath).\n\nChange-Id: I819615c47b4fd98440a241f681f93e4fc22d12e0\n" }, { "commit": "3da15f8b1097905e06a59149c3a4a9658cbb7d5e", "tree": "1c572d200ee0382b33d33e038b5b228b16c198c0", "parents": [ "a21489e7fa07722d340f69a12921cd7aa9ee4a17", "ac6ac10a0801fa6eb95e0ab0c72b2ed562210b34" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jan 12 12:19:19 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jan 12 12:19:19 2016 +0000" }, "message": "Merge \"Optimizing/ARM: Fix CmpConstant().\"" }, { "commit": "c928591f5b2c544751bb3fb26dc614d3c2e67bef", "tree": "b6c8a5e08c4d4c7a66a70f4d91e209ededf22334", "parents": [ "5ee288c9dd99614e3a238f5efceeec6456e3499d" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Dec 18 10:38:42 2015 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jan 08 12:55:31 2016 +0000" }, "message": "ARM Baker\u0027s read barrier fast path implementation.\n\nIntroduce an ARM fast path implementation in Optimizing for\nBaker\u0027s read barriers (for both heap reference loads and GC\nroot loads). The marking phase of the read barrier is\nperformed by a slow path, invoking the runtime entry point\nartReadBarrierMark.\n\nOther read barrier algorithms continue to use the original\nslow path based implementation, which has been renamed as\nGenerateReadBarrierSlow/GenerateReadBarrierForRootSlow.\n\nBug: 12687968\nChange-Id: Ie7ee85b1b4c0564148270cebdd3cbd4c3da51b3a\n" }, { "commit": "5f7b58ea1adfc0639dd605b65f59198d3763f801", "tree": "04556e673cdd3967cc967ff79931eab49e523956", "parents": [ "1201804d1813d7db0accead9721d67c40b3de564" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Nov 23 19:49:34 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Dec 23 09:59:07 2015 +0000" }, "message": "Rewrite HInstruction::Is/As\u003ctype\u003e().\n\nMake Is\u003ctype\u003e() and As\u003ctype\u003e() non-virtual for concrete\ninstruction types, relying on GetKind(), and mark GetKind()\nas PURE to improve optimization opportunities. This reduces\nthe number of relocations in libart-compiler.so\u0027s .rel.dyn\nsection by ~4K, or ~44%, and in .data.rel.ro by ~18K, or\n~65%. The file is 96KiB smaller for Nexus 5, including 8KiB\nreduction of the .text section.\n\nUnfortunately, the g++/clang++ __attribute__((pure)) is not\nstrong enough to avoid duplicated virtual calls and we would\nneed the C++ [[pure]] attribute proposed in n3744 instead.\nTo work around this deficiency, we introduce an extra\nnon-virtual indirection for GetKind(), so that the compiler\ncan optimize common expressions such as\n instruction-\u003eIsAdd() || instruction-\u003eIsSub()\nor\n instruction-\u003eIsAdd() \u0026\u0026 instruction-\u003eAsAdd()-\u003e...\nwhich contain two virtual calls to GetKind() after inlining.\n\nChange-Id: I83787de0671a5cb9f5b0a5f4a536cef239d5b401\n" }, { "commit": "ac6ac10a0801fa6eb95e0ab0c72b2ed562210b34", "tree": "3758a1903dbdd273c35d4bae4ee0e820857946c0", "parents": [ "1201804d1813d7db0accead9721d67c40b3de564" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Dec 17 12:14:00 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Dec 22 11:51:33 2015 +0000" }, "message": "Optimizing/ARM: Fix CmpConstant().\n\nCMN updates flags based on addition of its operands.\nDo not confuse the \"N\" suffix with bitwise inversion\nperformed by MVN.\n\nAlso add more special cases analogous to AddConstant()\nand use CmpConstant() more in code generator.\n\nChange-Id: I0d4571770a3f0fdf162e97d4bde56814098e7246\n" }, { "commit": "40a04bf64e5837fa48aceaffe970c9984c94084a", "tree": "27aeff3b9492b396050155734d81aba3c57ffbb7", "parents": [ "763fd2d3d131898cad6295a19ae9a30e22ce5f2a" ], "author": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Fri Dec 11 09:50:36 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Dec 11 16:13:44 2015 +0000" }, "message": "Replace rotate patterns and invokes with HRor IR.\n\nReplace constant and register version bitfield rotate patterns, and\nrotateRight/Left intrinsic invokes, with new HRor IR.\n\nWhere k is constant and r is a register, with the UShr and Shl on\neither side of a |, +, or ^, the following patterns are replaced:\n\n x \u003e\u003e\u003e #k OP x \u003c\u003c #(reg_size - k)\n x \u003e\u003e\u003e #k OP x \u003c\u003c #-k\n\n x \u003e\u003e\u003e r OP x \u003c\u003c (#reg_size - r)\n x \u003e\u003e\u003e (#reg_size - r) OP x \u003c\u003c r\n\n x \u003e\u003e\u003e r OP x \u003c\u003c -r\n x \u003e\u003e\u003e -r OP x \u003c\u003c r\n\nImplemented for ARM/ARM64 \u0026 X86/X86_64.\n\nTests changed to not be inlined to prevent optimization from folding\nthem out. Additional tests added for constant rotate amounts.\n\nChange-Id: I5847d104c0a0348e5792be6c5072ce5090ca2c34\n" }, { "commit": "b4536b7de576b20c74c612406c5d3132998075ef", "tree": "5265c07b51b4d79b2fd64c63d9b78d38b7601a8f", "parents": [ "883ef45b5d5a2e4005914c7b339881900976b6e7" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Nov 24 13:45:23 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Dec 01 11:38:03 2015 +0000" }, "message": "Optimizing/ARM: Implement kDexCachePcRelative dispatch.\n\nChange-Id: I0fe2da50a30a3f62bec8ea01688dd1fec84b1831\n" }, { "commit": "3b359c71f2fb784589be113206932e76807787bb", "tree": "f50f1b98a2948668d2ffabc42ce0cd9a00cecd0c", "parents": [ "a04f57badca0a9211d45eb7bde44c1d1e8f159ff" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Nov 17 19:35:12 2015 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Nov 17 19:35:12 2015 +0000" }, "message": "ARM read barrier support for concurrent GC in Optimizing.\n\nThis first implementation uses slow paths to instrument heap\nreference loads and GC root loads for the concurrent copying\ncollector, respectively calling the artReadBarrierSlow and\nartReadBarrierForRootSlow runtime entry points.\n\nNotes:\n- This implementation does not instrument HInvokeVirtual\n nor HInvokeInterface instructions (for class reference\n loads), as the corresponding read barriers are not stricly\n required with the current concurrent copying collector.\n- Intrinsics which may eventually call (on slow path) are\n disabled when read barriers are enabled, as the current\n slow path infrastructure does not support this case.\n- When read barriers are enabled, the code generated for a\n HArraySet instruction always go into the array set slow\n path for object arrays (delegating the operation to the\n runtime), as we are lacking a mechanism to keep a\n temporary register live accross a runtime call (needed for\n the instrumentation of type checking code, which requires\n two successive read barriers).\n\nBug: 12687968\nChange-Id: I92e8db414d029f952c07f3d3a98069e46dfdbc2a\n" }, { "commit": "0debae7bc89eb05f7a2bf7dccd223318fad7c88d", "tree": "3da9656dc77d271b12c1b02793e7d713ae3da790", "parents": [ "991842a5273d20695dd5f35eb9a9e28c386c5b4b" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Nov 12 18:37:00 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Nov 17 15:12:00 2015 +0000" }, "message": "ART: Refactor GenerateTestAndBranch\n\nEach code generator implements a method for generating condition\nevaluation and branching to arbitrary labels. This patch refactors\nit for better clarity but also to generate fewer jumps when the true\nbranch is the fallthrough successor.\n\nThis is preliminary work for implementing HSelect.\n\nChange-Id: Iaa545a5ecbacb761c5aa241fa69140cf6eb5952f\n" }, { "commit": "dc151b2346bb8a4fdeed0c06e54c2fca21d59b5d", "tree": "391d8ccb44ff9e6fc1c8fa8975e534e20cc002ff", "parents": [ "823e693aa946ba75cd047429e1290011a2ed8729" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 15 18:02:30 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 23 14:45:32 2015 +0100" }, "message": "Optimizing: Determine invoke-static/-direct dispatch early.\n\nDetermine the dispatch type of invoke-static/-direct in a\nspecial pass right after the type inference. This allows the\ninliner to pass the \"needs dex cache\" check and inline more.\nIt also allows the code generator to avoid requesting a\nregister location for the ArtMethod* for kDexCachePcRelative\nand direct methods.\n\nThe supported dispatch check handles also situations that\nthe CompilerDriver currently doesn\u0027t allow. The cleanup of\nthe CompilerDriver and required changes to Quick will come\nin a separate change.\n\nChange-Id: I3f8e903a119949e95871d8ab0a995f4731a13a07\n" }, { "commit": "d2b4ca2d02c86b1ce1826fd2b35ce6c9c58c1ff1", "tree": "dab4cdfacd3e7cb529f3b0de931c8a173039571f", "parents": [ "fb11bab9bc96ff05dcb12f43abf58df256b7c7aa" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Sep 14 15:13:26 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 14 12:20:59 2015 +0100" }, "message": "Improve Thumb2 bitwise operations.\n\nAllow embedding constants in AND, ORR, EOR. Add ORN to\nassembler, use BIC and ORN for AND and ORR when needed.\n\nChange-Id: I24d69ecc7ce6992b9c5eb7a313ff47a942de9661\n" }, { "commit": "e460d1df1f789c7c8bb97024a8efbd713ac175e9", "tree": "3511036fb18828dd0ee140d33a8bcd0535ebeab6", "parents": [ "25217af2a7cae96b32ba566aaf697288f3374c99" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Sep 29 04:52:17 2015 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Oct 02 02:25:18 2015 +0100" }, "message": "Revert \"Revert \"Support unresolved fields in optimizing\"\n\nThe CL also changes the calling convetion for 64bit static field set\nto use kArg2 instead of kArg1. This allows optimizing to keep\nthe asumptions:\n- arm pairs are always of form (even_reg, odd_reg)\n- ecx_edx is not used as a register on x86.\n\nThis reverts commit e6f49b47b6a4dc9c7684e4483757872cfc7ff1a1.\n\nChange-Id: I93159917565824084abc96775f31be1a4249f2f3\n" }, { "commit": "225b6464a58ebe11c156144653f11a1c6607f4eb", "tree": "3f1c6067c3841c892edaa1a60a61af9c559cb4e4", "parents": [ "6a9984e62c08bcd78c8e49dd40b1f0f9d53513b7" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Sep 28 12:17:40 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Sep 29 10:49:35 2015 +0100" }, "message": "Optimizing: Tag arena allocations in code generators.\n\nAnd completely remove the deprecated GrowableArray.\n\nReplace GrowableArray with ArenaVector in code generators\nand related classes and tag arena allocations.\n\nLabel arrays use direct allocations from ArenaAllocator\nbecause Label is non-copyable and non-movable and as such\ncannot be really held in a container. The GrowableArray\nnever actually constructed them, instead relying on the\nzero-initialized storage from the arena allocator to be\ncorrect. We now actually construct the labels.\n\nAlso avoid StackMapStream::ComputeDexRegisterMapSize() being\npassed null references, even though unused.\n\nChange-Id: I26a46fdd406b23a3969300a67739d55528df8bf4\n" }, { "commit": "85b62f23fc6dfffe2ddd3ddfa74611666c9ff41d", "tree": "c916b01b1608558a7d8c9d100274c4c6b6706386", "parents": [ "6766eae2d91e894b4ceab9f29cc983900e7bc0c7" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Sep 09 13:15:38 2015 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Sep 17 14:41:52 2015 -0700" }, "message": "ART: Refactor intrinsics slow-paths\n\nRefactor slow paths so that there is a default implementation for\ncommon cases (only arm64 with vixl is special). Write a generic\nintrinsic slow-path that can be reused for the specific architectures.\nMove helper functions into CodeGenerator so that they are accessible.\n\nChange-Id: Ibd788dce432601c6a9f7e6f13eab31f28dcb8550\n" }, { "commit": "e6f49b47b6a4dc9c7684e4483757872cfc7ff1a1", "tree": "6a5f45136832f73138ced75fcd3c6110b74116ea", "parents": [ "23a8e35481face09183a24b9d11e505597c75ebb" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Sep 17 14:04:33 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Sep 17 14:04:33 2015 +0000" }, "message": "Revert \"Support unresolved fields in optimizing\"\nbreaks debuggable tests.\n\nThis reverts commit 23a8e35481face09183a24b9d11e505597c75ebb.\n\nChange-Id: I8e60b5c8f48525975f25d19e5e8066c1c94bd2e5\n" }, { "commit": "23a8e35481face09183a24b9d11e505597c75ebb", "tree": "bcaafb6ea001349acbf160c2cc89334fab4a38dc", "parents": [ "175dc732c80e6f2afd83209348124df349290ba8" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Sep 08 19:56:31 2015 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Sep 17 12:29:59 2015 +0100" }, "message": "Support unresolved fields in optimizing\n\nChange-Id: I9941fa5fcb6ef0a7a253c7a0b479a44a0210aad4\n" }, { "commit": "175dc732c80e6f2afd83209348124df349290ba8", "tree": "6a5f45136832f73138ced75fcd3c6110b74116ea", "parents": [ "5d01db1aa7634a012109d43e6403451b76de1daa" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Aug 25 15:42:32 2015 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Sep 17 12:29:51 2015 +0100" }, "message": "Support unresolved methods in Optimizing\n\nChange-Id: If2da02b50d2fa668cd58f134a005f1752e7746b1\n" }, { "commit": "fe157012b6d760c275d944ff83e8bea371c59b09", "tree": "a2b013dded6e25cab1d3ff5abf09c426904e142c", "parents": [ "aef880c4b872ccf1a63a3c563cb056ae117fc9c8", "ecc4366670e12b4812ef1653f7c8d52234ca1b1f" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Sep 16 14:33:16 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Sep 16 14:33:16 2015 +0000" }, "message": "Merge \"Add OptimizingCompilerStats to the CodeGenerator class.\"" }, { "commit": "fa6b93c4b69e6d7ddfa2a4ed0aff01b0608c5a3a", "tree": "3528c88e104dac8e58ae5370ab066b8b1dd0218f", "parents": [ "e295be4a95d7861f6ec179edf6565f58cad747cc" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Sep 15 10:15:55 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 16 13:21:33 2015 +0100" }, "message": "Optimizing: Tag arena allocations in HGraph.\n\nReplace GrowableArray with ArenaVector in HGraph and related\nclasses HEnvironment, HLoopInformation, HInvoke and HPhi,\nand tag allocations with new arena allocation types.\n\nChange-Id: I3d79897af405b9a1a5b98bfc372e70fe0b3bc40d\n" }, { "commit": "bfb5ba90cd6425ce49c2125a87e3b12222cc2601", "tree": "6280171d451642dc70c87894d553f76c6c12db0a", "parents": [ "e6576390f957c82c2aede438834d028066757368" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Sep 01 15:45:02 2015 +0000" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Sep 08 20:36:09 2015 -0700" }, "message": "Revert \"Revert \"Do a second check for testing intrinsic types.\"\"\n\nThis reverts commit a14b9fef395b94fa9a32147862c198fe7c22e3d7.\n\nWhen an intrinsic with invoke-type virtual is recognized, replace\nthe instruction with a new HInvokeStaticOrDirect.\n\nMinimal update for dex-cache rework. Fix includes.\n\nChange-Id: I1c8e735a2fa7cda4419f76ca0717125ef236d332\n" }, { "commit": "ecc4366670e12b4812ef1653f7c8d52234ca1b1f", "tree": "fe7be52b1025b8122547b34d8765248d5959cd3a", "parents": [ "772cc4a2d4f978888d1b1e5a78c1c16a108260ed" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Thu Aug 13 13:33:12 2015 +0100" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Thu Aug 27 15:28:25 2015 +0100" }, "message": "Add OptimizingCompilerStats to the CodeGenerator class.\n\nJust refactoring, not yet used, but will be used by the incoming patch\nseries and future CodeGen specific stats.\n\nChange-Id: I7d20489907b82678120518a77bdab9c4cc58f937\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@linaro.org\u003e\n" }, { "commit": "581550137ee3a068a14224870e71aeee924a0646", "tree": "f62dd0d07c66a8ce4d7d994ee0e9c27bd8014bb1", "parents": [ "32f264e67afa8654a5570d38b627515fb73fc333" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 19 12:49:41 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 19 18:54:36 2015 +0100" }, "message": "Revert \"Revert \"Optimizing: Better invoke-static/-direct dispatch.\"\"\n\nFixed kCallArtMethod to use correct callee location for\nkRecursive. This combination is used when compiling with\ndebuggable flag set.\n\nThis reverts commit b2c431e80e92eb6437788cc544cee6c88c3156df.\n\nChange-Id: Idee0f2a794199ebdf24892c60f8a5dcf057db01c\n" }, { "commit": "b2c431e80e92eb6437788cc544cee6c88c3156df", "tree": "6c0ac5f843845e4b09829eb0fd9f1b3013cf4494", "parents": [ "9b688a095afbae21112df5d495487ac5231b12d0" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 19 12:45:42 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 19 12:45:42 2015 +0000" }, "message": "Revert \"Optimizing: Better invoke-static/-direct dispatch.\"\n\nReverting due to failing ndebug tests.\n\nThis reverts commit 9b688a095afbae21112df5d495487ac5231b12d0.\n\nChange-Id: Ie4f69da6609df3b7c8443412b6cf7f5c43c2c5d9\n" }, { "commit": "9b688a095afbae21112df5d495487ac5231b12d0", "tree": "e5e881d4d124803e66f1e90c1e0a0e4c90d22e13", "parents": [ "009c34cba875885d9540696f33255a9b355d6e15" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 06 14:12:42 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 19 12:23:37 2015 +0100" }, "message": "Optimizing: Better invoke-static/-direct dispatch.\n\nAdd framework for different types of loading ArtMethod*\nand code pointer retrieval. Implement invoke-static and\ninvoke-direct calls the same way as Quick. Document the\ndispatch kinds in HInvokeStaticOrDirect\u0027s new enumerations\nMethodLoadKind and CodePtrLocation.\n\nPC-relative loads from dex cache arrays are used only for\nx86-64 and arm64. The implementation for other architectures\nwill be done in separate CLs.\n\nChange-Id: I468ca4d422dbd14748e1ba6b45289f0d31734d94\n" }, { "commit": "4fa13f65ece3b68fe3d8722d679ebab8656bbf99", "tree": "09939739f6ae87e05e91d370007e978b5e72ca8e", "parents": [ "c470193cfc522fc818eb2eaab896aef9caf0c75a" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jul 06 18:11:54 2015 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jul 08 15:45:22 2015 +0100" }, "message": "Fuse long and FP compare \u0026 condition on ARM in Optimizing.\n\nAlso:\n- Stylistic changes in corresponding parts on the x86 and\n x86-64 code generators.\n- Update and improve the documentation of\n art::arm::Condition.\n\nBug: 21120453\nChange-Id: If144772046e7d21362c3c2086246cb7d011d49ce\n" }, { "commit": "b485915afd8a6396df7863b651dfe832038fd680", "tree": "4d12daee263e31d9603e962c1606cae3356faafe", "parents": [ "4a08e17a9db0f68b9623849bc288c31a47868fbc", "fc6a86ab2b70781e72b807c1798b83829ca7f931" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Jun 26 14:52:36 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jun 26 14:52:36 2015 +0000" }, "message": "Merge \"Revert \"Revert \"ART: Implement try/catch blocks in Builder\"\"\"" }, { "commit": "fc6a86ab2b70781e72b807c1798b83829ca7f931", "tree": "90201491e811cf7be0e0469d7a06a828f4384cad", "parents": [ "d3eaade87ac079accca30473ef0a3b38ab600828" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Jun 26 10:33:45 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Jun 26 13:49:50 2015 +0100" }, "message": "Revert \"Revert \"ART: Implement try/catch blocks in Builder\"\"\n\nThis patch enables the GraphBuilder to generate blocks and edges which\nrepresent the exceptional control flow when try/catch blocks are\npresent in the code. Actual compilation is still delegated to Quick\nand Baseline ignores the additional code.\n\nTo represent the relationship between try and catch blocks, Builder\nsplits the edges which enter/exit a try block and links the newly\ncreated blocks to the corresponding exception handlers. This layout\nwill later enable the SsaBuilder to correctly infer the dominators of\nthe catch blocks and to produce the appropriate reverse post ordering.\nIt will not, however, allow for building the complete SSA form of the\ncatch blocks and consequently optimizing such blocks.\n\nTo this end, a new TryBoundary control-flow instruction is introduced.\nCodegen treats it the same as a Goto but it allows for additional\nsuccessors (the handlers).\n\nThis reverts commit 3e18738bd338e9f8363b26bc895f38c0ec682824.\n\nChange-Id: I4f5ea961848a0b83d8db3673763861633e9bfcfb\n" }, { "commit": "3e18738bd338e9f8363b26bc895f38c0ec682824", "tree": "708013ef06cfb524f040b2b5c494f7f3cb84ac2c", "parents": [ "0b5c7d1994b76090afcc825e737f2b8c546da2f8" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Jun 26 09:59:52 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Jun 26 09:59:52 2015 +0000" }, "message": "Revert \"ART: Implement try/catch blocks in Builder\"\n\nCauses OutOfMemory issues, need to investigate.\n\nThis reverts commit 0b5c7d1994b76090afcc825e737f2b8c546da2f8.\n\nChange-Id: I263e6cc4df5f9a56ad2ce44e18932ca51d7e349f\n" }, { "commit": "0b5c7d1994b76090afcc825e737f2b8c546da2f8", "tree": "057eddf8830b1991f02af3c3ce1b63dee90dd2ad", "parents": [ "1dd3136d9f6b1c7d551897a2d96c8314e40f7324" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Jun 11 11:17:49 2015 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Jun 25 16:58:08 2015 +0100" }, "message": "ART: Implement try/catch blocks in Builder\n\nThis patch enables the GraphBuilder to generate blocks and edges which\nrepresent the exceptional control flow when try/catch blocks are\npresent in the code. Actual compilation is still delegated to Quick\nand Baseline ignores the additional code.\n\nTo represent the relationship between try and catch blocks, Builder\nsplits the edges which enter/exit a try block and links the newly\ncreated blocks to the corresponding exception handlers. This layout\nwill later enable the SsaBuilder to correctly infer the dominators of\nthe catch blocks and to produce the appropriate reverse post ordering.\nIt will not, however, allow for building the complete SSA form of the\ncatch blocks and consequently optimizing such blocks.\n\nTo this end, a new TryBoundary control-flow instruction is introduced.\nCodegen treats it the same as a Goto but it allows for additional\nsuccessors (the handlers).\n\nChange-Id: I415b985596d5bebb7b1bb358a46e08b7b04bb53a\n" }, { "commit": "f39e0641a6d1a6561b20f6a130d1e763788cd70b", "tree": "1679d6e1c2e77593d67fc519fe8cb8f94ddd6d5e", "parents": [ "a256ee9ccbd01407541958476f388ae7c687a9c2" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Tue Jun 23 11:33:45 2015 +0100" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Jun 24 08:17:25 2015 -0400" }, "message": "Minor fixes to mips64 for the arch-specific optimisation framework.\n\nChange-Id: I9d49ea61c732e4fc6b3393aa8778951e29ce4efe\n" }, { "commit": "a4f3581da73b83484a30ab499c4f8ad43b378dab", "tree": "a4f11578fc3df63ed9d63e248f01d09d4ff18438", "parents": [ "2d655f1ce89a714094a4f55ac75edcf9a34c7e24" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 22 23:12:45 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jun 23 11:02:44 2015 +0100" }, "message": "Do not overwrite an input register in shift operations.\n\n\u0027second_reg\u0027 is an input register that can survive the instruction.\nInstead use the output register as a temporary result.\n\nbug:21667432\nChange-Id: I1a4577b0333c3fb184645023d5eae30555bbf65c\n" }, { "commit": "eb7b7399dbdb5e471b8ae00a567bf4f19edd3907", "tree": "a0a488040883c14cc6cbec3186654137459d44ff", "parents": [ "8ec0e20347e13592539a8c0786b1db1735149800" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Jun 19 14:47:01 2015 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Jun 22 11:57:36 2015 +0100" }, "message": "Opt compiler: Add disassembly to the \u0027.cfg\u0027 output.\n\nThis is automatically added to the \u0027.cfg\u0027 output when using the usual\n`--dump-cfg` option.\n\nChange-Id: I864bfc3a8299c042e72e451cc7730ad8271e4deb\n" }, { "commit": "cf93a5cd9c978f59113d42f9f642fab5e2cc8877", "tree": "55162627fcbf2cb7913a735c7ed89e8e4b5e84d7", "parents": [ "db40ea768bd914125c3754dacb9b6f534a2e2399" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 16 11:33:24 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jun 17 09:43:51 2015 +0100" }, "message": "Revert \"Revert \"ART: Implement literal pool for arm, fix branch fixup.\"\"\n\nThis reverts commit fbeb4aede0ddc5b1e6a5a3a40cc6266fe8518c98.\n\nAdjust block label positions. Bad catch block labels were the\nreason for the revert.\n\nChange-Id: Ia6950d639d46b9da6b07f3ade63ab46d03d63310\n" }, { "commit": "db40ea768bd914125c3754dacb9b6f534a2e2399", "tree": "af87ccb86c7e0622912bf088a464716166ea450a", "parents": [ "e4394f7de28ae0b517daa033749979e46ff676ab", "fbeb4aede0ddc5b1e6a5a3a40cc6266fe8518c98" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 16 11:32:24 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jun 16 11:32:25 2015 +0000" }, "message": "Merge \"Revert \"ART: Implement literal pool for arm, fix branch fixup.\"\"" }, { "commit": "fbeb4aede0ddc5b1e6a5a3a40cc6266fe8518c98", "tree": "76ab28cf259def4dccec529df217fd760f27d2aa", "parents": [ "f38caa68cce551fb153dff37d01db518e58ed00f" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 16 11:32:01 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 16 11:32:01 2015 +0000" }, "message": "Revert \"ART: Implement literal pool for arm, fix branch fixup.\"\n\nThis reverts commit f38caa68cce551fb153dff37d01db518e58ed00f.\n\nChange-Id: Id88b82cc949d288cfcdb3c401b96f884b777fc40\nReason: broke the tests.\n" }, { "commit": "e4394f7de28ae0b517daa033749979e46ff676ab", "tree": "320596587f320a0becda91cfe4fa72c8052fb90a", "parents": [ "f6c77d7632bdfe564c2ba61690fecc65f10ea9f6", "f38caa68cce551fb153dff37d01db518e58ed00f" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 16 09:06:59 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jun 16 09:07:00 2015 +0000" }, "message": "Merge \"ART: Implement literal pool for arm, fix branch fixup.\"" }, { "commit": "f38caa68cce551fb153dff37d01db518e58ed00f", "tree": "723612f20666f429b7c67321f0353d57425b1c63", "parents": [ "bd8c725e465cc7f44062745a6f2b73248f5159ed" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri May 29 15:50:18 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 15 15:13:28 2015 +0100" }, "message": "ART: Implement literal pool for arm, fix branch fixup.\n\nChange-Id: Iecc91418bb4ee1c957f42fefb737d0ee2ba960e7\n" }, { "commit": "ef20f71e16f035a39a329c8524d7e59ca6a11f04", "tree": "a2892ae08f22ccf46baa4c77cea61f32bd07242d", "parents": [ "864a2d955aa85ab989c86d7f1eeacbe0b11f8b0f" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Tue Jun 09 10:29:30 2015 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Wed Jun 10 10:19:57 2015 +0100" }, "message": "Add boilerplate code for architecture-specific HInstructions.\n\nChange-Id: I2723cd96e5f03012c840863dd38d7b2168117db8\n" }, { "commit": "69aa60163989c33a008115205d39732a76ecc1dc", "tree": "058392dc104a8e7b3594a548239dca2d3ec06cce", "parents": [ "aa77f6e5839b2ad3bf8ca2c06a44ec92e2667af1" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jun 09 10:34:25 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jun 09 16:01:49 2015 +0100" }, "message": "Revert \"Revert \"Pass current method to HNewInstance and HNewArray.\"\"\n\nProblem exposed by this change was fixed in:\nhttps://android-review.googlesource.com/#/c/154031/\n\nThis reverts commit 7b0e353b49ac3f464c662f20e20e240f0231afff.\n\nChange-Id: I680c13dc9db9ba223ab11c7af255222860b4e6d2\n" }, { "commit": "7b0e353b49ac3f464c662f20e20e240f0231afff", "tree": "b5c936df891b08521176065ccaddb1f9e27c9f46", "parents": [ "e21aa42e1341d34250742abafdd83311ad9fa737" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jun 09 09:25:50 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jun 09 09:25:50 2015 +0000" }, "message": "Revert \"Pass current method to HNewInstance and HNewArray.\"\n\n082-inline-execute fails on x86.\n\nThis reverts commit e21aa42e1341d34250742abafdd83311ad9fa737.\n\nChange-Id: Ib3fd25faee2e0128001e40d3d51a74f959bc4449\n" }, { "commit": "e21aa42e1341d34250742abafdd83311ad9fa737", "tree": "d2c9f8530e59876588d32f04b4effc25ebc0fa89", "parents": [ "c47908e8c32fd58bc4dc75998a80f706954db1dc" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 08 15:35:07 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 08 15:36:27 2015 +0100" }, "message": "Pass current method to HNewInstance and HNewArray.\n\nAlso remove unsed CodeGenerator::LoadCurrentMethod.\n\nChange-Id: I4b8d3f2a30b8e2c76b6b329a72555483c993cb73\n" }, { "commit": "c345f141f11faad177aa9635a78088d00cf66086", "tree": "0a9fbb0f1f90dfe273d94659f077cc1e6b84966c", "parents": [ "38207af82afb6f99c687f64b15601ed20d82220a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 04 17:17:32 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 04 17:17:32 2015 +0000" }, "message": "Revert \"Use HCurrentMethod in HInvokeStaticOrDirect.\"\n\nFails on baseline/x86.\n\nThis reverts commit 38207af82afb6f99c687f64b15601ed20d82220a.\n\nChange-Id: Ib71018367eb7c6046965494a7e996c22af3de403\n" }, { "commit": "38207af82afb6f99c687f64b15601ed20d82220a", "tree": "f9360949b92e5b6b01c5828c03ac67d01adffe1d", "parents": [ "6a0d5e7fe6dc0c9d3dd941ab991203f2d5d1c354" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 01 15:46:22 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 04 14:39:06 2015 +0100" }, "message": "Use HCurrentMethod in HInvokeStaticOrDirect.\n\nChange-Id: I0d15244b6b44c8b10079398c55da5071a3e3af66\n" }, { "commit": "fd88f16100cceafbfde1b4f095f17e89444d6fa8", "tree": "fdb6d0520ca419acef9e953e74dcbd7d908bc4dd", "parents": [ "1aebdae18678403bdac078cbbe1f7dd4243c44f3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 03 11:23:52 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 03 11:23:52 2015 +0100" }, "message": "Factorize code for common LocationSummary of HInvoke.\n\nThis is one step forward, we could factorize more, but\nI wanted to get this out of the way first.\n\nChange-Id: I6ae411a737eebaecb64974f47af507ce0cfbae85\n" }, { "commit": "e401d146407d61eeb99f8d6176b2ac13c4df1e33", "tree": "17927f9bfe7d2041b5942c89832d55f9dedb24c5", "parents": [ "2006b7b9b8e32722bd0d640c62549d8a0ac624b6" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed Apr 22 13:56:20 2015 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri May 29 18:45:49 2015 -0700" }, "message": "Move mirror::ArtMethod to native\n\nOptimizing + quick tests are passing, devices boot.\n\nTODO: Test and fix bugs in mips64.\n\nSaves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS.\nSome of the savings are from removal of virtual methods and direct\nmethods object arrays.\n\nBug: 19264997\nChange-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d\n" }, { "commit": "07276db28d654594e0e86e9e467cad393f752e6e", "tree": "6450e07d64045f0c0949b3423501316b672641c7", "parents": [ "17f1bc531ea2f8c1a6fac3def13dee1b901949dd" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 18 14:22:09 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 18 19:15:52 2015 +0100" }, "message": "Don\u0027t do a null test in MarkGCCard if the value cannot be null.\n\nChange-Id: I45687f6d3505178e2fc3689eac9cb6ab1b2c1e29\n" }, { "commit": "c66671076b12a0ee8b9d1ae782732cc91beacb73", "tree": "e8007c01f0bce06dcd3b0d6e2db9e7079fc4dd04", "parents": [ "ef4366a159ecdd357c98e577583bbe224d065128" ], "author": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Fri May 15 16:08:45 2015 +0800" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri May 15 16:10:29 2015 +0100" }, "message": "Opt compiler: Speedup div/rem by constants on arm32 and arm64.\n\nThis patch also includes:\n1. Add java test for div/rem negative constants.\n2. Fix a thumb2 encoding issue where the last operand is\n \"reg, shift #amount\" in some instructions.\n3. Support a simple filter in arm32 assembler test to filter out\n unsupported cases, such as \"smull r0, r0, r1, r2\".\n4. Add smull arm32 assembler test.\n5. Add smull/umull thumb2 test.\n6. Add test for the thumb2 encoding issue which is fixed in this\n patch.\n\nChange-Id: I1601bc9c38f70f11909f2816fe3ec105a158951e\n" }, { "commit": "2d27c8e338af7262dbd4aaa66127bb8fa1758b86", "tree": "e01e0bc57359df0bdf00c3da694c5403fb7fc9e6", "parents": [ "3adfc4bbe6c42d574bd2069d8e38a13d5ad98ccf" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Apr 28 15:48:45 2015 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Apr 29 14:09:17 2015 +0100" }, "message": "Refactor InvokeDexCallingConventionVisitor in Optimizing.\n\nChange-Id: I7ede0f59d5109644887bf5d39201d4e1bf043f34\n" }, { "commit": "ad4450e5c3ffaa9566216cc6fafbf5c11186c467", "tree": "eecf36e8e9d8112e765ad8840eb2d27f8d0415ab", "parents": [ "f8bdd9f3a002970e4b8fdcf6fe6730116f1626c3" ], "author": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Fri Apr 17 18:48:56 2015 +0800" }, "committer": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Fri Apr 17 18:54:08 2015 +0800" }, "message": "Opt compiler: Implement parallel move resolver without using swap.\n\nThe algorithm of ParallelMoveResolverNoSwap() is almost the same with\nParallelMoveResolverWithSwap(), except the way we resolve the circular\ndependency. NoSwap() uses additional scratch register to resolve the\ncircular dependency. For example, (0-\u003e1) (1-\u003e2) (2-\u003e0) will be performed\nas (2-\u003escratch) (1-\u003e2) (0-\u003e1) (scratch-\u003e0).\n\nOn architectures without swap register support, NoSwap() can reduce the\nnumber of moves from 3x(N-1) to (N+1) when there is circular dependency\nwith N moves.\n\nAnd also, NoSwap() algorithm does not depend on architecture register\nlayout information, which means it can support register pairs on arm32\nand X/W, D/S registers on arm64 without additional modification.\n\nChange-Id: Idf56bd5469bb78c0e339e43ab16387428a082318\n" }, { "commit": "d43b3ac88cd46b8815890188c9c2b9a3f1564648", "tree": "6c599c3f40d57e92786bd7f41c0541d9eaa2643b", "parents": [ "a109632b240f3c9355ca95500f6f48e4478e3c51" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Wed Apr 01 14:03:04 2015 -0700" }, "committer": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Wed Apr 01 14:05:13 2015 -0700" }, "message": "Revert \"Revert \"Deoptimization-based bce.\"\"\n\nThis reverts commit 0ba627337274ccfb8c9cb9bf23fffb1e1b9d1430.\n\nChange-Id: I1ca10d15bbb49897a0cf541ab160431ec180a006\n" }, { "commit": "d75948ac93a4a317feaf136cae78823071234ba5", "tree": "7593fb8c1ba2b67decdaa967b6348501f58d8b9d", "parents": [ "b3665e3dfdd23cc7a2f17a0b53bb16205bf4151f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 27 09:53:16 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 27 12:01:40 2015 +0000" }, "message": "Intrinsify String.compareTo.\n\nChange-Id: Ia540df98755ac493fe61bd63f0bd94f6d97fbb57\n" }, { "commit": "0ba627337274ccfb8c9cb9bf23fffb1e1b9d1430", "tree": "0e1d0813c1d8d1c7239a900c1653296975713df0", "parents": [ "e295e6ec5beaea31be5d7d3c996cd8cfa2053129" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Mar 24 02:39:46 2015 +0000" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Mar 24 02:39:46 2015 +0000" }, "message": "Revert \"Deoptimization-based bce.\"\n\nThis breaks compiling the core image:\n\n Error after BCE: art::SSAChecker: Instruction 219 in block 1 does not dominate use 221 in block 1.\n\nThis reverts commit e295e6ec5beaea31be5d7d3c996cd8cfa2053129.\n\nChange-Id: Ieeb48797d451836ed506ccb940872f1443942e4e\n" }, { "commit": "e295e6ec5beaea31be5d7d3c996cd8cfa2053129", "tree": "4d8a657d23d511743ce35bee596544d7f652efdb", "parents": [ "d24ba2c44c76a2b2dd13aafe8f7981c15be31a98" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Sat Mar 07 06:37:59 2015 -0800" }, "committer": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Mon Mar 23 16:39:37 2015 -0700" }, "message": "Deoptimization-based bce.\n\nA mechanism is introduced that a runtime method can be called\nfrom code compiled with optimizing compiler to deoptimize into\ninterpreter. This can be used to establish invariants in the managed code\nIf the invariant does not hold at runtime, we will deoptimize and continue\nexecution in the interpreter. This allows to optimize the managed code as\nif the invariant was proven during compile time. However, the exception\nwill be thrown according to the semantics demanded by the spec.\n\nThe invariant and optimization included in this patch are based on the\nlength of an array. Given a set of array accesses with constant indices\n{c1, ..., cn}, we can optimize away all bounds checks iff all 0 \u003c\u003d min(ci) and\nmax(ci) \u003c array-length. The first can be proven statically. The second can be\nestablished with a deoptimization-based invariant. This replaces n bounds\nchecks with one invariant check (plus slow-path code).\n\nChange-Id: I8c6e34b56c85d25b91074832d13dba1db0a81569\n" }, { "commit": "eeefa1276e83776f08704a3db4237423b0627e20", "tree": "d7c647ca77703f3712f567704f40b00d59a125de", "parents": [ "02c0bac34c246c1bd974dbb86d292d4b52ba98e4" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 18:52:59 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Mar 16 10:48:21 2015 +0000" }, "message": "Update locations of registers after slow paths spilling.\n\nChange-Id: Id9aafcc13c1a085c17ce65d704c67b73f9de695d\n" }, { "commit": "dc23d8318db08cb42e20f1d16dbc416798951a8b", "tree": "e7a883bb3263ccb971898df98bc58700604c1d1d", "parents": [ "e5f5953e744060fde3b4489cea4d934d529e3e32" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Feb 16 11:15:43 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Feb 18 09:53:32 2015 +0000" }, "message": "Avoid generating jmp +0.\n\nWhen a block branches to a non-following block, but blocks\nin-between do branch to it, we can avoid doing the branch.\n\nChange-Id: I9b343f662a4efc718cd4b58168f93162a24e1219\n" }, { "commit": "2bcf9bf784a0021630d8fe63d7230d46d6891780", "tree": "167d773b796c5e63d84c205a8ae9a2fe3585d06a", "parents": [ "61fdf5bca503c30ba1e4dcaf333a8d3299f3bde6" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jan 29 09:56:07 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Feb 09 13:08:39 2015 -0800" }, "message": "ART: Arm intrinsics for Optimizing compiler\n\nAdd arm32 intrinsics to the optimizing compiler.\n\nChange-Id: If4aeedbf560862074d8ee08ca4484b666d6b9bf0\n" }, { "commit": "1cf95287364948689f6a1a320567acd7728e94a3", "tree": "70a8b60c768894d635cf63b0a480baa5073d2bed", "parents": [ "4a50662eeaa0b1a26be66e7584fb765151dabc59" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Dec 12 19:22:03 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 29 10:52:14 2015 +0000" }, "message": "Small optimization for recursive calls: avoid dex cache.\n\nChange-Id: I044757a2f06e535cdc1480c4fc8182b89635baf6\n" }, { "commit": "4dee636d21d9ce54386cdfbb824e5eb2a9c1af0d", "tree": "ee8650cc14ec18ce0d7abf089c7d2e0dfc9e079d", "parents": [ "336247fa6deba2948f5ede1df806f48cf67c790a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 23 18:23:14 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sat Jan 24 14:34:01 2015 +0000" }, "message": "Support callee-save registers on ARM.\n\nChange-Id: I7c519b7a828c9891b1141a8e51e12d6a8bc84118\n" }, { "commit": "d97dc40d186aec46bfd318b6a2026a98241d7e9c", "tree": "5cf0257eda25e2722a1adafb9de22690c06a56d8", "parents": [ "c698b78a17043d8898deb817098181595fbe734e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 22 13:50:01 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 23 09:20:42 2015 +0000" }, "message": "Support callee save floating point registers on x64.\n\n- Share the computation of core_spill_mask and fpu_spill_mask\n between backends.\n- Remove explicit stack overflow check support: we need to adjust\n them and since they are not tested, they will easily bitrot.\n\nChange-Id: I0b619b8de4e1bdb169ea1ae7c6ede8df0d65837a\n" }, { "commit": "988939683c26c0b1c8808fc206add6337319509a", "tree": "876e94428276547a29c27ccf17509a42dfe7cda1", "parents": [ "59add47cabce3735ccd470cd3b5dac8b112e09ab" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 12:32:32 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 18:50:25 2015 +0000" }, "message": "Enable core callee-save on x64.\n\nWill work on other architectures and FP support in other CLs.\n\nChange-Id: I8cef0343eedc7202d206f5217fdf0349035f0e4d\n" }, { "commit": "77520bca97ec44e3758510cebd0f20e3bb4584ea", "tree": "2e3be6fdc182e5cf5ae390019457af5e9c1ed242", "parents": [ "4d2c611bf17ff309abfa152e56c0b98a21ec8787" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Jan 12 18:45:46 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Jan 21 14:26:35 2015 +0000" }, "message": "Record implicit null checks at the actual invoke time.\n\nImplicitNullChecks are recorded only for instructions directly (see NB\nbelow) preceeded by NullChecks in the graph. This way we avoid recording\nredundant safepoints and minimize the code size increase.\n\nNB: ParallalelMoves might be inserted by the register allocator between\nthe NullChecks and their uses. These modify the environment and the\ncorrect action would be to reverse their modification. This will be\naddressed in a follow-up CL.\n\nChange-Id: Ie50006e5a4bd22932dcf11348f5a655d253cd898\n" }, { "commit": "cd6dffedf1bd8e6dfb3fb0c933551f9a90f7de3f", "tree": "0d83e9fdf65bded684d6e836078f253e63b7e11f", "parents": [ "12c03ac7575db242a6f35739bb459e8277115da4" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Jan 08 17:35:35 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Jan 16 17:27:03 2015 +0000" }, "message": "Add implicit null checks for the optimizing compiler\n\n- for backends: arm, arm64, x86, x86_64\n- fixed parameter passing for CodeGenerator\n- 003-omnibus-opcodes test verifies that NullPointerExceptions work as\nexpected\n\nChange-Id: I1b302acd353342504716c9169a80706cf3aba2c8\n" }, { "commit": "c507c7f8f905f77b039e58441b2e7da20fa65342", "tree": "98411281496e2af2f3b001881bec8f11782131cd", "parents": [ "f80dfb498451dc59e8f3375e6cf617055d3e76d1", "f85a9ca9859ad843dc03d3a2b600afbaf2e9bbdd" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 15 16:58:14 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jan 15 16:58:14 2015 +0000" }, "message": "Merge \"[optimizing compiler] Compute live spill size\"" }, { "commit": "f85a9ca9859ad843dc03d3a2b600afbaf2e9bbdd", "tree": "a802042fa7a3a8cb820916d558e630596daaa9b4", "parents": [ "8fccea249b1a6f1469eeea42c2b2cca06ce1c70d" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Jan 13 09:20:58 2015 -0500" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Jan 15 11:21:37 2015 -0500" }, "message": "[optimizing compiler] Compute live spill size\n\nThe current stack frame calculation assumes that each live register to\nbe saved/restored has the word size of the machine. This fails for X86,\nwhere a double in an XMM register takes up 8 bytes. Change the\ncalculation to keep track of the number of core registers and number of\nfp registers to handle this distinction.\n\nThis is slightly pessimal, as the registers may not be active at the\nsame time, but the only way to handle this would be to allocate both\nclasses of registers simultaneously, or remember all the active\nintervals, matching them up and compute the size of each safepoint\ninterval.\n\nChange-Id: If7860aa319b625c214775347728cdf49a56946eb\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "69c15d340e7e76821bbc5d4494d4cef383774dee", "tree": "afea69c321ffa55e0af63a83be62eedd2b378d2f", "parents": [ "603104b5b5c3759b0bc2733bda2f972686a775a3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jan 13 11:42:13 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jan 13 18:11:24 2015 +0000" }, "message": "Skip r1 on arm if first parameter is a long.\n\nChange-Id: I16d927ee0a0b55031ade4c92c0095fd74e18ed5b\n" }, { "commit": "840e5461a85f8908f51e7f6cd562a9129ff0e7ce", "tree": "ea8b4cbc5a0e3dea96fefcd9247e6c06b17ac518", "parents": [ "893e8881e31180721512c1b9e5ffacb03aad2e45" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 07 16:01:24 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 08 13:57:51 2015 +0000" }, "message": "Implement double and float support for arm in register allocator.\n\nThe basic approach is:\n- An instruction that needs two registers gets two intervals.\n- When allocating the low part, we also allocate the high part.\n- When splitting a low (or high) interval, we also split the high\n (or low) equivalent.\n- Allocation follows the (S/D register) requirement that low\n registers are always even and the high equivalent is low + 1.\n\nChange-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797\n" }, { "commit": "3416601a9e9be81bb7494864287fd3602d18ef13", "tree": "dd228519bfb9733aa7627b9cea81ecb28974a1ab", "parents": [ "8558375377946aabbbda6ab584e13f754590bd89" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Dec 19 17:22:29 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Jan 05 16:25:59 2015 +0000" }, "message": "Look at instruction set features when generating volatiles code\n\nChange-Id: Ia882405719fdd60b63e4102af7e085f7cbe0bb2a\n" }, { "commit": "52c489645b6e9ae33623f1ec24143cde5444906e", "tree": "a39667aa354645bd42a7a061d08ca82df3004143", "parents": [ "193c7a94822f765b0b6b0cecd54c9f08dfd26425" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Dec 16 17:02:57 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Dec 19 09:58:27 2014 +0000" }, "message": "[optimizing compiler] Add support for volatile\n\n- for backends: arm, x86, x86_64\n- added necessary instructions to assemblies\n- clean up code gen for field set/get\n- fixed InstructionDataEquals for some instructions\n- fixed comments in compiler_enums\n\n* 003-opcode test verifies basic volatile functionality\n\nChange-Id: I144393efa312dfb2c332cb84056b00edffee338a\n" }, { "commit": "9aec02fc5df5518c16f1e5a9b6cb198a192db973", "tree": "fe924b37f395af1bb50f55ee6c87c66b727f00af", "parents": [ "20032e512c003a8f42735c4e1eca19c1472bb95e" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Nov 18 23:06:35 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Nov 24 16:06:55 2014 +0000" }, "message": "[optimizing compiler] Add shifts\n\nAdded SHL, SHR, USHR for arm, x86, x86_64.\n\nChange-Id: I971f594e270179457e6958acf1401ff7630df07e\n" }, { "commit": "86a8d7afc7f00ff0f5ea7b8aaf4d50514250a4e6", "tree": "3db61320369973e463f67927a8983d7eb0d9f860", "parents": [ "255a5bde2f0014dc86a564555106a4291c0867b4" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 19 08:47:18 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 19 08:47:18 2014 +0000" }, "message": "Consistently use k{InstructionSet}WordSize.\n\nThese constants were defined prior to k{InstructionSet}PointerSize. So\nuse them consistently in optimizing as a first step. We can discuss\nwhether we should remove them in a second step.\n\nChange-Id: If129de1a3bb8b65f8d9c816a8ad466815fb202e6\n" }, { "commit": "a3279c80b4f92e0cc96902cf069c09424ed94ed0", "tree": "2d566e00a4976fe72c54663192715f919d3fa1dd", "parents": [ "a1af1b59256820dde25ec21581e9e64f698e182f", "f0e3937b87453234d0d7970b8712082062709b8d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Nov 13 09:58:56 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Nov 13 09:58:57 2014 +0000" }, "message": "Merge \"Do a parallel move in BoundsCheckSlowPath.\"" }, { "commit": "f0e3937b87453234d0d7970b8712082062709b8d", "tree": "e552c1173ee90fea1d2ba11cc08878efe65ba0be", "parents": [ "59321e0e10ea09694efecf6154704e2743b9bffd" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 12 17:50:07 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 12 17:55:24 2014 +0000" }, "message": "Do a parallel move in BoundsCheckSlowPath.\n\nThe two locations of the index and length could overlap,\nso we need a parallel move. Also factorize the code for\ndoing a parallel move based on two locations.\n\nChange-Id: Iee8b3459e2eed6704d45e9a564fb2cd050741ea4\n" }, { "commit": "9574c4b5f5ef039d694ac12c97e25ca02eca83c0", "tree": "2ad3cb7ffaf3579b9ca2a7bb0d7d7e99b3c758b6", "parents": [ "59321e0e10ea09694efecf6154704e2743b9bffd" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 12 13:19:37 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 12 13:55:36 2014 +0000" }, "message": "Implement and/or/xor in optimizing.\n\nChange-Id: I7cf6da1fd334a7177a5580931b8f174dd40b7cec\n" }, { "commit": "de58ab2c03ff8112b07ab827c8fa38f670dfc656", "tree": "c872bfbcad1e90845008140bbddcc43e56dc19d2", "parents": [ "3ed86e4e98dfe1b05c9a03aa2aee42c145a018c3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 05 12:46:03 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Nov 06 16:49:52 2014 +0000" }, "message": "Implement try/catch/throw in optimizing.\n\n- We currently don\u0027t run optimizations in the presence of a try/catch.\n- We therefore implement Quick\u0027s mapping table.\n- Also fix a missing null check on array-length.\n\nChange-Id: I6917dfcb868e75c1cf6eff32b7cbb60b6cfbd68f\n" }, { "commit": "424f676379f2f872acd1478672022f19f3240fc1", "tree": "bdd8fbb9c2401465d9a0536e94dec74acc8b4f3b", "parents": [ "793d1023785f81eb8e29a3eb67fec17d7ee7dcbe" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Nov 03 14:51:25 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Nov 04 11:23:08 2014 +0000" }, "message": "Implement CONST_CLASS in optimizing compiler.\n\nChange-Id: Ia8c8dfbef87cb2f7893bfb6e178466154eec9efd\n" }, { "commit": "19a19cffd197a28ae4c9c3e59eff6352fd392241", "tree": "265b971afd0e33afc8986317aea2f5a6fe817aec", "parents": [ "7c049c1f34220b0dc1a7f68f3b30f388bae7bdb9" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Oct 22 16:07:05 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Oct 29 13:01:48 2014 +0000" }, "message": "Add support for static fields in optimizing compiler.\n\nChange-Id: Id2f010589e2bd6faf42c05bb33abf6816ebe9fa9\n" }, { "commit": "1ba0f596e9e4ddd778ab431237d11baa85594eba", "tree": "c1d51616adf4d98aab3ebccf47ad5146635cb87f", "parents": [ "1ef3495abfa2a858b3cc7a1844383c8e7dff0b60" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Oct 27 15:14:55 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Oct 27 17:20:35 2014 +0000" }, "message": "Support hard float on arm in optimizing compiler.\n\nAlso bump oat version, needed after latest hard float switch.\n\nChange-Id: Idf5acfb36c07e74acff00edab998419a3c6b2965\n" }, { "commit": "102cbed1e52b7c5f09458b44903fe97bb3e14d5f", "tree": "cb0a433c8f284021298c8a0c4dd0da97ca9d198a", "parents": [ "07f5c5edb7ef24ac35364e6ef9a8107a44e6564e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Oct 15 18:31:05 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 21 16:03:51 2014 +0100" }, "message": "Implement register allocator for floating point registers.\n\nAlso:\n- Fix misuses of emitting the rex prefix in the x86_64 assembler.\n- Fix movaps code generation in the x86_64 assembler.\n\nChange-Id: Ib6dcf6e7c4a9c43368cfc46b02ba50f69ae69cbe\n" }, { "commit": "34bacdf7eb46c0ffbf24ba7aa14a904bc9176fb2", "tree": "e8ed8e40c5f7896a9ac01bf7dcc2e56f40cfc804", "parents": [ "7f758228f7904d2f65f06bfbd2b8ecbb8e8c6a9d" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Oct 07 20:23:36 2014 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Oct 17 11:46:45 2014 +0100" }, "message": "Add multiplication for integral types\n\nThis also fixes an issue where we could allocate a pair register even if\none of its parts was already blocked.\n\nChange-Id: I4869175933409add2a56f1ccfb369c3d3dd3cb01\n" }, { "commit": "92a73aef279be78e3c2b04db1713076183933436", "tree": "e73b214fb7d740588f5d065b2e4ff3eb8c527e34", "parents": [ "5c5efc253507eb43265997c9afcd778f72b6cef4" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 16 11:12:52 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 16 15:17:44 2014 +0100" }, "message": "Don\u0027t use assembler classes in code_generator.h.\n\nThe arm64 backend uses its own assembler and does not share\nthe same classes as the other backends. To avoid conflicts\nor unnecessary mappings, just don\u0027t use those classes in the\nshared part of the code generator.\n\nChange-Id: I9e5fa40c1021d2e83a4ef14c52cd1ccd03f2f73d\n" }, { "commit": "71175b7f19a4f6cf9cc264feafd820dbafa371fb", "tree": "5370e7c7c9f7d1edf148a00548cb1334d5118f8d", "parents": [ "b76c5495c4879fcfa0866b1490031a3123baf9ee" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 09 22:13:55 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Oct 10 11:36:03 2014 +0000" }, "message": "Cleanup baseline register allocator.\n\n- Use three arrays for blocking regsters instead of\n one and computing offsets in that array.]\n- Don\u0027t pass blocked_registers_ to methods, just use the field.\n\nChange-Id: Ib698564c31127c59b5a64c80f4262394b8394dc6\n" }, { "commit": "360231a056e796c36ffe62348507e904dc9efb9b", "tree": "a62ff73c11eaa6694649c98e4c2d872e89149b0c", "parents": [ "2072c465cfff077da257bdf14f1f1b2690c946c8" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Oct 08 21:07:48 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 09 15:21:57 2014 +0100" }, "message": "Fix code generation of materialized conditions.\n\nMove the logic for knowing if a condition needs to be materialized\nin an optimization pass (so that the information does not change\nas a side effect of another optimization).\n\nAlso clean-up arm and x86_64 codegen:\n- arm: ldr and str are for power-users when a constant is\n in play. We should use LoadFromOffset and StoreToOffset.\n- x86_64: fix misuses of movq instead of movl.\n\nChange-Id: I01a03b91803624be2281a344a13ad5efbf4f3ef3\n" }, { "commit": "56b9ee6fe1d6880c5fca0e7feb28b25a1ded2e2f", "tree": "34e5163967f59a98e64f2c89489ed7b76334b48a", "parents": [ "a3c4d72210de174552f47b2d117b1946f274af1e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 09 11:47:51 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 09 14:42:13 2014 +0100" }, "message": "Stop converting from Location to ManagedRegister.\n\nNow the source of truth is the Location object that knows\nwhich register (core, pair, fpu) it needs to refer to.\n\nChange-Id: I62401343d7479ecfb24b5ed161ec7829cda5a0b1\n" }, { "commit": "7fb49da8ec62e8a10ed9419ade9f32c6b1174687", "tree": "8b1bec67452b84809cecd5645543e1f885ccbd44", "parents": [ "4a1b4679cda2f0d2893b8e3f910c21231849291c" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Oct 06 09:12:41 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 07 20:19:47 2014 +0100" }, "message": "Add support for floats and doubles.\n\n- Follows Quick conventions.\n- Currently only works with baseline register allocator.\n\nChange-Id: Ie4b8e298f4f5e1cd82364da83e4344d4fc3621a3\n" }, { "commit": "a72cb229d555a8ca86dca748733ea3791eaeec14", "tree": "b051a0f2d10c126a83d22ff45f2feecf0365aca3", "parents": [ "d7e2f329ddacd2294ba94cd5acde026677d32e0d", "3c04974a90b0e03f4b509010bff49f0b2a3da57f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Sep 25 13:37:06 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Sep 25 13:37:06 2014 +0000" }, "message": "Merge \"Optimize suspend checks in optimizing compiler.\"" }, { "commit": "5799fc0754da7ff2b50b472e05c65cd4ba32dda2", "tree": "38a4189bc2e667dfd0537b02b24a8563907898d4", "parents": [ "f2476d524281c6d649f5deb6d1ccccc92380c1ed" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Sep 25 12:15:20 2014 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Sep 25 13:06:17 2014 +0100" }, "message": "Optimizing compiler: remove unnecessary `explicit\u0027 keywords.\n\nChange-Id: I5927fd92d53308c81e14edbd6e7d1c943bfa085b\n" }, { "commit": "3c04974a90b0e03f4b509010bff49f0b2a3da57f", "tree": "52649104e3e80272c3774793350f4d9f260ae732", "parents": [ "c0d36abb12cdbb9469039c1dc153a586bd984015" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Sep 24 18:10:46 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Sep 25 12:23:40 2014 +0100" }, "message": "Optimize suspend checks in optimizing compiler.\n\n- Remove the ones added during graph build (they were added\n for the baseline code generator).\n- Emit them at loop back edges after phi moves, so that the test\n can directly jump to the loop header.\n- Fix x86 and x86_64 suspend check by using cmpw instead of cmpl.\n\nChange-Id: I6fad5795a55705d86c9e1cb85bf5d63dadfafa2a\n" }, { "commit": "3bca0df855f0e575c6ee020ed016999fc8f14122", "tree": "15e15c8290ad314c29ca608f51d89d4db68fd9ba", "parents": [ "d41491adb23764f28a80cbb7f2bd7af6491cd892" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Sep 19 11:01:00 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Sep 23 13:57:30 2014 +0100" }, "message": "Support for saving and restoring live registers in a slow path.\n\nAnd use it in suspend check slow paths.\n\nChange-Id: I79caf28f334c145a36180c79a6e2fceae3990c31\n" }, { "commit": "e982f0b8e809cece6f460fa2d8df25873aa69de4", "tree": "df729d47439f7243b498dd4503a5f7aa41a4818b", "parents": [ "f031724abf4f215e1627ff837f87cad5d7a25165" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Aug 13 02:11:24 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Sep 17 09:53:50 2014 +0100" }, "message": "Implement invoke virtual in optimizing compiler.\n\nAlso refactor 004 tests to make them work with both Quick and\nOptimizing.\n\nChange-Id: I87e275cb0ae0258fc3bb32b612140000b1d2adf8\n" }, { "commit": "8a16d97fb8f031822b206e65f9109a071da40563", "tree": "9dbbf5feaac15d2e4f54fbfc3c204fcdd6e8317a", "parents": [ "c7f6b86c269727fe031146b9c18652d40916d46f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Sep 11 10:30:02 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Sep 11 10:32:12 2014 +0100" }, "message": "Fix valgrind errors.\n\nFor now just stack allocate the code generator. Will think\nabout cleaning up the root problem later (CodeGenerator being an\narena object).\n\nChange-Id: I161a6f61c5f27ea88851b446f3c1e12ee9c594d7\n" }, { "commit": "3c7bb98698f77af10372cf31824d3bb115d9bf0f", "tree": "1cd4cc18babfbb16ab908f23929fa88d7678f06b", "parents": [ "98cc1e552c2ccbe5d51bc81d49e79119280f5416" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 23 16:04:16 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jul 28 15:44:28 2014 +0100" }, "message": "Implement array get and array put in optimizing.\n\nAlso fix a couple of assembler/disassembler issues.\n\nChange-Id: I705c8572988c1a9c4df3172b304678529636d5f6\n" }, { "commit": "96f89a290eb67d7bf4b1636798fa28df14309cc7", "tree": "ca2b484a18107f8253aa7774cde304586a31bc60", "parents": [ "4436e926aa8e64ac7e4c4afb81f2a59b2477045a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jul 11 10:57:49 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jul 21 09:54:20 2014 +0100" }, "message": "Add assembly operations with constants in optimizing compiler.\n\nChange-Id: I5bcc35ab50d4457186effef5592a75d7f4e5b65f\n" }, { "commit": "8d486731559ba0c5e12c27b4a507181333702b7e", "tree": "78d19970d33511d6a1c54560801d5c5dcc0c47af", "parents": [ "fbde4dd1cb6db729e3f3ee5bdae0cdd824d73054" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 16 16:23:40 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 16 17:55:38 2014 +0100" }, "message": "Use the thumb2 assembler for the optimizing compiler.\n\nChange-Id: I2b058f4433504dc3299c06f5cb0b5ab12f34aa82\n" }, { "commit": "ab032bc1ff57831106fdac6a91a136293609401f", "tree": "5891daefe635283443a255a811ab6a3f3b8a62cd", "parents": [ "635561b86ac03f5562bdb779baa6db12f31b3cae" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jul 15 12:55:21 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jul 15 12:58:29 2014 +0100" }, "message": "Fix a braino in the stack layout.\n\nAlso do some refactoring to have this code be just in CodeGenerator.\n\nChange-Id: I88de109889138af8d60027973c12a64bee813cb7\n" }, { "commit": "e50383288a75244255d3ecedcc79ffe9caf774cb", "tree": "8858489463a57c7b50f7db4d972abec21302b7a7", "parents": [ "cf90ba7ebe00346651f3b7ce1e5b1f785f7caabd" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jul 04 09:41:32 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jul 14 10:06:11 2014 +0100" }, "message": "Support fields in optimizing compiler.\n\n- Required support for temporaries, to be only used by baseline compiler.\n- Also fixed a few invalid assumptions around locations and instructions\n that don\u0027t need materialization. These instructions should not have an Out.\n\nChange-Id: Idc4a30dd95dd18015137300d36bec55fc024cf62\n" } ], "next": "412f10cfed002ab617c78f2621d68446ca4dd8bd" }