)]}'
{
  "log": [
    {
      "commit": "c8150b5def82058c23df377a5006a78e7668afeb",
      "tree": "8f0e15b91cd55b978ca7f152206f0a550353810a",
      "parents": [
        "b2028739a2db03623ed76f5028ede1333c48f4c9"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Wed Jul 31 18:28:00 2019 +0100"
      },
      "committer": {
        "name": "Treehugger Robot",
        "email": "treehugger-gerrit@google.com",
        "time": "Fri Apr 17 10:35:45 2020 +0000"
      },
      "message": "ART: Refactor SIMD slots and regs size processing.\n\nART vectorizer assumes that there is single size of SIMD\nregister used for the whole program. Make this assumption explicit\nand refactor the code.\n\nNote: This is a base for the future introduction of SIMD slots of\nsize other than 8 or 16 bytes.\n\nTest: test-art-target, test-art-host.\nChange-Id: Id699d5e3590ca8c655ecd9f9ed4e63f49e3c4f9c\n"
    },
    {
      "commit": "0a51605ddd81635135463dab08b6f7c21b58ffb0",
      "tree": "820f338333010f4d6e4b543ffea47e9ff7d2dd3f",
      "parents": [
        "e2727154f25e0db9a5bb92af494d8e47b181dfcf"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Oct 14 13:00:44 2019 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Oct 14 13:00:44 2019 +0000"
      },
      "message": "Revert \"Make compiler/optimizing/ symbols hidden.\"\n\nThis reverts commit e2727154f25e0db9a5bb92af494d8e47b181dfcf.\n\nReason for revert: Breaks ASAN tests (ODR violation).\nBug: 142365358\n\nChange-Id: I38103d74a1297256c81d90872b6902ff1e9ef7a4\n"
    },
    {
      "commit": "e2727154f25e0db9a5bb92af494d8e47b181dfcf",
      "tree": "0ddc6eec3ad9508d7eb1f2b941786dd0ed7d2cd8",
      "parents": [
        "c78860b91ae07eed92f86876e7a03132adea6fcd"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Oct 10 10:46:42 2019 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Oct 14 08:22:00 2019 +0000"
      },
      "message": "Make compiler/optimizing/ symbols hidden.\n\nMake symbols in compiler/optimizing hidden by a namespace\nattribute. The unit intrinsic_objects.{h,cc} is excluded as\nit is needed by dex2oat.\n\nAs the symbols are no longer exported, gtests are now linked\nwith the static version of the libartd-compiler library.\n\nlibart-compiler.so size:\n  - before:\n    arm: 2396152\n    arm64: 3345280\n  - after:\n    arm: 2016176 (-371KiB, -15.9%)\n    arm64: 2874480 (-460KiB, -14.1%)\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nBug: 142365358\nChange-Id: I1fb04a33351f53f00b389a1642e81a68e40912a8\n"
    },
    {
      "commit": "6a0b657a1875b4fbb020b806169e2f73fcb2578b",
      "tree": "955bb0e3413e18f2b13b7fee7fa3e6e48a214597",
      "parents": [
        "61f071630083775fe64d177455a056daa7071eca"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Fri Jul 26 20:38:37 2019 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Aug 02 13:31:43 2019 +0000"
      },
      "message": "ART: ARM64: Optimize frame size for SIMD graphs.\n\nFor SIMD graphs allocate 64 bit instead of 128 bit on stack for\neach FP register to be preserved by the callee in the frame entry\nas ABI suggests (currently 64-bit registers are preserved but\nmore space on stack is allocated).\n\nNote: slow paths still require spilling full 128-bit Q-Registers\nfor SIMD graphs due to register allocator restrictions.\n\nTest: test-art-target.\nChange-Id: Ie0b12e4b769158445f3d0f4562c70d4fb0ea7744\n"
    },
    {
      "commit": "3db70689e3e1c92344d436a8ea4265046bdef449",
      "tree": "3db08743e968062ed5bdc143233cdb3c4564696b",
      "parents": [
        "1650dafad62578a1766bd617d78458a4cf1e2a9a"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Wed Dec 26 15:12:03 2018 -0800"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Thu Dec 27 12:56:39 2018 -0800"
      },
      "message": "ART: Refactor for bugprone-argument-comment\n\nHandles compiler.\n\nBug: 116054210\nTest: WITH_TIDY\u003d1 mmma art\nChange-Id: I5cdfe73c31ac39144838a2736146b71de037425e\n"
    },
    {
      "commit": "66c158ef6b2a16257f1590b3ace78848a7c2407b",
      "tree": "f17f7eee70aa43711c7eb764c1789f4ec17aef37",
      "parents": [
        "92d0c8b68c24a2fa21f95d63a1ff2fb00fdb9aaf"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Jan 31 12:55:04 2018 -0800"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Feb 01 13:26:03 2018 -0800"
      },
      "message": "Clean up signed/unsigned in vectorizer.\n\nRationale:\nCurrently we have some remaining ugliness around signed and unsigned\nSIMD operations due to lack of kUint32 and kUint64 in the HIR. By\n\"softly\" introducing these types, ABS/MIN/MAX/HALVING_ADD/SAD_ACCUMULATE\noperations can solely rely on the packed data types to distinguish\nbetween signed and unsigned operations. Cleaner, and also allows for\nsome code removal in the current loop optimizer.\n\nBug: 72709770\n\nTest: test-art-host test-art-target\nChange-Id: I68e4cdfba325f622a7256adbe649735569cab2a3\n"
    },
    {
      "commit": "174b2e27ebf933b80f4e8b64b4b024ab4306aaac",
      "tree": "968cdd8d7fd68571115db77cc288807c3b257911",
      "parents": [
        "6783118d2ad9d759f0617b1219a9e29a10a569f7"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Oct 12 13:34:49 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Oct 17 11:12:08 2017 +0100"
      },
      "message": "Use ScopedArenaAllocator for code generation.\n\nReuse the memory previously allocated on the ArenaStack by\noptimization passes.\n\nThis CL handles only the architecture-independent codegen\nand slow paths, architecture-dependent codegen allocations\nshall be moved to the ScopedArenaAllocator in a follow-up.\n\nMemory needed to compile the two most expensive methods for\naosp_angler-userdebug boot image:\n  BatteryStats.dumpCheckinLocked() : 19.6MiB -\u003e 18.5MiB (-1189KiB)\n  BatteryStats.dumpLocked(): 39.3MiB -\u003e 37.0MiB (-2379KiB)\n\nAlso move definitions of functions that use bit_vector-inl.h\nfrom bit_vector.h also to bit_vector-inl.h .\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nBug: 64312607\nChange-Id: I84688c3a5a95bf90f56bd3a150bc31fedc95f29c\n"
    },
    {
      "commit": "e764d2e50c544c2cb98ee61a15d613161ac6bd17",
      "tree": "112aa7ca459d2edb4f800897060a2407fcc622c7",
      "parents": [
        "ca6fff898afcb62491458ae8bcd428bfb3043da1"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Oct 05 14:35:55 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Oct 09 10:39:22 2017 +0100"
      },
      "message": "Use ScopedArenaAllocator for register allocation.\n\nMemory needed to compile the two most expensive methods for\naosp_angler-userdebug boot image:\n  BatteryStats.dumpCheckinLocked() : 25.1MiB -\u003e 21.1MiB\n  BatteryStats.dumpLocked(): 49.6MiB -\u003e 42.0MiB\nThis is because all the memory previously used by Scheduler\nis reused by the register allocator; the register allocator\nhas a higher peak usage of the ArenaStack.\n\nAnd continue the \"arena\"-\u003e\"allocator\" renaming.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nBug: 64312607\nChange-Id: Idfd79a9901552b5147ec0bf591cb38120de86b01\n"
    },
    {
      "commit": "d5d2f2ce627aa0f6920d7ae05197abd1a396e035",
      "tree": "e8e780780c832e3614a22438a23fb60ee4960ca3",
      "parents": [
        "efac0df8c738764823c637deeca1f3be33912064"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Sep 26 12:37:26 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Oct 03 10:40:51 2017 +0100"
      },
      "message": "ART: Introduce Uint8 compiler data type.\n\nThis CL adds all the necessary codegen for the Uint8 type\nbut does not add code transformations that use that code.\nVectorization codegens are modified to use Uint8 as the\npacked type when appropriate. The side effects are now\ndisconnected from the instruction\u0027s type after the graph has\nbeen built to allow changing HArrayGet/H*FieldGet/HVecLoad\nto use a type different from the underlying field or array.\n\nNote: HArrayGet for String.charAt() is modified to have\nno side effects whatsoever; Strings are immutable.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: testrunner.py --target --optimizing on Nexus 6P\nTest: Nexus 6P boots.\nBug: 23964345\nChange-Id: If2dfffedcfb1f50db24570a1e9bd517b3f17bfd0\n"
    },
    {
      "commit": "0ebe0d83138bba1996e9c8007969b5381d972b32",
      "tree": "a5ee66ebc5b587ade97e56ac8fc7d832fbbed4af",
      "parents": [
        "e1e347dace0ded83774999bb26c37527dcdb1d5a"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Sep 21 22:50:39 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Sep 25 15:45:01 2017 +0100"
      },
      "message": "ART: Introduce compiler data type.\n\nReplace most uses of the runtime\u0027s Primitive in compiler\nwith a new class DataType. This prepares for introducing\nnew types, such as Uint8, that the runtime does not need\nto know about.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nBug: 23964345\nChange-Id: Iec2ad82454eec678fffcd8279a9746b90feb9b0c\n"
    },
    {
      "commit": "82b0740f03b1a6acab4558214d3edc362e27e238",
      "tree": "c19ec7ad047fbbef0c0f4dcd46905604b75841b5",
      "parents": [
        "8144b1ebea42feaa798419eaf53a6bbbf37822a9"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Mar 01 19:02:04 2017 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Jun 01 20:37:10 2017 +0100"
      },
      "message": "Use IntrusiveForwardList\u003c\u003e for Env-/UsePosition.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nChange-Id: I2b720e2ed8f96303cf80e9daa6d5278bf0c3da2f\n"
    },
    {
      "commit": "5576f3741c58cb8b5fb2f68f3b3a9415efe05f4f",
      "tree": "2187c109d24ae3634416b551e83fef310e975a74",
      "parents": [
        "6efac9929f8952e4871e8c423c923989fc6f2ad2"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Mar 23 16:17:37 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Mar 23 16:51:52 2017 -0700"
      },
      "message": "Implement a SIMD spilling slot.\n\nRationale:\nThe last ART vectorizer break-out CL    \\O/\nThis ensures spilling on x86 and x86_4 is correct.\nAlso, it paves the way to wider SIMD on ARM and MIPS.\n\nTest: test-art-host\nBug: 34083438\n\nChange-Id: I5b27d18c2045f3ab70b64c335423b3ff2a507ac2\n"
    },
    {
      "commit": "cc89525c13894247cb82a1973617da6cba286f0c",
      "tree": "dc67bee8e66f9b34f979fae67624336a0ece3753",
      "parents": [
        "2b864659d4399de6c17e93b8df8cdbf08c6a7ac9"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Mar 21 10:55:15 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Mar 22 23:41:21 2017 +0000"
      },
      "message": "Change 1/2 spill slots to more general number of spill slots.\n\nRationale:\nThis prepares requesting a different number of spill slots\nduring SIMD vectorization.\n\nBug: 34083438\nTest: test-art-host, test-art-host-gtest-register_allocator_test\nChange-Id: I6d22966ba483deec72b5eea5061c403c12b2ada7\n"
    },
    {
      "commit": "356bd28feeedeb24e1f458492fdc5ecaef39c1eb",
      "tree": "e68b917d6c7ae3347baa74dea279a8681b0626a7",
      "parents": [
        "d1d4530ffa97729aa8944932a7ac2009ae51c7e3"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Mar 01 12:01:11 2017 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Mar 13 18:05:45 2017 +0000"
      },
      "message": "Introduce EnvUsePosition for liveness analysis.\n\nNormal and environment use positions are held in separate\nlists and the code never mixes them together. By using two\nseparate classes, we can reduce complexity and avoid an\nunnecesary data member, reducing the memory usage.\n\nTracking allocations for a certain big app, the peak arena\nmemory usage is\n  before:\n    MEM: used: 79245960, ...\n    SsaLiveness    31221600\n  after:\n    MEM: used: 78754024, ...\n    SsaLiveness    30729664\n\nTest: testrunner.py --host\nBug: 34053922\nChange-Id: I02d3c9f564bbe3b1da0e03c33cf7c0f810f235dc\n"
    },
    {
      "commit": "063fc772b5b8aed7d769cd7cccb6ddc7619326ee",
      "tree": "bc165781989087a998721991504e589a7d5b0926",
      "parents": [
        "48d08a4233ee4450b0d5073d41445f9dd1f17191"
      ],
      "author": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Tue Aug 02 11:02:54 2016 -0700"
      },
      "committer": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Thu Dec 01 11:15:47 2016 -0800"
      },
      "message": "Class Hierarchy Analysis (CHA)\n\nThe class linker now tracks whether a method has a single implementation\nand if so, the JIT compiler will try to devirtualize a virtual call for\nthe method into a direct call. If the single-implementation assumption\nis violated due to additional class linking, compiled code that makes the\nassumption is invalidated. Deoptimization is triggered for compiled code\nlive on stack. Instead of patching return pc\u0027s on stack, a CHA guard is\nadded which checks a hidden should_deoptimize flag for deoptimization.\nThis approach limits the number of deoptimization points.\n\nThis CL does not devirtualize abstract/interface method invocation.\n\nSlides on CHA:\nhttps://docs.google.com/a/google.com/presentation/d/1Ax6cabP1vM44aLOaJU3B26n5fTE9w5YU-1CRevIDsBc/edit?usp\u003dsharing\n\nChange-Id: I18bf716a601b6413b46312e925a6ad9e4008efa4\nTest: ART_TEST_JIT\u003dtrue m test-art-host/target-run-test test-art-host-gtest\n"
    },
    {
      "commit": "19c5419d21376dd69404736b998fbbb9da54af56",
      "tree": "1e15b39f7c6662b2939bbaa7f34560fcea72e7b4",
      "parents": [
        "c46e708aa0bd7a007f0de8db1cad8ef49166ca10"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Fri Nov 04 13:44:09 2016 +0000"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Fri Nov 04 16:43:41 2016 +0000"
      },
      "message": "Revert \"Revert \"Enable IntermediateAddress for primitive arrays with read barriers.\"\"\n\nThis reverts commit 4a3aa578eff94eb10450fae1772deb7cb8ddc6a6.\n\nThe failing assertion (see b/30762467):\n\n08-09 11:32:46.767  1654  1656 F dex2oatd: art/compiler/optimizing/register_allocation_resolver.cc:325] Check failed: interval-\u003eGetDefinedBy()-\u003eIsActualObject() IntermediateAddress@InstanceFieldGet\n\nthat motivated the initial revert has been removed by a\nprevious CL (commit\n70e97462116a47ef2e582ea29a037847debcc029,\nhttps://android-review.googlesource.com/#/c/254920/).\n\nTest: ART host and target (ARM, ARM64) tests with `ART_USE_READ_BARRIER\u003dtrue`.\nBug: 26601270\nBug: 12687968\nChange-Id: I09cae0c6c38ca403924153e9f0eb0cc3ff4540e7\n"
    },
    {
      "commit": "9620230700d4b451097c2163faa70627c9d8088a",
      "tree": "695b96b9efeaa4c2cb3816e51904e19540fe3883",
      "parents": [
        "4aa6a93c46a959df1ab71ee7a68ad345338046ef"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Oct 04 17:33:56 2016 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Oct 05 11:50:42 2016 -0700"
      },
      "message": "Refactoring of graph linearization and linear order.\n\nRationale:\nOwnership of graph\u0027s linear order and iterators was\na bit unclear now that other phases are using it.\nNew approach allows phases to compute their own\norder, while ssa_liveness is sole owner for graph\n(since it is not mutated afterwards).\n\nAlso shortens lifetime of loop\u0027s arena.\n\nTest: test-art-host\nChange-Id: Ib7137d1203a1e0a12db49868f4117d48a4277f30\n"
    },
    {
      "commit": "70e97462116a47ef2e582ea29a037847debcc029",
      "tree": "ee587e35b9b9483c35875ccc8ddea139978ca823",
      "parents": [
        "521691ae4dfad47cf6b46858347fa5fa32fd7bcc"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Aug 09 11:04:26 2016 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Sep 05 17:27:41 2016 +0100"
      },
      "message": "Avoid excessive spill slots for slow paths.\n\nReducing the frame size makes stack maps smaller as we need\nfewer bits for stack masks and some dex register locations\nmay use short location kind rather than long. On Nexus 9,\nAOSP ToT, the boot.oat size reduction is\n  prebuilt multi-part boot image:\n    - 32-bit boot.oat: -416KiB (-0.6%)\n    - 64-bit boot.oat: -635KiB (-0.9%)\n  prebuilt multi-part boot image with read barrier:\n    - 32-bit boot.oat: -483KiB (-0.7%)\n    - 64-bit boot.oat: -703KiB (-0.9%)\n  on-device built single boot image:\n    - 32-bit boot.oat: -380KiB (-0.6%)\n    - 64-bit boot.oat: -632KiB (-0.9%)\n  on-device built single boot image with read barrier:\n    - 32-bit boot.oat: -448KiB (-0.6%)\n    - 64-bit boot.oat: -692KiB (-0.9%)\n\nThe other benefit is that at runtime, threads may need fewer\npages for their stacks, reducing overall memory usage.\n\nWe defer the calculation of the maximum spill size from\nthe main register allocator (linear scan or graph coloring)\nto the RegisterAllocationResolver and do it based on the\nlive registers at slow path safepoints. The old notion of\nan artificial slow path safepoint interval is removed as\nit is no longer needed.\n\nTest: Run ART test suite on host and Nexus 9.\nBug: 30212852\nChange-Id: I40b3d114e278e2c5807982904fa49bf6642c6275\n"
    },
    {
      "commit": "0b110f499171aa562fc77834b4357c23eacacad4",
      "tree": "681d7120babd7e668316918bd87a82810a96f984",
      "parents": [
        "360b4b0137ce5f0bb771e2ddbfd4735cae932565"
      ],
      "author": {
        "name": "Matthew Gharrity",
        "email": "gharrma@google.com",
        "time": "Wed Jul 20 10:13:45 2016 -0700"
      },
      "committer": {
        "name": "Matthew Gharrity",
        "email": "gharrma@google.com",
        "time": "Wed Jul 20 10:13:45 2016 -0700"
      },
      "message": "Fix accidental pass-by-value\n\nChange-Id: I245111eabb43368875c1215ca4f3a1f1918492fe\n"
    },
    {
      "commit": "5d6e27d136756216c945d3fc5eb2ecc1537bfe7a",
      "tree": "6c558348ad01c748894902ac9b0adc6cc032384f",
      "parents": [
        "bae13af2fc2fa89985d0466cedf155cb96767910"
      ],
      "author": {
        "name": "Matthew Gharrity",
        "email": "gharrma@google.com",
        "time": "Mon Jul 18 13:38:44 2016 -0700"
      },
      "committer": {
        "name": "Matthew Gharrity",
        "email": "gharrma@google.com",
        "time": "Tue Jul 19 14:18:30 2016 -0700"
      },
      "message": "Refactor SSA deconstruction into its own class\n\nTest: m test-art-host\n\nChange-Id: Ie82c2802f76f27512ef922ba583caeccf5675063\n"
    }
  ]
}