)]}'
{
  "log": [
    {
      "commit": "c6f3bb87ffbb44d902c4a1f67a71bb108bd01560",
      "tree": "c423db1d6e7914e57559ab5a4325094e6f1ea5c0",
      "parents": [
        "e5b7894351ecc5ef99442eea0700c913178c95ce"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Wed Mar 21 20:40:33 2012 -0700"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Wed Mar 21 20:41:16 2012 -0700"
      },
      "message": "Further x86 progress and image creation.\n\nChange-Id: Idafadfc55228541536f25d2c92d40d9e0510b602\n"
    },
    {
      "commit": "16da88c70c4bdbd97b8482be8b42103a52f22d59",
      "tree": "905c1bfc68c7a301706a5cd2b7a3d7d9084a06b3",
      "parents": [
        "b41b33b5e5f08083e35f84818b4f44d26feb4a8b"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Tue Mar 20 10:38:17 2012 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Tue Mar 20 14:36:11 2012 -0700"
      },
      "message": "Custom codegen for small frameless methods.\n\nAdded a general mechanism that will allow pattern matching of\nsmall methods and (generally) frameless code generation.  Prevously,\nall frames were at least 16 bytes, not you can have zero-length\nframes (and thus some old asserts had to go).\n\nChange-Id: Ic786940a602e25b48cbc317ac601ac84cc307762\n"
    },
    {
      "commit": "b41b33b5e5f08083e35f84818b4f44d26feb4a8b",
      "tree": "a888c3c40bd6070acc459700ed5c79055c6984f4",
      "parents": [
        "49ac9bfa63aea6d331e4c9aa5011953777bf98ad"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Tue Mar 20 14:22:54 2012 -0700"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Tue Mar 20 14:24:39 2012 -0700"
      },
      "message": "Add 3rd argument register to X86.\n\nImplement more instructions.\n\nChange-Id: I3af7bbaf18eedc6537f1cfc2d57c4f6106fb5164\n"
    },
    {
      "commit": "a7c12688da57ea052e127776ad3043ca5079488d",
      "tree": "a34c72a35f260e0680a486e3b98e7965dfcdc687",
      "parents": [
        "b3ab25b58945f1bd22da1be2eb49dc3eb121011e"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Mon Mar 19 13:13:53 2012 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Mon Mar 19 13:17:53 2012 -0700"
      },
      "message": "Restore card marking, minor tuning\n\nRestore GC card marks that were mistakenly dropped during an\nearlier retructuring.  Add debugging to code to gather opcode\nfrequency statics.  Minor tuning for code size.\n\nChange-Id: I117f62c29e29250277166e7f005706e27998f77a\n"
    },
    {
      "commit": "ab2b55dfcf630fdf8d03b5f506386f114fa2874c",
      "tree": "288b6e463a5eb13d78bb0a1a511233ddf1259124",
      "parents": [
        "b2793375d42b5d90d9a0111581c4314abe11ca4c"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Sun Mar 18 00:06:11 2012 -0700"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Sun Mar 18 00:06:11 2012 -0700"
      },
      "message": "Refactor callRuntimeHelper\n\nChange-Id: I87c5f592a931c98c4b5b693b72216f4e71990162\n"
    },
    {
      "commit": "239c4e72b5a69754e1d6879be5ba1f85150655c1",
      "tree": "45404157d7a684a739d218dc5a9ee3c0a6cdab19",
      "parents": [
        "8ed14528fb70a9ba7cc5e471317d08dc629cbc23"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Fri Mar 16 08:42:29 2012 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sat Mar 17 16:52:32 2012 -0700"
      },
      "message": "Loop detection, improved reg allocation\n\nDetect loops and loop nesting depth, and use the latter to\nweight register uses (which are then used to determine which\nregisters to promote).\n\nAlso:\n\n   o Fixed typo that prevented squashing of useless fp reg copies\n\n   o Rescheduled array access checks to hide latency of limit load.\n\n   o Add basic-block optimization pass to remove duplicate range\n     checks.\n\n   o Fixed bug that prevented recognition of redundant null\n     checks following iput-wide and aput-wide.\n\nChange-Id: Icfbae39e89b1d14b8703ad6bbb0b29c0635fed1e\n"
    },
    {
      "commit": "6cbb2bd8ba9a52de7e50a5da1f4e98dd7a460f1b",
      "tree": "1ab9f2f8e6c056b799d389a38a6b9abd052459a7",
      "parents": [
        "0512f02dd6623c0870c11fbf3274d7462f732136"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Fri Mar 16 13:45:30 2012 -0700"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Fri Mar 16 13:45:30 2012 -0700"
      },
      "message": "X86 invocation tidy up.\n\nChange-Id: I5bbea741e6434f9172e4041e562a5b15e2f37f95\n"
    },
    {
      "commit": "f7d9ad39541dd09030e26d54d3b73a076f90cc74",
      "tree": "aa0a9bc7b422ecc31432471fedd1b5fb496866b1",
      "parents": [
        "f320b639eee1ec0e9d99e8d6c2a805892d016807"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Tue Mar 13 18:45:39 2012 -0700"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Wed Mar 14 23:25:39 2012 -0700"
      },
      "message": "Enable all JNI internal compiler tests on the host.\n\n(cherry picked from commit abda43c90f70963909128c1cc495190d60fd8372)\n\nChange-Id: I0a7fc96e84dacf34108551271760aae13d5ee010\n"
    },
    {
      "commit": "3d661949dba4a2f3311e6f74a3c42b5addf1f534",
      "tree": "d8fd2c903fe425bb65a92a7ee9f72a1e57cf5045",
      "parents": [
        "fb84494fc1888b92e938ece850990668073a276b"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Wed Mar 14 17:37:27 2012 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Wed Mar 14 17:53:18 2012 -0700"
      },
      "message": "Real fix for 064\n\nThe recent ssa cleanup CL surfaced a somewhat subtle bug in\nlive register tracking.  The code generation register utilities\nattempt to remember and reuse live Dalvik register values for future\nuse.  This remembering takes place in the storeValueXX() code.\nFor this to work, though, storeValue may only be called once during\nthe compilation of any single Dalvik instruction.\n\nHowever, the code generation routine for CONST_CLASS included a\nsomewhat complicated slow path with iternal branches and two\ngenerated \"storeValue\" locations.  This resulted in downstream\ncode expecting to find a live value in the wrong place.\n\nThis fix is to note this special case and do a \"clobber\" on the ssa name.\n\nThis CL also includes some sanity checking code that can detect\nmultiple calls to storeValue during one intruction compilation to\ntry to catch this situation in the future.\n\nChange-Id: I66a279140accd80cda83f66efe570c9702fb351b\n"
    },
    {
      "commit": "e196567b50a084b163937ea9605b51ee1e48adeb",
      "tree": "709964fc09a36132490d9a3a4805983ec80c57e3",
      "parents": [
        "13b835a45f3dccff1c6d024ad82a2044831c7c41"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sun Mar 11 18:39:19 2012 -0700"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Tue Mar 13 20:59:18 2012 -0700"
      },
      "message": "SSA rework and support compiler temps in the frame\n\nAdd ability for the compiler to allocate new frame temporaries\nthat play nicely with the register allocation mechanism.  To do this\nwe assign negative virtual register numbers and give them SSA names.\nAs part of this change, I did a general cleanup of the ssa naming.\nAn ssa name (or SReg) is in index into an array of (virtual reg, subscript)\npairs.  Previously, 16 bits were allocated for the reg and the subscript.\nThis CL expands the virtual reg and subscript to 32 bits each.\n\nMethod* is now treated as a RegLocation, and will be subject to\ntemp register tracking and reuse.  This CL does not yet include\nsupport for promotion of Method* - that will show up in the next one.\n\nAlso included is the beginning of a basic block optimization pass (not\nyet in a runable state, so conditionally compiled out).\n\n(cherry picked from commit f689ffec8827f1dd6b31084f8a6bb240338c7acf)\n\nChange-Id: Ibbdeb97fe05d0e33c1f4a9a6ccbdef1cac7646fc\n"
    },
    {
      "commit": "b5d09b2f87202bc132ac3991d4b6d71f4f6d9264",
      "tree": "e9d805a956b42fd9958163a1f5feef68e8c7d97b",
      "parents": [
        "79ab9e32c6880e7b342c192a479c858c9dccf496"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Tue Mar 06 22:14:17 2012 -0800"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Mon Mar 12 16:01:37 2012 -0700"
      },
      "message": "Method prologue and epilogues, add missing x86 functionality.\n\nEnables compiling and running a number of JNI internal managed code\nmethods on the host.\n\nChange-Id: I56fceb813d0cb24637bc784ba57f2d1d16911d48\n"
    },
    {
      "commit": "680b1bdd7e5d112ba4b95d6c81a43b65119b3b9c",
      "tree": "21514b638db9b28cf26b4b452c3e5f9449568812",
      "parents": [
        "d8af8bd46c13347ca15558999db4da85dbc31818"
      ],
      "author": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Wed Mar 07 20:18:49 2012 -0800"
      },
      "committer": {
        "name": "Ian Rogers",
        "email": "irogers@google.com",
        "time": "Wed Mar 07 20:18:49 2012 -0800"
      },
      "message": "Unify branch flags, pretty printer for OpKind.\n\nLIR operand 0 is always an offset for a branch. This is clear in\nconditional branches that are binary and have the 2nd operand as the\ncondition codes of the branch. This changes unconditional branches to be\nunary and therefore more intention revealing that the 1st operand will\nbe used by the assembler to hold an offset.\n\nA \u003c\u003c operator for OpKind allows easy pretty printing.\n\nChange-Id: I933b8e0bf43f5be3eff13f93c3fc1539ae526840\n"
    },
    {
      "commit": "86a4bce32e2aaf3d377c0acf865f0630a7c30495",
      "tree": "98517211fdb1309f461e3fe3c41a34739ad121c1",
      "parents": [
        "6150d9889b56e95f1267d9200c5702b16e0d32d5"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Tue Mar 06 18:15:00 2012 -0800"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Wed Mar 07 12:10:21 2012 -0800"
      },
      "message": "Fix branch bug (showed up in codegen for debug)\n\nThere are a few \"safe\" optimizations in the compiler - removing\nregister copies where source and target are the same, deleting\nbranches to the next instruction, etc.  One of the redundant\nbranch optimizations, however, was incorrect and resulted in\na good branch being deleted.  This one showed up in the debug\nbuild, and resulted in a failure to do a suspend check (because\nthe branch to the suspend check was deleted).\n\nI had hoped that this but might also be the case of some\nother unexpected failures, but unfortunately I was only able\nto trigger it when doing a \"codegen for debug\" build.\n\nThe source of the bug was a confusion around 16 v/ 32-bit\nunconditional branch encodings.  For a 32-bit unconditional\nbranch, going to the next instruction means an displacement\nof zero.  However, for 16-bit branches, the next instruction\nis represented by a displacement of -1.\n\nTo help track down this sort of thing in the future, this CL\nalso adds a new optimization disable flag: kSafeOptimizations.\nThis will allow us to really turn off all optimizations for A/B\ntesting.\n\nAlso in this CL we are re-enabling the ability to promote argument\nregisters and improving somewhat the code sequence for suspend\ncheck when debug is enabled.\n\nChange-Id: Ib6b202746eac751cab3b4609805a389c18cb67b2\n"
    },
    {
      "commit": "adb8c67f6d87a160d4e3a8afea7cb93f6c14568b",
      "tree": "93b265743b7fd7a831803f6bc84e2aa8ce338156",
      "parents": [
        "731b2abfccd8704d129e3b8e46a086660161fef3"
      ],
      "author": {
        "name": "Elliott Hughes",
        "email": "enh@google.com",
        "time": "Tue Mar 06 16:49:32 2012 -0800"
      },
      "committer": {
        "name": "Elliott Hughes",
        "email": "enh@google.com",
        "time": "Tue Mar 06 17:21:07 2012 -0800"
      },
      "message": "Move the compiler away from libdex.\n\nChange-Id: I0c5fdc38d94f1199023cfc6aab3060b927ad2383\n"
    },
    {
      "commit": "a7678db092ac6bb79f7cad490099a1015fbbc714",
      "tree": "95181107e5ef16068298cbec717b605f54748ca4",
      "parents": [
        "e88dfbf138bc204b1ce21911f1c34098ea74af7c"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Mon Mar 05 15:35:46 2012 -0800"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Mon Mar 05 15:35:46 2012 -0800"
      },
      "message": "x86 source code hack and slash\n\nMade a pass over the compiler source to get it into a compileable\nstate for the x86 target.  Lots of temporary #ifdefs, but it\ncompiles and makes it to oatArchInit().\n\nChange-Id: Ib8bcd2a032e47dcb83430dbc479a29758e084359\n"
    },
    {
      "commit": "a2ebdd74eb2f36e6efa7a482bc11c7b93d97c2c3",
      "tree": "2d63c98a1f729f1e17969bfbc4b7dc1da48f4567",
      "parents": [
        "11f9d2130e938511efceb6d2a4793cee7dfdde35"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sun Mar 04 14:57:06 2012 -0800"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sun Mar 04 15:00:36 2012 -0800"
      },
      "message": "Complete MIPS code generation support\n\nWith this CL code generation for MIPS is complete (though untested on\nactual hardware).  Core and the boot classpath compile without issue.\n\nThe primary thrust here was to support expanding of short branch\nsequences to long form during assembly if the displacement field overflowed.\nThat led to a general cleanup of creation on LIR nodes outside of the\nnormal flow.\n\nAlso introduced is a README to describe the state of MIPS support, as well\nas memory barrier handling.\n\nChange-Id: I251a2ef8d74bc7183406dce9493464be24a9d7f7\n"
    },
    {
      "commit": "c5159d55ca8e9022b748176f9f53676e8e9d4cd2",
      "tree": "d407a682788fbbca4dbd0821350058a3c2901617",
      "parents": [
        "5b455485c1deda58959fdc410050e01448c032c2"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sat Mar 03 11:48:39 2012 -0800"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Sat Mar 03 16:32:24 2012 -0800"
      },
      "message": "MIPS switch table support\n\nAnd 64-bit neg/add/sub (ouch! Mips has no carry bit...)\n\nChange-Id: Ifb94324a0052d6069977fb8f22679b95890445d8\n"
    },
    {
      "commit": "0398c42cd64682d18120a26c6c39b193fdf97658",
      "tree": "f5a60c8bca5d4acd7b31d21239f3c74bf7c7d42c",
      "parents": [
        "82488f563e7f72f8c626052893c1792d76ab3faf"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Fri Mar 02 15:22:47 2012 -0800"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Fri Mar 02 15:22:47 2012 -0800"
      },
      "message": "More MIPS support\n\nWorking through the unimps.\n\nChange-Id: Ie088d2061ca9a77f42ebd75e2936159465deed10\n"
    },
    {
      "commit": "82488f563e7f72f8c626052893c1792d76ab3faf",
      "tree": "e17e3bc62adf8b57bfeb86a3a879dfb099d3d1d7",
      "parents": [
        "013b6f296ff7c0cb6aa5aeb6868df05995eeadb7"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Fri Mar 02 08:20:26 2012 -0800"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Fri Mar 02 13:02:52 2012 -0800"
      },
      "message": "Multi-target Codegen cleanup\n\nTrying to get a bit more consistent in the abstraction layer\nnaming:\n\n     genXXX   -\u003e high-level codegen, for ex: genIGet()\n     opXXX    -\u003e instruction-level output, for ex: opRegImm()\n\nAlso more fleshing out of the Mips codegen support.\n\nChange-Id: Iafdf397cbb5015bfe3aa2c38680d96c7c05f8bc4\n"
    },
    {
      "commit": "5de3494e4297c0d480409da3fecee39173f1d4e1",
      "tree": "269cd3447925d0b474d47fb056da4730f288ee12",
      "parents": [
        "6edfde4ae89f3a16d22ca82c928a5dd420e9fce9"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Thu Mar 01 14:51:57 2012 -0800"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Thu Mar 01 16:43:54 2012 -0800"
      },
      "message": "Another step towards a Mips target\n\nUpdating the MIPS target to use the now common codegen routines.\nStill much to do, but the general structure is sufficient to allow\nwork to begin on the other target.\n\nChange-Id: I0d288fdfb59c8e76fad73185fdd56b345e87b604\n"
    },
    {
      "commit": "31a4a6f5717f645da6b97ccc1e420ae1e1c71ce0",
      "tree": "de07c7175bcda6c2e3f11329d72d142319354f3f",
      "parents": [
        "32c9a2decebe7b736e1f05b53b5822affea5e81d"
      ],
      "author": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Tue Feb 28 15:36:15 2012 -0800"
      },
      "committer": {
        "name": "buzbee",
        "email": "buzbee@google.com",
        "time": "Wed Feb 29 18:52:47 2012 -0800"
      },
      "message": "More target-independence\n\nContinuing to move target-specific code from the Arm\ncode generator into the independent realm.  This will be\ndone in multiple small steps.\n\nIn this CL, the focus is on unifying the LIR data structure and\nvarious enums that don\u0027t really need to be target specific. Also\ncreates two new shared source files: GenCommon.cc (to hold\ntop-level code generation functions) and GenInvoke.cc (which\nis likely to be shared only by the Arm and Mips targets).\n\nAlso added is a makefile hack to build for Mips (which we\u0027ll\neventually remove when the compiler support multiple targets\nvia the command line) and various minor cleanups.\n\nOverall, this CL moves more than 3,000 lines of code from\ntarget dependent to target independent.\n\nChange-Id: I431ca4ae728100ed7d0e9d83a966a3f789f731b1\n"
    }
  ]
}