)]}' { "log": [ { "commit": "cac5a7e871f1f346b317894359ad06fa7bd67fba", "tree": "2df7d4892216a7c976dfe848c9893cb5eb8fa6a5", "parents": [ "6f51d7756a9c66007fe7666b19399e1f60ff6092" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Feb 22 10:39:50 2016 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Mar 29 19:27:40 2016 +0100" }, "message": "Optimizing: Improve const-string code generation.\n\nFor strings in the boot image, use either direct pointers\nor pc-relative addresses. For other strings, use PC-relative\naccess to the dex cache arrays for AOT and direct address of\nthe string\u0027s dex cache slot for JIT.\n\nFor aosp_flounder-userdebug:\n - 32-bit boot.oat: -692KiB (-0.9%)\n - 64-bit boot.oat: -948KiB (-1.1%)\n - 32-bit dalvik cache total: -900KiB (-0.9%)\n - 64-bit dalvik cache total: -3672KiB (-1.5%)\n (contains more files than the 32-bit dalvik cache)\nFor aosp_flounder-userdebug forced to compile PIC:\n - 32-bit boot.oat: -380KiB (-0.5%)\n - 64-bit boot.oat: -928KiB (-1.0%)\n - 32-bit dalvik cache total: -468KiB (-0.4%)\n - 64-bit dalvik cache total: -1928KiB (-0.8%)\n (contains more files than the 32-bit dalvik cache)\n\nBug: 26884697\nChange-Id: Iec7266ce67e6fedc107be78fab2e742a8dab2696\n" }, { "commit": "0ced281ae6216c29f57ca0f8b7388a722e8da97b", "tree": "b7f8273bb117c8ec8f8546ed937a8c0a96d2e5de", "parents": [ "843a65556616183a36792bbcc1632c6d8d0e78b2", "1a65388f1d86bb232c2e44fecb44cebe13105d2e" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Mar 24 10:25:51 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Mar 24 10:25:51 2016 +0000" }, "message": "Merge \"Clean up art::HConstant predicates.\"" }, { "commit": "1a65388f1d86bb232c2e44fecb44cebe13105d2e", "tree": "515e3000b3ad6d195101f20f33f3c9498e536593", "parents": [ "f808e8a0cc218c2b98023ef0e91f3c5b74ad2962" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Mar 18 18:05:57 2016 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Mar 18 18:05:57 2016 +0000" }, "message": "Clean up art::HConstant predicates.\n\n- Make the difference between arithmetic zero and zero-bit\n pattern non ambiguous.\n- Introduce Boolean predicates in art::HIntConstant for when\n they are used as Booleans.\n- Introduce aritmetic positive and negative zero predicates\n for floating-point constants.\n\nBug: 27639313\nChange-Id: Ia04ecc6f6aa7450136028c5362ed429760c883bd\n" }, { "commit": "2ae48182573da7087bffc2873730bc758ec29696", "tree": "d6955329ad876aefd477f7ef8905b070b9ab95dd", "parents": [ "6915898b28cea6c9836ca1be6814d87e89cc6d76" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Mar 16 14:05:09 2016 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Mar 16 14:10:27 2016 +0000" }, "message": "Clean up NullCheck generation and record stats about it.\n\nThis removes redundant code from the generators and allows for easier\nstat recording.\n\nChange-Id: Iccd4368f9e9d87a6fecb863dee4e2145c97851c4\n" }, { "commit": "4a0dad67867f389e01a5a6c0fe381d210f687c0d", "tree": "91f1e70f4a2d0bd32aa7eb51e546f5330d72f772", "parents": [ "d15ede2df7d157ea5480614fd18c2bf0d37a6c2a" ], "author": { "name": "Artem Udovichenko", "email": "artem.u@samsung.com", "time": "Tue Jan 26 12:28:31 2016 +0300" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Feb 25 10:14:30 2016 +0000" }, "message": "Revert \"Revert \"ARM/ARM64: Extend support of instruction combining.\"\"\n\nThis reverts commit 6b5afdd144d2bb3bf994240797834b5666b2cf98.\n\nChange-Id: Ic27a10f02e21109503edd64e6d73d1bb0c6a8ac6\n" }, { "commit": "9cd6d378bd573cdc14d049d32bdd22a97fa4d84a", "tree": "be293c89806b919143b7dcd203bae14f5f4eaf04", "parents": [ "0e02ee9efbf1dbdde05d2b10f7307bbe191c52f5" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Feb 09 15:24:47 2016 +0000" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Feb 24 10:25:29 2016 +0000" }, "message": "Associate slow paths with the instruction that they belong to.\n\nAlmost all slow paths already know the instruction they belong to,\nthis CL just moves the knowledge to the base class as well.\n\nThis is needed to be be able to get the corresponding dex pc for\nslow path, which allows us generate better native line numbers,\nwhich in turn fixes some native debugging stepping issues.\n\nChange-Id: I568dbe78a7cea6a43a4a71a014b3ad135782c270\n" }, { "commit": "c7098ff991bb4e00a800d315d1c36f52a9cb0149", "tree": "3a150e927bc7f4894f5b148ec6f5a2b796cdd80d", "parents": [ "5322e55ab9a15996a197456ca39d9c77488cd5c1" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Feb 09 14:30:11 2016 +0000" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Feb 24 10:21:57 2016 +0000" }, "message": "Remove HNativeDebugInfo from start of basic blocks.\n\nWe do not require full environment at the start of basic block.\nThe dex pc contained in basic block is sufficient for line mapping.\n\nChange-Id: I5ba9e5f5acbc4a783ad544769f9a73bb33e2bafa\n" }, { "commit": "6e332529c33be4d7dae5dad3609a839f4c0d3bfc", "tree": "cedd2e1beb170fd5821136fe974e3f34adfcddc2", "parents": [ "d3caabd4f85f86dd744da432993e12935d843a83" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Feb 02 16:15:27 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Feb 12 15:17:50 2016 +0000" }, "message": "ART: Remove HTemporary\n\nChange-Id: I21b984224370a9ce7a4a13a9652503cfb03c5f03\n" }, { "commit": "44015868a5ed9f6915d510ade42e84949b719e3a", "tree": "c23fd6c5de3d727ff310ef6fe06574a502133150", "parents": [ "28a2ff0bd6c30549f3f6465d8316f5707b1d072f" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jan 22 11:47:17 2016 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jan 22 11:47:17 2016 +0000" }, "message": "Revert \"Revert \"ARM64 Baker\u0027s read barrier fast path implementation.\"\"\n\nThis reverts commit 28a2ff0bd6c30549f3f6465d8316f5707b1d072f.\n\nBug: 12687968\nChange-Id: I6e25c70f303368629cdb1084f1d7039261cbb79a\n" }, { "commit": "28a2ff0bd6c30549f3f6465d8316f5707b1d072f", "tree": "4d181bd254584f78cf1f3d81d3acb23d6f2f8b3d", "parents": [ "c8f1df9965ca7f97ba9e6289f8c7a717765a59a9" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Thu Jan 21 18:21:59 2016 +0000" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Thu Jan 21 18:21:59 2016 +0000" }, "message": "Revert \"ARM64 Baker\u0027s read barrier fast path implementation.\"\n\nThis reverts commit c8f1df9965ca7f97ba9e6289f8c7a717765a59a9.\n\nThis breaks master.\n\nChange-Id: Ic07f602af8732e2835bd11f65e3b9e766d3349c7\n" }, { "commit": "c8f1df9965ca7f97ba9e6289f8c7a717765a59a9", "tree": "7c04fd5601293cc251651ce2df2dfd2416737a1c", "parents": [ "fef7aabd582ae0237a44947c5e0b24cb63e395f0" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jan 20 16:38:05 2016 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jan 20 16:38:05 2016 +0000" }, "message": "ARM64 Baker\u0027s read barrier fast path implementation.\n\nIntroduce an ARM64 fast path implementation in Optimizing\nfor Baker\u0027s read barriers (for both heap reference loads and\nGC root loads). The marking phase of the read barrier is\nperformed by a slow path, invoking the runtime entry point\nartReadBarrierMark.\n\nOther read barrier algorithms continue to use the original\nslow path based implementation, which has been renamed as\nGenerateReadBarrierSlow/GenerateReadBarrierForRootSlow.\n\nBug: 12687968\nBug: 26601270\nChange-Id: I60da15249b58a8ee1a065ed9be2c4e438ee17150\n" }, { "commit": "58282f4510961317b8d5a364a6f740a78926716f", "tree": "5d97c0db9fe01dd6e8df2357ef11f614abb853e8", "parents": [ "b8bb9f6d0b59be125066f604f134155f8998f5ae" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Jan 14 12:45:10 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Jan 18 16:39:30 2016 +0000" }, "message": "ART: Remove Baseline compiler\n\nWe don\u0027t need Baseline any more and it hasn\u0027t been maintained for\na while anyway. Let\u0027s remove it.\n\nChange-Id: I442ed26855527be2df3c79935403a25b1ee55df6\n" }, { "commit": "42249c3602c3d0243396ee3627ffb5906aa77c1e", "tree": "1e822a21c87331246cbde3923eac88fa315fa2cc", "parents": [ "922698ded1e80cad1ecce4c2172a88c76a216373" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Jan 07 15:33:50 2016 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Jan 12 16:39:20 2016 -0800" }, "message": "Reduce code size by sharing slow paths.\n\nRationale:\nSharing identical slow path code reduces code size.\n\nBackground:\nCurrently, slow paths with the same dex-pc, same physical register\nspilling code, and identical stack maps are shared (making this\nonly useful for deopt slow paths). The newly introduced mechanism\nis sufficiently general to allow future improvements by e.g.\nallowing different dex-pc (by passing this to runtime) or even\nthe kind of slow paths (by passing runtime addresses to the slowpath).\n\nChange-Id: I819615c47b4fd98440a241f681f93e4fc22d12e0\n" }, { "commit": "5f7b58ea1adfc0639dd605b65f59198d3763f801", "tree": "04556e673cdd3967cc967ff79931eab49e523956", "parents": [ "1201804d1813d7db0accead9721d67c40b3de564" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Nov 23 19:49:34 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Dec 23 09:59:07 2015 +0000" }, "message": "Rewrite HInstruction::Is/As\u003ctype\u003e().\n\nMake Is\u003ctype\u003e() and As\u003ctype\u003e() non-virtual for concrete\ninstruction types, relying on GetKind(), and mark GetKind()\nas PURE to improve optimization opportunities. This reduces\nthe number of relocations in libart-compiler.so\u0027s .rel.dyn\nsection by ~4K, or ~44%, and in .data.rel.ro by ~18K, or\n~65%. The file is 96KiB smaller for Nexus 5, including 8KiB\nreduction of the .text section.\n\nUnfortunately, the g++/clang++ __attribute__((pure)) is not\nstrong enough to avoid duplicated virtual calls and we would\nneed the C++ [[pure]] attribute proposed in n3744 instead.\nTo work around this deficiency, we introduce an extra\nnon-virtual indirection for GetKind(), so that the compiler\ncan optimize common expressions such as\n instruction-\u003eIsAdd() || instruction-\u003eIsSub()\nor\n instruction-\u003eIsAdd() \u0026\u0026 instruction-\u003eAsAdd()-\u003e...\nwhich contain two virtual calls to GetKind() after inlining.\n\nChange-Id: I83787de0671a5cb9f5b0a5f4a536cef239d5b401\n" }, { "commit": "22ccc3a93d32fa6991535eaebb17daf5abaf4ebf", "tree": "974af8f7cf41d131234eeb60dc8a7c4831f4a97f", "parents": [ "51a354c747c8a76a4716a49a1f70bfd975d63787" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Nov 24 13:10:05 2015 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Nov 24 13:10:05 2015 +0000" }, "message": "ARM64 read barrier support for concurrent GC in Optimizing.\n\nThis first implementation uses slow paths to instrument heap\nreference loads and GC root loads for the concurrent copying\ncollector, respectively calling the artReadBarrierSlow and\nartReadBarrierForRootSlow runtime entry points.\n\nNotes:\n- This implementation does not instrument HInvokeVirtual\n nor HInvokeInterface instructions (for class reference\n loads), as the corresponding read barriers are not stricly\n required with the current concurrent copying collector.\n- Intrinsics which may eventually call (on slow path) are\n disabled when read barriers are enabled, as the current\n slow path infrastructure does not support this case.\n- When read barriers are enabled, the code generated for a\n HArraySet instruction always go into the array set slow\n path for object arrays (delegating the operation to the\n runtime), as we are lacking a mechanism to keep a\n temporary register live accross a runtime call (needed for\n the instrumentation of type checking code, which requires\n two successive read barriers).\n\nBug: 12687968\nChange-Id: Icfb74f67bf23ae80e7723ee6a0c9ff34ba325d48\n" }, { "commit": "3927c8b8361336f1b16aae6eb2ed7577b20560f4", "tree": "daa5ffabb2103980538200097b5fb97c5bc2193a", "parents": [ "cb6638ff664e3136ccfee3cffb9307e0d43ffbc1" ], "author": { "name": "Zheng Xu", "email": "zheng.xu@linaro.org", "time": "Wed Nov 18 17:46:25 2015 +0800" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Nov 18 16:11:25 2015 +0000" }, "message": "Opt compiler: Arm64 packed-switch jump tables.\n\nIn this patch, we set a rough threshold and only generate jump table\nwith limited number of HIRs in the graph. This is because current VIXL\ncan only handle Adr with label in the range of +/-1Mb.\n\nChange-Id: I42bff2095ec26caeacc5efc90afebe34e229b518\n" }, { "commit": "a04f57badca0a9211d45eb7bde44c1d1e8f159ff", "tree": "49a3e42024120ca21165277abff8e7dc0949376d", "parents": [ "9013bb031c1c3244e70ae246437604f2c094a671", "6dc01748c61a7ad41d4ab701d3e27897bd39a899" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Nov 17 17:40:57 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Nov 17 17:40:57 2015 +0000" }, "message": "Merge \"Minor fixes and cleaning of arm64 static and direct calls code.\"" }, { "commit": "0debae7bc89eb05f7a2bf7dccd223318fad7c88d", "tree": "3da9656dc77d271b12c1b02793e7d713ae3da790", "parents": [ "991842a5273d20695dd5f35eb9a9e28c386c5b4b" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Nov 12 18:37:00 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Nov 17 15:12:00 2015 +0000" }, "message": "ART: Refactor GenerateTestAndBranch\n\nEach code generator implements a method for generating condition\nevaluation and branching to arbitrary labels. This patch refactors\nit for better clarity but also to generate fewer jumps when the true\nbranch is the fallthrough successor.\n\nThis is preliminary work for implementing HSelect.\n\nChange-Id: Iaa545a5ecbacb761c5aa241fa69140cf6eb5952f\n" }, { "commit": "6dc01748c61a7ad41d4ab701d3e27897bd39a899", "tree": "4c536fc4ab19c3f99b8dddfa8bafbe11deaec0d7", "parents": [ "cff81076cbb4bbe3841942f14326f4401fa3c8df" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Thu Nov 12 14:44:19 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Nov 12 17:58:50 2015 +0000" }, "message": "Minor fixes and cleaning of arm64 static and direct calls code.\n\nFixes:\nThe proper way to avoid the MacroAssembler to generate code before or\nafter an instruction is to block the pools (usually via\n`vixl::BlockPoolsScope`). Here we can use\n`vixl::SingleEmissionCheckScope`, that checks we generate only one\ninstruction and also blocks the pools.\nIn practice the current code would have worked fine because VIXL would\nnot have generated anything after `Bl()` or `Ldr()`, but that was not\nguaranteed.\n\nCleaning:\n- `XRegisterFrom()` returns an X register. Calling `.X()` is not\n required.\n- Since we are sure (after the previous fixes) that nothing will be\n emitted around the instructions we care about, update the code to\n bind labels before the instructions for simplicity.\n\nChange-Id: I42d49976721e380e66bcd7a5b345f1777009434a\n" }, { "commit": "0f7dca4ca0be8d2f8776794d35edf8b51b5bc997", "tree": "cb2d99a0e9b7c50eb853a64b477268baaa77c11b", "parents": [ "ce0f43b97ffb5e4d14c5df6607d8efb46a5dc9d2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Nov 02 14:36:43 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Nov 12 10:43:47 2015 +0000" }, "message": "Optimizing/X86: PC-relative dex cache array addressing.\n\nAdd PC-relative dex cache array addressing for X86 and use\nit for better invoke-static/-direct dispatch. Also delay\nthe initialization to the PC-relative base until needed.\n\nChange-Id: Ib8634d5edce4920cd70172fd13211809cf6948d1\n" }, { "commit": "cbf3c0f4e8335b460ce2faba3877d4b24fe492a1", "tree": "2118db00ced221b5fe55e5bb37738a8535cfa574", "parents": [ "1af35996afc82bfecb501fc5ecdc0d3350d8a532", "dc151b2346bb8a4fdeed0c06e54c2fca21d59b5d" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Oct 27 15:02:06 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Oct 27 15:02:06 2015 +0000" }, "message": "Merge \"Optimizing: Determine invoke-static/-direct dispatch early.\"" }, { "commit": "dc151b2346bb8a4fdeed0c06e54c2fca21d59b5d", "tree": "391d8ccb44ff9e6fc1c8fa8975e534e20cc002ff", "parents": [ "823e693aa946ba75cd047429e1290011a2ed8729" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 15 18:02:30 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 23 14:45:32 2015 +0100" }, "message": "Optimizing: Determine invoke-static/-direct dispatch early.\n\nDetermine the dispatch type of invoke-static/-direct in a\nspecial pass right after the type inference. This allows the\ninliner to pass the \"needs dex cache\" check and inline more.\nIt also allows the code generator to avoid requesting a\nregister location for the ArtMethod* for kDexCachePcRelative\nand direct methods.\n\nThe supported dispatch check handles also situations that\nthe CompilerDriver currently doesn\u0027t allow. The cleanup of\nthe CompilerDriver and required changes to Quick will come\nin a separate change.\n\nChange-Id: I3f8e903a119949e95871d8ab0a995f4731a13a07\n" }, { "commit": "e6dbf48d7a549e58a3d798bbbdc391e4d091b432", "tree": "e9edbb884c0143a38e0b32350119999bc11b4dee", "parents": [ "45513eb694fe55cf02ca6e8f0884621a6c3f6268" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Mon Oct 19 10:10:41 2015 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Mon Oct 19 10:10:41 2015 +0100" }, "message": "ARM64: Instruction simplification for array accesses.\n\nHArrayGet and HArraySet with variable indexes generate two\ninstructions on arm64, like\n\n add temp, obj, #data_offset\n ldr out, [temp, index LSL #shift_amount]\n\nWhen we have multiple accesses to the same array, the initial `add`\ninstruction is redundant.\n\nThis patch introduces the first instruction simplification in the\narm64-specific instruction simplification pass. It splits HArrayGet\nand HArraySet using the new arm64-specific IR HIntermediateAddress.\nAfter that we run GVN again to squash the multiple occurrences of\nHIntermediateAddress.\n\nChange-Id: I2e3d12fbb07fed07b2cb2f3f47f99f5a032f8312\n" }, { "commit": "e460d1df1f789c7c8bb97024a8efbd713ac175e9", "tree": "3511036fb18828dd0ee140d33a8bcd0535ebeab6", "parents": [ "25217af2a7cae96b32ba566aaf697288f3374c99" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Sep 29 04:52:17 2015 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Oct 02 02:25:18 2015 +0100" }, "message": "Revert \"Revert \"Support unresolved fields in optimizing\"\n\nThe CL also changes the calling convetion for 64bit static field set\nto use kArg2 instead of kArg1. This allows optimizing to keep\nthe asumptions:\n- arm pairs are always of form (even_reg, odd_reg)\n- ecx_edx is not used as a register on x86.\n\nThis reverts commit e6f49b47b6a4dc9c7684e4483757872cfc7ff1a1.\n\nChange-Id: I93159917565824084abc96775f31be1a4249f2f3\n" }, { "commit": "225b6464a58ebe11c156144653f11a1c6607f4eb", "tree": "3f1c6067c3841c892edaa1a60a61af9c559cb4e4", "parents": [ "6a9984e62c08bcd78c8e49dd40b1f0f9d53513b7" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Sep 28 12:17:40 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Sep 29 10:49:35 2015 +0100" }, "message": "Optimizing: Tag arena allocations in code generators.\n\nAnd completely remove the deprecated GrowableArray.\n\nReplace GrowableArray with ArenaVector in code generators\nand related classes and tag arena allocations.\n\nLabel arrays use direct allocations from ArenaAllocator\nbecause Label is non-copyable and non-movable and as such\ncannot be really held in a container. The GrowableArray\nnever actually constructed them, instead relying on the\nzero-initialized storage from the arena allocator to be\ncorrect. We now actually construct the labels.\n\nAlso avoid StackMapStream::ComputeDexRegisterMapSize() being\npassed null references, even though unused.\n\nChange-Id: I26a46fdd406b23a3969300a67739d55528df8bf4\n" }, { "commit": "85b62f23fc6dfffe2ddd3ddfa74611666c9ff41d", "tree": "c916b01b1608558a7d8c9d100274c4c6b6706386", "parents": [ "6766eae2d91e894b4ceab9f29cc983900e7bc0c7" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Sep 09 13:15:38 2015 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Sep 17 14:41:52 2015 -0700" }, "message": "ART: Refactor intrinsics slow-paths\n\nRefactor slow paths so that there is a default implementation for\ncommon cases (only arm64 with vixl is special). Write a generic\nintrinsic slow-path that can be reused for the specific architectures.\nMove helper functions into CodeGenerator so that they are accessible.\n\nChange-Id: Ibd788dce432601c6a9f7e6f13eab31f28dcb8550\n" }, { "commit": "e6f49b47b6a4dc9c7684e4483757872cfc7ff1a1", "tree": "6a5f45136832f73138ced75fcd3c6110b74116ea", "parents": [ "23a8e35481face09183a24b9d11e505597c75ebb" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Sep 17 14:04:33 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Sep 17 14:04:33 2015 +0000" }, "message": "Revert \"Support unresolved fields in optimizing\"\nbreaks debuggable tests.\n\nThis reverts commit 23a8e35481face09183a24b9d11e505597c75ebb.\n\nChange-Id: I8e60b5c8f48525975f25d19e5e8066c1c94bd2e5\n" }, { "commit": "23a8e35481face09183a24b9d11e505597c75ebb", "tree": "bcaafb6ea001349acbf160c2cc89334fab4a38dc", "parents": [ "175dc732c80e6f2afd83209348124df349290ba8" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Sep 08 19:56:31 2015 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Sep 17 12:29:59 2015 +0100" }, "message": "Support unresolved fields in optimizing\n\nChange-Id: I9941fa5fcb6ef0a7a253c7a0b479a44a0210aad4\n" }, { "commit": "175dc732c80e6f2afd83209348124df349290ba8", "tree": "6a5f45136832f73138ced75fcd3c6110b74116ea", "parents": [ "5d01db1aa7634a012109d43e6403451b76de1daa" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Aug 25 15:42:32 2015 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Sep 17 12:29:51 2015 +0100" }, "message": "Support unresolved methods in Optimizing\n\nChange-Id: If2da02b50d2fa668cd58f134a005f1752e7746b1\n" }, { "commit": "fe157012b6d760c275d944ff83e8bea371c59b09", "tree": "a2b013dded6e25cab1d3ff5abf09c426904e142c", "parents": [ "aef880c4b872ccf1a63a3c563cb056ae117fc9c8", "ecc4366670e12b4812ef1653f7c8d52234ca1b1f" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Sep 16 14:33:16 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Sep 16 14:33:16 2015 +0000" }, "message": "Merge \"Add OptimizingCompilerStats to the CodeGenerator class.\"" }, { "commit": "fa6b93c4b69e6d7ddfa2a4ed0aff01b0608c5a3a", "tree": "3528c88e104dac8e58ae5370ab066b8b1dd0218f", "parents": [ "e295be4a95d7861f6ec179edf6565f58cad747cc" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Sep 15 10:15:55 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 16 13:21:33 2015 +0100" }, "message": "Optimizing: Tag arena allocations in HGraph.\n\nReplace GrowableArray with ArenaVector in HGraph and related\nclasses HEnvironment, HLoopInformation, HInvoke and HPhi,\nand tag allocations with new arena allocation types.\n\nChange-Id: I3d79897af405b9a1a5b98bfc372e70fe0b3bc40d\n" }, { "commit": "bfb5ba90cd6425ce49c2125a87e3b12222cc2601", "tree": "6280171d451642dc70c87894d553f76c6c12db0a", "parents": [ "e6576390f957c82c2aede438834d028066757368" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Sep 01 15:45:02 2015 +0000" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Sep 08 20:36:09 2015 -0700" }, "message": "Revert \"Revert \"Do a second check for testing intrinsic types.\"\"\n\nThis reverts commit a14b9fef395b94fa9a32147862c198fe7c22e3d7.\n\nWhen an intrinsic with invoke-type virtual is recognized, replace\nthe instruction with a new HInvokeStaticOrDirect.\n\nMinimal update for dex-cache rework. Fix includes.\n\nChange-Id: I1c8e735a2fa7cda4419f76ca0717125ef236d332\n" }, { "commit": "ecc4366670e12b4812ef1653f7c8d52234ca1b1f", "tree": "fe7be52b1025b8122547b34d8765248d5959cd3a", "parents": [ "772cc4a2d4f978888d1b1e5a78c1c16a108260ed" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Thu Aug 13 13:33:12 2015 +0100" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Thu Aug 27 15:28:25 2015 +0100" }, "message": "Add OptimizingCompilerStats to the CodeGenerator class.\n\nJust refactoring, not yet used, but will be used by the incoming patch\nseries and future CodeGen specific stats.\n\nChange-Id: I7d20489907b82678120518a77bdab9c4cc58f937\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@linaro.org\u003e\n" }, { "commit": "581550137ee3a068a14224870e71aeee924a0646", "tree": "f62dd0d07c66a8ce4d7d994ee0e9c27bd8014bb1", "parents": [ "32f264e67afa8654a5570d38b627515fb73fc333" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 19 12:49:41 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 19 18:54:36 2015 +0100" }, "message": "Revert \"Revert \"Optimizing: Better invoke-static/-direct dispatch.\"\"\n\nFixed kCallArtMethod to use correct callee location for\nkRecursive. This combination is used when compiling with\ndebuggable flag set.\n\nThis reverts commit b2c431e80e92eb6437788cc544cee6c88c3156df.\n\nChange-Id: Idee0f2a794199ebdf24892c60f8a5dcf057db01c\n" }, { "commit": "b2c431e80e92eb6437788cc544cee6c88c3156df", "tree": "6c0ac5f843845e4b09829eb0fd9f1b3013cf4494", "parents": [ "9b688a095afbae21112df5d495487ac5231b12d0" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 19 12:45:42 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 19 12:45:42 2015 +0000" }, "message": "Revert \"Optimizing: Better invoke-static/-direct dispatch.\"\n\nReverting due to failing ndebug tests.\n\nThis reverts commit 9b688a095afbae21112df5d495487ac5231b12d0.\n\nChange-Id: Ie4f69da6609df3b7c8443412b6cf7f5c43c2c5d9\n" }, { "commit": "9b688a095afbae21112df5d495487ac5231b12d0", "tree": "e5e881d4d124803e66f1e90c1e0a0e4c90d22e13", "parents": [ "009c34cba875885d9540696f33255a9b355d6e15" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 06 14:12:42 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 19 12:23:37 2015 +0100" }, "message": "Optimizing: Better invoke-static/-direct dispatch.\n\nAdd framework for different types of loading ArtMethod*\nand code pointer retrieval. Implement invoke-static and\ninvoke-direct calls the same way as Quick. Document the\ndispatch kinds in HInvokeStaticOrDirect\u0027s new enumerations\nMethodLoadKind and CodePtrLocation.\n\nPC-relative loads from dex cache arrays are used only for\nx86-64 and arm64. The implementation for other architectures\nwill be done in separate CLs.\n\nChange-Id: I468ca4d422dbd14748e1ba6b45289f0d31734d94\n" }, { "commit": "3887c468d731420e929e6ad3acf190d5431e94fc", "tree": "67dacb849e722e33e118b97714a48e467c06cbd5", "parents": [ "6a5037eb3340e4c981fd7de3ff45167ee5b7fc82" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Aug 12 18:15:42 2015 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Aug 12 18:15:42 2015 +0100" }, "message": "Remove unnecessary `explicit` qualifiers on constructors.\n\nChange-Id: Id12e392ad50f66a6e2251a68662b7959315dc567\n" }, { "commit": "fc6a86ab2b70781e72b807c1798b83829ca7f931", "tree": "90201491e811cf7be0e0469d7a06a828f4384cad", "parents": [ "d3eaade87ac079accca30473ef0a3b38ab600828" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Jun 26 10:33:45 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Jun 26 13:49:50 2015 +0100" }, "message": "Revert \"Revert \"ART: Implement try/catch blocks in Builder\"\"\n\nThis patch enables the GraphBuilder to generate blocks and edges which\nrepresent the exceptional control flow when try/catch blocks are\npresent in the code. Actual compilation is still delegated to Quick\nand Baseline ignores the additional code.\n\nTo represent the relationship between try and catch blocks, Builder\nsplits the edges which enter/exit a try block and links the newly\ncreated blocks to the corresponding exception handlers. This layout\nwill later enable the SsaBuilder to correctly infer the dominators of\nthe catch blocks and to produce the appropriate reverse post ordering.\nIt will not, however, allow for building the complete SSA form of the\ncatch blocks and consequently optimizing such blocks.\n\nTo this end, a new TryBoundary control-flow instruction is introduced.\nCodegen treats it the same as a Goto but it allows for additional\nsuccessors (the handlers).\n\nThis reverts commit 3e18738bd338e9f8363b26bc895f38c0ec682824.\n\nChange-Id: I4f5ea961848a0b83d8db3673763861633e9bfcfb\n" }, { "commit": "3e18738bd338e9f8363b26bc895f38c0ec682824", "tree": "708013ef06cfb524f040b2b5c494f7f3cb84ac2c", "parents": [ "0b5c7d1994b76090afcc825e737f2b8c546da2f8" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Jun 26 09:59:52 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Jun 26 09:59:52 2015 +0000" }, "message": "Revert \"ART: Implement try/catch blocks in Builder\"\n\nCauses OutOfMemory issues, need to investigate.\n\nThis reverts commit 0b5c7d1994b76090afcc825e737f2b8c546da2f8.\n\nChange-Id: I263e6cc4df5f9a56ad2ce44e18932ca51d7e349f\n" }, { "commit": "0b5c7d1994b76090afcc825e737f2b8c546da2f8", "tree": "057eddf8830b1991f02af3c3ce1b63dee90dd2ad", "parents": [ "1dd3136d9f6b1c7d551897a2d96c8314e40f7324" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Jun 11 11:17:49 2015 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Jun 25 16:58:08 2015 +0100" }, "message": "ART: Implement try/catch blocks in Builder\n\nThis patch enables the GraphBuilder to generate blocks and edges which\nrepresent the exceptional control flow when try/catch blocks are\npresent in the code. Actual compilation is still delegated to Quick\nand Baseline ignores the additional code.\n\nTo represent the relationship between try and catch blocks, Builder\nsplits the edges which enter/exit a try block and links the newly\ncreated blocks to the corresponding exception handlers. This layout\nwill later enable the SsaBuilder to correctly infer the dominators of\nthe catch blocks and to produce the appropriate reverse post ordering.\nIt will not, however, allow for building the complete SSA form of the\ncatch blocks and consequently optimizing such blocks.\n\nTo this end, a new TryBoundary control-flow instruction is introduced.\nCodegen treats it the same as a Goto but it allows for additional\nsuccessors (the handlers).\n\nChange-Id: I415b985596d5bebb7b1bb358a46e08b7b04bb53a\n" }, { "commit": "eb7b7399dbdb5e471b8ae00a567bf4f19edd3907", "tree": "a0a488040883c14cc6cbec3186654137459d44ff", "parents": [ "8ec0e20347e13592539a8c0786b1db1735149800" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Jun 19 14:47:01 2015 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Jun 22 11:57:36 2015 +0100" }, "message": "Opt compiler: Add disassembly to the \u0027.cfg\u0027 output.\n\nThis is automatically added to the \u0027.cfg\u0027 output when using the usual\n`--dump-cfg` option.\n\nChange-Id: I864bfc3a8299c042e72e451cc7730ad8271e4deb\n" }, { "commit": "ef20f71e16f035a39a329c8524d7e59ca6a11f04", "tree": "a2892ae08f22ccf46baa4c77cea61f32bd07242d", "parents": [ "864a2d955aa85ab989c86d7f1eeacbe0b11f8b0f" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Tue Jun 09 10:29:30 2015 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Wed Jun 10 10:19:57 2015 +0100" }, "message": "Add boilerplate code for architecture-specific HInstructions.\n\nChange-Id: I2723cd96e5f03012c840863dd38d7b2168117db8\n" }, { "commit": "69aa60163989c33a008115205d39732a76ecc1dc", "tree": "058392dc104a8e7b3594a548239dca2d3ec06cce", "parents": [ "aa77f6e5839b2ad3bf8ca2c06a44ec92e2667af1" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jun 09 10:34:25 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jun 09 16:01:49 2015 +0100" }, "message": "Revert \"Revert \"Pass current method to HNewInstance and HNewArray.\"\"\n\nProblem exposed by this change was fixed in:\nhttps://android-review.googlesource.com/#/c/154031/\n\nThis reverts commit 7b0e353b49ac3f464c662f20e20e240f0231afff.\n\nChange-Id: I680c13dc9db9ba223ab11c7af255222860b4e6d2\n" }, { "commit": "7b0e353b49ac3f464c662f20e20e240f0231afff", "tree": "b5c936df891b08521176065ccaddb1f9e27c9f46", "parents": [ "e21aa42e1341d34250742abafdd83311ad9fa737" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jun 09 09:25:50 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jun 09 09:25:50 2015 +0000" }, "message": "Revert \"Pass current method to HNewInstance and HNewArray.\"\n\n082-inline-execute fails on x86.\n\nThis reverts commit e21aa42e1341d34250742abafdd83311ad9fa737.\n\nChange-Id: Ib3fd25faee2e0128001e40d3d51a74f959bc4449\n" }, { "commit": "e21aa42e1341d34250742abafdd83311ad9fa737", "tree": "d2c9f8530e59876588d32f04b4effc25ebc0fa89", "parents": [ "c47908e8c32fd58bc4dc75998a80f706954db1dc" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 08 15:35:07 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 08 15:36:27 2015 +0100" }, "message": "Pass current method to HNewInstance and HNewArray.\n\nAlso remove unsed CodeGenerator::LoadCurrentMethod.\n\nChange-Id: I4b8d3f2a30b8e2c76b6b329a72555483c993cb73\n" }, { "commit": "38207af82afb6f99c687f64b15601ed20d82220a", "tree": "f9360949b92e5b6b01c5828c03ac67d01adffe1d", "parents": [ "6a0d5e7fe6dc0c9d3dd941ab991203f2d5d1c354" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 01 15:46:22 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 04 14:39:06 2015 +0100" }, "message": "Use HCurrentMethod in HInvokeStaticOrDirect.\n\nChange-Id: I0d15244b6b44c8b10079398c55da5071a3e3af66\n" }, { "commit": "fd88f16100cceafbfde1b4f095f17e89444d6fa8", "tree": "fdb6d0520ca419acef9e953e74dcbd7d908bc4dd", "parents": [ "1aebdae18678403bdac078cbbe1f7dd4243c44f3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 03 11:23:52 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 03 11:23:52 2015 +0100" }, "message": "Factorize code for common LocationSummary of HInvoke.\n\nThis is one step forward, we could factorize more, but\nI wanted to get this out of the way first.\n\nChange-Id: I6ae411a737eebaecb64974f47af507ce0cfbae85\n" }, { "commit": "e401d146407d61eeb99f8d6176b2ac13c4df1e33", "tree": "17927f9bfe7d2041b5942c89832d55f9dedb24c5", "parents": [ "2006b7b9b8e32722bd0d640c62549d8a0ac624b6" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed Apr 22 13:56:20 2015 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri May 29 18:45:49 2015 -0700" }, "message": "Move mirror::ArtMethod to native\n\nOptimizing + quick tests are passing, devices boot.\n\nTODO: Test and fix bugs in mips64.\n\nSaves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS.\nSome of the savings are from removal of virtual methods and direct\nmethods object arrays.\n\nBug: 19264997\nChange-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d\n" }, { "commit": "9bd88b0933a372e6a7b64b850868e6a7998567e2", "tree": "bcd275674c1234842b757ea8e100c4030f9ac6fe", "parents": [ "01cb410f4ad23135671d821ba36c269f8c82affa" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Wed Apr 22 16:24:46 2015 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri May 22 12:01:07 2015 +0100" }, "message": "ARM64: Move xSELF from x18 to x19.\n\nThis patch moves xSELF to callee saved x19 and removes support for\nETR (external thread register), previously used across native calls.\n\nChange-Id: Icee07fbb9292425947f7de33d10a0ddf98c7899b\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@linaro.org\u003e\n" }, { "commit": "48fb0b7be18a783de9cd1b246042c1ec5b732c49", "tree": "4b977dd414301330586dd828736dd6ff03056647", "parents": [ "45970a4cde2fb12e1cb1515aaf0d9cb9869c5116", "07276db28d654594e0e86e9e467cad393f752e6e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue May 19 11:43:08 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue May 19 11:43:08 2015 +0000" }, "message": "Merge \"Don\u0027t do a null test in MarkGCCard if the value cannot be null.\"" }, { "commit": "07276db28d654594e0e86e9e467cad393f752e6e", "tree": "6450e07d64045f0c0949b3423501316b672641c7", "parents": [ "17f1bc531ea2f8c1a6fac3def13dee1b901949dd" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 18 14:22:09 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 18 19:15:52 2015 +0100" }, "message": "Don\u0027t do a null test in MarkGCCard if the value cannot be null.\n\nChange-Id: I45687f6d3505178e2fc3689eac9cb6ab1b2c1e29\n" }, { "commit": "2f9d1379fdebcdeeac52eaeff25ad5697c6b6ffb", "tree": "6fe7dd64fc17928540cac48162c4b6471fc2ab6a", "parents": [ "5969307a254fb731a464119506b2cef9404871b9", "da40309f61f98c16d7d58e4c34cc0f5eef626f93" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 18 15:25:39 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon May 18 15:25:40 2015 +0000" }, "message": "Merge \"Opt compiler: ARM64: Use ldp/stp on arm64 for slow paths.\"" }, { "commit": "c66671076b12a0ee8b9d1ae782732cc91beacb73", "tree": "e8007c01f0bce06dcd3b0d6e2db9e7079fc4dd04", "parents": [ "ef4366a159ecdd357c98e577583bbe224d065128" ], "author": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Fri May 15 16:08:45 2015 +0800" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri May 15 16:10:29 2015 +0100" }, "message": "Opt compiler: Speedup div/rem by constants on arm32 and arm64.\n\nThis patch also includes:\n1. Add java test for div/rem negative constants.\n2. Fix a thumb2 encoding issue where the last operand is\n \"reg, shift #amount\" in some instructions.\n3. Support a simple filter in arm32 assembler test to filter out\n unsupported cases, such as \"smull r0, r0, r1, r2\".\n4. Add smull arm32 assembler test.\n5. Add smull/umull thumb2 test.\n6. Add test for the thumb2 encoding issue which is fixed in this\n patch.\n\nChange-Id: I1601bc9c38f70f11909f2816fe3ec105a158951e\n" }, { "commit": "2d27c8e338af7262dbd4aaa66127bb8fa1758b86", "tree": "e01e0bc57359df0bdf00c3da694c5403fb7fc9e6", "parents": [ "3adfc4bbe6c42d574bd2069d8e38a13d5ad98ccf" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Apr 28 15:48:45 2015 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Apr 29 14:09:17 2015 +0100" }, "message": "Refactor InvokeDexCallingConventionVisitor in Optimizing.\n\nChange-Id: I7ede0f59d5109644887bf5d39201d4e1bf043f34\n" }, { "commit": "da40309f61f98c16d7d58e4c34cc0f5eef626f93", "tree": "7525c544dc9acae0e1041757149be2eabb733dc8", "parents": [ "021190bf584662e75b269ef47cd48e2044e34fe4" ], "author": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Fri Apr 24 17:35:39 2015 +0800" }, "committer": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Fri Apr 24 17:38:13 2015 +0800" }, "message": "Opt compiler: ARM64: Use ldp/stp on arm64 for slow paths.\n\nIt should be a bit faster than load/store single registers and reduce\nthe code size.\n\nChange-Id: I67b8302adf6174b7bb728f7c2afd2c237e34ffde\n" }, { "commit": "27eac12a66a73eb38b5ccb45b62350cf341299d0", "tree": "7cc7eea6dd543720da2921c11f68296f5df37b07", "parents": [ "e40d82ffe388458c2674ec051f1dd897362692eb", "ad4450e5c3ffaa9566216cc6fafbf5c11186c467" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Apr 20 15:20:15 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Apr 20 15:20:15 2015 +0000" }, "message": "Merge \"Opt compiler: Implement parallel move resolver without using swap.\"" }, { "commit": "09a99965bb27649f5b1d373f76bfbec6a2500c9e", "tree": "a1584b26a5b6f3dee692d0b21373de27734c965f", "parents": [ "2e0f89b1b61685f7c322a4c6ec3e3b4839e76d64" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Wed Apr 15 11:47:56 2015 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Mon Apr 20 14:45:01 2015 +0100" }, "message": "Opt compiler: ARM64: Follow other archs for a few codegen stubs.\n\nCode generation for HInstanceFieldGet, HInstanceFieldSet,\nHStaticFieldGet, and HStaticFieldSet are refactored to follow the\nstructure used for other backends.\n\nChange-Id: I34a3bd17effa042238c6bf199848cbc2ec26ac5d\n" }, { "commit": "ad4450e5c3ffaa9566216cc6fafbf5c11186c467", "tree": "eecf36e8e9d8112e765ad8840eb2d27f8d0415ab", "parents": [ "f8bdd9f3a002970e4b8fdcf6fe6730116f1626c3" ], "author": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Fri Apr 17 18:48:56 2015 +0800" }, "committer": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Fri Apr 17 18:54:08 2015 +0800" }, "message": "Opt compiler: Implement parallel move resolver without using swap.\n\nThe algorithm of ParallelMoveResolverNoSwap() is almost the same with\nParallelMoveResolverWithSwap(), except the way we resolve the circular\ndependency. NoSwap() uses additional scratch register to resolve the\ncircular dependency. For example, (0-\u003e1) (1-\u003e2) (2-\u003e0) will be performed\nas (2-\u003escratch) (1-\u003e2) (0-\u003e1) (scratch-\u003e0).\n\nOn architectures without swap register support, NoSwap() can reduce the\nnumber of moves from 3x(N-1) to (N+1) when there is circular dependency\nwith N moves.\n\nAnd also, NoSwap() algorithm does not depend on architecture register\nlayout information, which means it can support register pairs on arm32\nand X/W, D/S registers on arm64 without additional modification.\n\nChange-Id: Idf56bd5469bb78c0e339e43ab16387428a082318\n" }, { "commit": "69a503050fb8a7b3a79b2cd2cdc2d8fbc594575d", "tree": "b7f99172f921d7100959ab48210097906794d043", "parents": [ "e015a31e509c3f4de8a90b57b77329ba6609ce2f" ], "author": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Tue Apr 14 20:04:41 2015 +0800" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Apr 14 17:29:08 2015 +0100" }, "message": "ARM64: Remove suspend register.\n\nIt also clean up build/remove frame used by JNI compiler and generates\nstp/ldp instead of str/ldr. Also x19 has been unblocked in both quick and\noptimizing compiler.\n\nChange-Id: Idbeac0942265f493266b2ef9b7a65bb4054f0e2d\n" }, { "commit": "c6b4dd8980350aaf250f0185f73e9c42ec17cd57", "tree": "ef8d73e37abc04aecb430072a8bc463c73398fee", "parents": [ "dd97393aca1a3ff2abec4dc4f78d7724300971bc" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Apr 07 20:32:43 2015 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu Apr 09 16:47:50 2015 +0100" }, "message": "Implement CFI for Optimizing.\n\nCFI is necessary for stack unwinding in gdb, lldb, and libunwind.\n\nChange-Id: I1a3480e3a4a99f48bf7e6e63c4e83a80cfee40a2\n" }, { "commit": "d43b3ac88cd46b8815890188c9c2b9a3f1564648", "tree": "6c599c3f40d57e92786bd7f41c0541d9eaa2643b", "parents": [ "a109632b240f3c9355ca95500f6f48e4478e3c51" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Wed Apr 01 14:03:04 2015 -0700" }, "committer": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Wed Apr 01 14:05:13 2015 -0700" }, "message": "Revert \"Revert \"Deoptimization-based bce.\"\"\n\nThis reverts commit 0ba627337274ccfb8c9cb9bf23fffb1e1b9d1430.\n\nChange-Id: I1ca10d15bbb49897a0cf541ab160431ec180a006\n" }, { "commit": "82e52ce8364e3e1c644d0d3b3b4f61364bf7089a", "tree": "d26020cbee67645a46838c57747d2ba1533ba5d1", "parents": [ "ebbb1e322d8c89e69424a543faa03402e5b63673" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Thu Mar 26 16:50:57 2015 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Tue Mar 31 15:53:57 2015 +0100" }, "message": "ARM64: Update to VIXL 1.9.\n\nUpdate VIXL\u0027s interface to VIXL 1.9.\n\nChange-Id: Iebae947539cbad65488b7195aaf01de284b71cbb\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "d75948ac93a4a317feaf136cae78823071234ba5", "tree": "7593fb8c1ba2b67decdaa967b6348501f58d8b9d", "parents": [ "b3665e3dfdd23cc7a2f17a0b53bb16205bf4151f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 27 09:53:16 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 27 12:01:40 2015 +0000" }, "message": "Intrinsify String.compareTo.\n\nChange-Id: Ia540df98755ac493fe61bd63f0bd94f6d97fbb57\n" }, { "commit": "0ba627337274ccfb8c9cb9bf23fffb1e1b9d1430", "tree": "0e1d0813c1d8d1c7239a900c1653296975713df0", "parents": [ "e295e6ec5beaea31be5d7d3c996cd8cfa2053129" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Mar 24 02:39:46 2015 +0000" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Mar 24 02:39:46 2015 +0000" }, "message": "Revert \"Deoptimization-based bce.\"\n\nThis breaks compiling the core image:\n\n Error after BCE: art::SSAChecker: Instruction 219 in block 1 does not dominate use 221 in block 1.\n\nThis reverts commit e295e6ec5beaea31be5d7d3c996cd8cfa2053129.\n\nChange-Id: Ieeb48797d451836ed506ccb940872f1443942e4e\n" }, { "commit": "e295e6ec5beaea31be5d7d3c996cd8cfa2053129", "tree": "4d8a657d23d511743ce35bee596544d7f652efdb", "parents": [ "d24ba2c44c76a2b2dd13aafe8f7981c15be31a98" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Sat Mar 07 06:37:59 2015 -0800" }, "committer": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Mon Mar 23 16:39:37 2015 -0700" }, "message": "Deoptimization-based bce.\n\nA mechanism is introduced that a runtime method can be called\nfrom code compiled with optimizing compiler to deoptimize into\ninterpreter. This can be used to establish invariants in the managed code\nIf the invariant does not hold at runtime, we will deoptimize and continue\nexecution in the interpreter. This allows to optimize the managed code as\nif the invariant was proven during compile time. However, the exception\nwill be thrown according to the semantics demanded by the spec.\n\nThe invariant and optimization included in this patch are based on the\nlength of an array. Given a set of array accesses with constant indices\n{c1, ..., cn}, we can optimize away all bounds checks iff all 0 \u003c\u003d min(ci) and\nmax(ci) \u003c array-length. The first can be proven statically. The second can be\nestablished with a deoptimization-based invariant. This replaces n bounds\nchecks with one invariant check (plus slow-path code).\n\nChange-Id: I8c6e34b56c85d25b91074832d13dba1db0a81569\n" }, { "commit": "eeefa1276e83776f08704a3db4237423b0627e20", "tree": "d7c647ca77703f3712f567704f40b00d59a125de", "parents": [ "02c0bac34c246c1bd974dbb86d292d4b52ba98e4" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 18:52:59 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Mar 16 10:48:21 2015 +0000" }, "message": "Update locations of registers after slow paths spilling.\n\nChange-Id: Id9aafcc13c1a085c17ce65d704c67b73f9de695d\n" }, { "commit": "579885a26d761f5ba9550f2a1cd7f0f598c2e1e3", "tree": "58d144157b7a24bbdf7f8892631a15abeefa2c9f", "parents": [ "2eb5168bd9e43b80452eaee5be32c063e124886e" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Sun Feb 22 20:51:33 2015 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Mon Mar 02 14:16:56 2015 +0000" }, "message": "Opt Compiler: ARM64: Enable explicit memory barriers over acquire/release\n\nImplement remaining explicit memory barrier code paths and temporarily\nenable the use of explicit memory barriers for testing.\n\nThis CL also enables the use of instruction set features in the ARM64\nbackend. kUseAcquireRelease has been replaced with PreferAcquireRelease(),\nwhich for now is statically set to false (prefer explicit memory barriers).\n\nPlease note that we still prefer acquire-release for the ARM64 Optimizing\nCompiler, but we would like to exercise the explicit memory barrier code\npath too.\n\nChange-Id: I84e047ecd43b6fbefc5b82cf532e3f5c59076458\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "dc23d8318db08cb42e20f1d16dbc416798951a8b", "tree": "e7a883bb3263ccb971898df98bc58700604c1d1d", "parents": [ "e5f5953e744060fde3b4489cea4d934d529e3e32" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Feb 16 11:15:43 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Feb 18 09:53:32 2015 +0000" }, "message": "Avoid generating jmp +0.\n\nWhen a block branches to a non-following block, but blocks\nin-between do branch to it, we can avoid doing the branch.\n\nChange-Id: I9b343f662a4efc718cd4b58168f93162a24e1219\n" }, { "commit": "3d087decd1886b818adcccd4f16802e5e54dd03e", "tree": "2be4d4a62d972e33150b517ff71b3023a095c8bd", "parents": [ "ca9a26859d2ca8e106316dd5f16b60a325f0533c" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Wed Jan 28 11:57:05 2015 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Thu Feb 05 20:12:31 2015 +0000" }, "message": "Opt Compiler: ARM64: Enable Callee-saved register, as defined by AAPCS64.\n\nFor now we block kQuickSuspendRegister - x19, since Quick and the runtime\nuse this as a suspend counter register.\n\nChange-Id: I090d386670e81e7924e4aa9a3864ef30d0580a30\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "1cf95287364948689f6a1a320567acd7728e94a3", "tree": "70a8b60c768894d635cf63b0a480baa5073d2bed", "parents": [ "4a50662eeaa0b1a26be66e7584fb765151dabc59" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Dec 12 19:22:03 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 29 10:52:14 2015 +0000" }, "message": "Small optimization for recursive calls: avoid dex cache.\n\nChange-Id: I044757a2f06e535cdc1480c4fc8182b89635baf6\n" }, { "commit": "878d58cbaf6b17a9e3dcab790754527f3ebc69e5", "tree": "1c1af4ef938ad06a783da51e2c6276d6b0628da6", "parents": [ "b80c3154d3b6359d8ad4ce50d3a6a68224400cdd" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jan 15 23:24:00 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jan 28 15:32:40 2015 -0800" }, "message": "ART: Arm64 optimizing compiler intrinsics\n\nImplement most intrinsics for the optimizing compiler for Arm64.\n\nChange-Id: Idb459be09f0524cb9aeab7a5c7fccb1c6b65a707\n" }, { "commit": "d97dc40d186aec46bfd318b6a2026a98241d7e9c", "tree": "5cf0257eda25e2722a1adafb9de22690c06a56d8", "parents": [ "c698b78a17043d8898deb817098181595fbe734e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 22 13:50:01 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 23 09:20:42 2015 +0000" }, "message": "Support callee save floating point registers on x64.\n\n- Share the computation of core_spill_mask and fpu_spill_mask\n between backends.\n- Remove explicit stack overflow check support: we need to adjust\n them and since they are not tested, they will easily bitrot.\n\nChange-Id: I0b619b8de4e1bdb169ea1ae7c6ede8df0d65837a\n" }, { "commit": "988939683c26c0b1c8808fc206add6337319509a", "tree": "876e94428276547a29c27ccf17509a42dfe7cda1", "parents": [ "59add47cabce3735ccd470cd3b5dac8b112e09ab" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 12:32:32 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 18:50:25 2015 +0000" }, "message": "Enable core callee-save on x64.\n\nWill work on other architectures and FP support in other CLs.\n\nChange-Id: I8cef0343eedc7202d206f5217fdf0349035f0e4d\n" }, { "commit": "77520bca97ec44e3758510cebd0f20e3bb4584ea", "tree": "2e3be6fdc182e5cf5ae390019457af5e9c1ed242", "parents": [ "4d2c611bf17ff309abfa152e56c0b98a21ec8787" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Jan 12 18:45:46 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Jan 21 14:26:35 2015 +0000" }, "message": "Record implicit null checks at the actual invoke time.\n\nImplicitNullChecks are recorded only for instructions directly (see NB\nbelow) preceeded by NullChecks in the graph. This way we avoid recording\nredundant safepoints and minimize the code size increase.\n\nNB: ParallalelMoves might be inserted by the register allocator between\nthe NullChecks and their uses. These modify the environment and the\ncorrect action would be to reverse their modification. This will be\naddressed in a follow-up CL.\n\nChange-Id: Ie50006e5a4bd22932dcf11348f5a655d253cd898\n" }, { "commit": "cd6dffedf1bd8e6dfb3fb0c933551f9a90f7de3f", "tree": "0d83e9fdf65bded684d6e836078f253e63b7e11f", "parents": [ "12c03ac7575db242a6f35739bb459e8277115da4" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Jan 08 17:35:35 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Jan 16 17:27:03 2015 +0000" }, "message": "Add implicit null checks for the optimizing compiler\n\n- for backends: arm, arm64, x86, x86_64\n- fixed parameter passing for CodeGenerator\n- 003-omnibus-opcodes test verifies that NullPointerExceptions work as\nexpected\n\nChange-Id: I1b302acd353342504716c9169a80706cf3aba2c8\n" }, { "commit": "f85a9ca9859ad843dc03d3a2b600afbaf2e9bbdd", "tree": "a802042fa7a3a8cb820916d558e630596daaa9b4", "parents": [ "8fccea249b1a6f1469eeea42c2b2cca06ce1c70d" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Jan 13 09:20:58 2015 -0500" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Jan 15 11:21:37 2015 -0500" }, "message": "[optimizing compiler] Compute live spill size\n\nThe current stack frame calculation assumes that each live register to\nbe saved/restored has the word size of the machine. This fails for X86,\nwhere a double in an XMM register takes up 8 bytes. Change the\ncalculation to keep track of the number of core registers and number of\nfp registers to handle this distinction.\n\nThis is slightly pessimal, as the registers may not be active at the\nsame time, but the only way to handle this would be to allocate both\nclasses of registers simultaneously, or remember all the active\nintervals, matching them up and compute the size of each safepoint\ninterval.\n\nChange-Id: If7860aa319b625c214775347728cdf49a56946eb\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "840e5461a85f8908f51e7f6cd562a9129ff0e7ce", "tree": "ea8b4cbc5a0e3dea96fefcd9247e6c06b17ac518", "parents": [ "893e8881e31180721512c1b9e5ffacb03aad2e45" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 07 16:01:24 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 08 13:57:51 2015 +0000" }, "message": "Implement double and float support for arm in register allocator.\n\nThe basic approach is:\n- An instruction that needs two registers gets two intervals.\n- When allocating the low part, we also allocate the high part.\n- When splitting a low (or high) interval, we also split the high\n (or low) equivalent.\n- Allocation follows the (S/D register) requirement that low\n registers are always even and the high equivalent is low + 1.\n\nChange-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797\n" }, { "commit": "02d81cc8d162a31f0664249535456775e397b608", "tree": "8bce70d3d44dcc9384d72e4edc1505e4d1a6ea07", "parents": [ "8558375377946aabbbda6ab584e13f754590bd89" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Mon Jan 05 16:08:49 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Jan 05 18:23:33 2015 +0000" }, "message": "Opt Compiler: ARM64: Add support for rem-float, rem-double and volatile.\n\nAdd support for rem-float, rem-double and volatile memory accesses\nusing acquire-release and memory barriers.\n\nChange-Id: I96a24dff66002c3b772c3d8e6ed792e3cb59048a\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "5b4b898ed8725242ee6b7229b94467c3ea3054c8", "tree": "46f6df76e49f9a42dae89a6b9cf8336eae1da519", "parents": [ "6004796d6c630696127df2494dcd4f30d1367a34" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 17:45:56 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 17:45:56 2014 +0000" }, "message": "Revert \"Don\u0027t block quick callee saved registers for optimizing.\"\n\nX64 has one libcore test failing, and codegen_test on\narm is failing.\n\nThis reverts commit 6004796d6c630696127df2494dcd4f30d1367a34.\n\nChange-Id: I20e00431fa18e11ce4c0cb6fffa91977fa8e9b4f\n" }, { "commit": "6004796d6c630696127df2494dcd4f30d1367a34", "tree": "850f3e82a47061200c4e34e2c7e7a934f4769a97", "parents": [ "407d77f344cfbdbbfb50531c5f0766bc0892e2fe" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 15 00:01:18 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 14:59:50 2014 +0000" }, "message": "Don\u0027t block quick callee saved registers for optimizing.\n\nThis change builds on:\nhttps://android-review.googlesource.com/#/c/118983/\n\n- Also fix x86_64 assembler bug triggered by this change.\n- Fix (and improve) x86\u0027s backend byte register usage.\n- Fix a bug in baseline register allocator: a fixed\n out register must prevent inputs from allocating it.\n\nChange-Id: I4883862e29b4e4b6470f1823cf7eab7e7863d8ad\n" }, { "commit": "3e69f16ae3fddfd24f4f0e29deb106d564ab296c", "tree": "c796b1a2f71d4410af9fbdcb970b548a681f3955", "parents": [ "776b880f66edb21cb3b4225877e494ec7a9ec1a2" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Wed Dec 10 10:36:50 2014 +0000" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Wed Dec 10 14:36:14 2014 +0000" }, "message": "Opt compiler: Add arm64 support for register allocation.\n\nChange-Id: Idc6e84eee66170de4a9c0a5844c3da038c083aa7" }, { "commit": "02164b352a1474c616771582ca9a73a2cc514c1f", "tree": "6c124ec6e19f18343b69df8cddcb74e17447f294", "parents": [ "32f5b4d2c8c9b52e9522941c159577b21752d0fa" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Thu Nov 13 14:05:07 2014 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Fri Nov 28 13:10:25 2014 +0000" }, "message": "Opt Compiler: Arm64: Add support for more IRs plus various fixes.\n\nAdd support for more IRs and update others.\n\nChange-Id: Iae1bef01dc3c0d238a46fbd2800e71c38288b1d2\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "32f5b4d2c8c9b52e9522941c159577b21752d0fa", "tree": "1b30de145c7865fd8a79f17a4cfe67b1b890878c", "parents": [ "eea79dd779ba199658ada7264f8f96d776e53f19" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Tue Nov 25 20:05:46 2014 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Fri Nov 28 12:02:58 2014 +0000" }, "message": "Vixl: Update the VIXL interface to VIXL 1.7 and enable VIXL debug.\n\nThis patch updates the interface to VIXL 1.7 and enables the debug version of\nVIXL when ART is built in debug mode.\n\nChange-Id: I443fb941bec3cffefba7038f93bb972e6b7d8db5\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "86a8d7afc7f00ff0f5ea7b8aaf4d50514250a4e6", "tree": "3db61320369973e463f67927a8983d7eb0d9f860", "parents": [ "255a5bde2f0014dc86a564555106a4291c0867b4" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 19 08:47:18 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 19 08:47:18 2014 +0000" }, "message": "Consistently use k{InstructionSet}WordSize.\n\nThese constants were defined prior to k{InstructionSet}PointerSize. So\nuse them consistently in optimizing as a first step. We can discuss\nwhether we should remove them in a second step.\n\nChange-Id: If129de1a3bb8b65f8d9c816a8ad466815fb202e6\n" }, { "commit": "67555f7e9a05a9d436e034f67ae683bbf02d072d", "tree": "9a01b7c69032b08b3c55c18076f68c1e397d8a35", "parents": [ "bf75c5cf32a47eecadcc5e4a324237c1f1d09cde" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Tue Nov 18 10:55:16 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Nov 18 15:36:36 2014 +0000" }, "message": "Opt compiler: Add support for more IRs on arm64.\n\nChange-Id: I4b6425135d1af74912a206411288081d2516f8bf\n" }, { "commit": "f0e3937b87453234d0d7970b8712082062709b8d", "tree": "e552c1173ee90fea1d2ba11cc08878efe65ba0be", "parents": [ "59321e0e10ea09694efecf6154704e2743b9bffd" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 12 17:50:07 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 12 17:55:24 2014 +0000" }, "message": "Do a parallel move in BoundsCheckSlowPath.\n\nThe two locations of the index and length could overlap,\nso we need a parallel move. Also factorize the code for\ndoing a parallel move based on two locations.\n\nChange-Id: Iee8b3459e2eed6704d45e9a564fb2cd050741ea4\n" }, { "commit": "fc19de8b201475231751b9df08fce01a093e5c2b", "tree": "7c0e9c923a37d059f1707156d69f4908aca308ac", "parents": [ "a89086e3be94fb262c4c4feb15241b30616c3b8f" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Fri Nov 07 17:13:31 2014 +0000" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Mon Nov 10 17:31:38 2014 +0000" }, "message": "Opt compiler: Add arm64 support for a few more IRs.\n\nChange-Id: I781ddcbc61eb2b04ae80b1c7697e1ed5694bd5b9" }, { "commit": "a89086e3be94fb262c4c4feb15241b30616c3b8f", "tree": "82878d8a6c5418c43ff45857b81db7c88af7d455", "parents": [ "974bc2747b345667e07692109d63675ec50955a3" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Fri Nov 07 17:13:25 2014 +0000" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Mon Nov 10 17:31:17 2014 +0000" }, "message": "Opt compiler: Add arm64 support for floating-point.\n\nChange-Id: I0d97ab0f5ab770fee62c819505743febbce8835e" }, { "commit": "de58ab2c03ff8112b07ab827c8fa38f670dfc656", "tree": "c872bfbcad1e90845008140bbddcc43e56dc19d2", "parents": [ "3ed86e4e98dfe1b05c9a03aa2aee42c145a018c3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 05 12:46:03 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Nov 06 16:49:52 2014 +0000" }, "message": "Implement try/catch/throw in optimizing.\n\n- We currently don\u0027t run optimizations in the presence of a try/catch.\n- We therefore implement Quick\u0027s mapping table.\n- Also fix a missing null check on array-length.\n\nChange-Id: I6917dfcb868e75c1cf6eff32b7cbb60b6cfbd68f\n" }, { "commit": "6a3c1fcb4ba42ad4d5d142c17a3712a6ddd3866f", "tree": "9df58b57af13240a93a6da4eefcf03f70cce9ad9", "parents": [ "c6e0955737e15f7c0c3575d4e13789b3411f4993" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Oct 31 00:33:20 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Nov 03 20:01:04 2014 -0800" }, "message": "Remove -Wno-unused-parameter and -Wno-sign-promo from base cflags.\n\nFix associated errors about unused paramenters and implict sign conversions.\nFor sign conversion this was largely in the area of enums, so add ostream\noperators for the effected enums and fix tools/generate-operator-out.py.\nTidy arena allocation code and arena allocated data types, rather than fixing\nnew and delete operators.\nRemove dead code.\n\nChange-Id: I5b433e722d2f75baacfacae4d32aef4a828bfe1b\n" }, { "commit": "5319defdf502fc4569316473846b83180ec08035", "tree": "909c6b29f065c79c8368a283946947cbb582d1c7", "parents": [ "37a7188810e865a1ee0a7bdc2d01d62c1f1ea49e" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Thu Oct 23 10:03:10 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Oct 23 13:44:42 2014 +0100" }, "message": "ART: optimizing compiler: initial support for ARM64.\n\nThe ARM64 port uses VIXL for code generation, to which it defers work\nlike label binding and branch resolving, register type coherency\nchecking, and immediate values handling.\n\nChange-Id: I0a44508c0c991f472a63e67b3469cdd878fe1a68\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\nSigned-off-by: Alexandre Rames \u003calexandre.rames@arm.com\u003e\n" } ] }