)]}'
{
  "log": [
    {
      "commit": "33bff25bcd7a02d35c54f63740eadb1a4833fc92",
      "tree": "553db4f60878acf2a0fa7036a739d406df9a29b7",
      "parents": [
        "321b3ca9a36d769283c64d4bdee0798db80af524"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Nov 01 14:35:42 2017 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Nov 02 10:11:02 2017 +0000"
      },
      "message": "ART: Make InstructionSet an enum class and add kLast.\n\nAdding InstructionSet::kLast shall make it easier to encode\nthe InstructionSet in fewer bits using BitField\u003c\u003e. However,\nintroducing `kLast` into the `art` namespace is not a good\nidea, so we change the InstructionSet to an enum class.\nThis also uncovered a case of InstructionSet::kNone being\nerroneously used instead of vixl32::Condition::None(), so\nit\u0027s good to remove `kNone` from the `art` namespace.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nChange-Id: I6fa6168dfba4ed6da86d021a69c80224f09997a6\n"
    },
    {
      "commit": "e764d2e50c544c2cb98ee61a15d613161ac6bd17",
      "tree": "112aa7ca459d2edb4f800897060a2407fcc622c7",
      "parents": [
        "ca6fff898afcb62491458ae8bcd428bfb3043da1"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Oct 05 14:35:55 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Oct 09 10:39:22 2017 +0100"
      },
      "message": "Use ScopedArenaAllocator for register allocation.\n\nMemory needed to compile the two most expensive methods for\naosp_angler-userdebug boot image:\n  BatteryStats.dumpCheckinLocked() : 25.1MiB -\u003e 21.1MiB\n  BatteryStats.dumpLocked(): 49.6MiB -\u003e 42.0MiB\nThis is because all the memory previously used by Scheduler\nis reused by the register allocator; the register allocator\nhas a higher peak usage of the ArenaStack.\n\nAnd continue the \"arena\"-\u003e\"allocator\" renaming.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nBug: 64312607\nChange-Id: Idfd79a9901552b5147ec0bf591cb38120de86b01\n"
    },
    {
      "commit": "ca6fff898afcb62491458ae8bcd428bfb3043da1",
      "tree": "195a6b16d3a4b34acc2faf91ce56f448efb15e07",
      "parents": [
        "aa7273e56fbafc2692c8d20a31b50d2f4bdd2aa1"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Oct 03 14:49:14 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Oct 06 17:53:50 2017 +0100"
      },
      "message": "ART: Use ScopedArenaAllocator for pass-local data.\n\nPasses using local ArenaAllocator were hiding their memory\nusage from the allocation counting, making it difficult to\ntrack down where memory was used. Using ScopedArenaAllocator\nreveals the memory usage.\n\nThis changes the HGraph constructor which requires a lot of\nchanges in tests. Refactor these tests to limit the amount\nof work needed the next time we change that constructor.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: Build with kArenaAllocatorCountAllocations \u003d true.\nBug: 64312607\nChange-Id: I34939e4086b500d6e827ff3ef2211d1a421ac91a\n"
    },
    {
      "commit": "5daa4950038a4329ac745059f1ad0927d4a60166",
      "tree": "48fdf4d85953e931bd455ede290e769979e3906c",
      "parents": [
        "2b03a1f24600c8c9558fb13d3f8bca1ef0f8ee40"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Mon Jul 03 17:23:56 2017 +0100"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Fri Aug 11 11:44:50 2017 +0100"
      },
      "message": "Instrument ARM generated code to check the Marking Register.\n\nGenerate run-time code in the Optimizing compiler checking that\nthe Marking Register\u0027s value matches `self.tls32_.is.gc_marking`\nin debug mode (on target; and on host with JIT, or with AOT when\ncompiling the core image). If a check fails, abort.\n\nTest: m test-art-target\nTest: m test-art-target with tree built with ART_USE_READ_BARRIER\u003dfalse\nTest: ARM device/emulator boot test with libartd\nBug: 37707231\nChange-Id: I903f44d385d66ff74d65aa09d7113aa9cb7b9f24\n"
    },
    {
      "commit": "2b03a1f24600c8c9558fb13d3f8bca1ef0f8ee40",
      "tree": "4d5fb728acd7f98f8949c84364375a804ff0ba63",
      "parents": [
        "461ec567f16039374dff35e2f3b808986c100249"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Tue Jun 06 16:09:59 2017 +0100"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Thu Aug 10 18:17:47 2017 +0100"
      },
      "message": "Instrument ARM64 generated code to check the Marking Register.\n\nGenerate run-time code in the Optimizing compiler checking that\nthe Marking Register\u0027s value matches `self.tls32_.is.gc_marking`\nin debug mode (on target; and on host with JIT, or with AOT when\ncompiling the core image). If a check fails, abort.\n\nTest: m test-art-target\nTest: m test-art-target with tree built with ART_USE_READ_BARRIER\u003dfalse\nTest: ARM64 device boot test with libartd.\nBug: 37707231\nChange-Id: Ie9b322b22b3d26654a06821e1db71dbda3c43061\n"
    },
    {
      "commit": "71da4878f2e3f0dc8b7c3a31b4f57172fde5f378",
      "tree": "ae560b5e56ce09cfaaf1f3c04e96366f193c4180",
      "parents": [
        "b22ae40038aeeebb16936fbf62b48f080d6e7ef4"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Wed Jul 26 10:02:07 2017 -0700"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Wed Jul 26 11:23:03 2017 -0700"
      },
      "message": "ART: Move simulator to art/\n\nMove the simulator library out of the runtime directory. Let\u0027s not\npollute the runtime library.\n\nTest: m\nChange-Id: I351a0061ae628c3af0462b72d4de727db296ec23\n"
    },
    {
      "commit": "9983e302384c12a975c8d2d5ae239f79fd8e1996",
      "tree": "4e4d269fe1a3d4f0f1b93cd972adab9f17aab8e0",
      "parents": [
        "bac2bd1c2fbdd94f4d4dfe83d8451f655e875e36"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Fri Jul 14 14:34:22 2017 +0100"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Fri Jul 14 17:25:39 2017 +0100"
      },
      "message": "Remove the old ARM code generator from ART\u0027s Optimizing compiler.\n\nThe AArch32 VIXL-based code generator has been the default\nARM code generator in ART for some time now. The old ARM\ncode generator does not compile anymore; retiring it.\n\nTest: test.py\nBug: 63316036\nChange-Id: Iab8fbc4ac73eac2c1a809cd7b22fec6b619755db\n"
    },
    {
      "commit": "7d157fcaaae137cc98dbfb872aa1bdc0105a898f",
      "tree": "2b7d8affda23908e5bfbfaad446079db2ef1ee09",
      "parents": [
        "58d7ddc678e5bcd2364c24c4bdc8a3cfbcfc5358"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed May 10 16:29:23 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu May 11 11:14:54 2017 +0100"
      },
      "message": "Clean up some uses of \"auto\".\n\nMake actual types more explicit, either by replacing \"auto\"\nwith actual type or by assigning std::pair\u003c\u003e elements of\nan \"auto\" variable to typed variables. Avoid binding const\nreferences to temporaries. Avoid copying a container.\n\nTest: m test-art-host-gtest\nChange-Id: I1a59f9ba1ee15950cacfc5853bd010c1726de603\n"
    },
    {
      "commit": "d9911eeca13f609c885e0f6a5ce81af9b6340bfa",
      "tree": "f850510643ee120dba140bf0bb3e1c1b9c9ce4db",
      "parents": [
        "46bfb7c047a590ac5c24b658f31c170631556bb6"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Mon Mar 27 13:27:24 2017 -0700"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Mon Mar 27 13:53:48 2017 -0700"
      },
      "message": "ART: Clean up field initialization\n\nAdd explicit field initialization to default value where necessary.\nAlso clean up interpreter intrinsics header.\n\nTest: m\nChange-Id: I7a850ac30dcccfb523a5569fb8400b9ac892c8e5\n"
    },
    {
      "commit": "22aa54bf8469689c7c6c33f15ff4df2ffba8fa15",
      "tree": "14204d55784dce3ffdd2641382a763afee85ced0",
      "parents": [
        "8116003cc9dd1e74fac1682eec547b8bb0afb061"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Tue Oct 18 09:32:29 2016 +0100"
      },
      "committer": {
        "name": "xueliang.zhong",
        "email": "xueliang.zhong@linaro.org",
        "time": "Wed Jan 25 14:25:20 2017 +0000"
      },
      "message": "AArch64: Add HInstruction scheduling support.\n\nThis commit adds a new `HInstructionScheduling` pass that performs\nbasic scheduling on the `HGraph`.\n\nCurrently, scheduling is performed at the block level, so no\n`HInstruction` ever leaves its block in this pass.\n\nThe scheduling process iterates through blocks in the graph. For\nblocks that we can and want to schedule:\n1) Build a dependency graph for instructions. It includes data\n   dependencies (inputs/uses), but also environment dependencies and\n   side-effect dependencies.\n2) Schedule the dependency graph. This is a topological sort of the\n   dependency graph, using heuristics to decide what node to schedule\n   first when there are multiple candidates. Currently the heuristics\n   only consider instruction latencies and schedule first the\n   instructions that are on the critical path.\n\nTest: m test-art-host\nTest: m test-art-target\n\nChange-Id: Iec103177d4f059666d7c9626e5770531fbc5ccdc\n"
    }
  ]
}