)]}' { "log": [ { "commit": "14e5a29a8c5dcd971376a4a04b3c3b05100b3f86", "tree": "81c607cde36b6481ed2cd2d8b41293f62a5521f8", "parents": [ "e0943873483cb2169e5360e1f746931a3371aa24" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jun 28 12:00:56 2018 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Aug 14 18:01:43 2018 +0100" }, "message": "Rename art::ReadBarrier::WhiteState as art::ReadBarrier::NonGrayState.\n\nThe read barrier state recorded in object\u0027s lockword used to be a\nthree-state value (white/gray/black), which was turned into a\ntwo-state value (white/gray), where the \"black\" state was conceptually\nmerged into the \"white\" state. This change renames the \"white\" state\nas \"non-gray\" and adjusts corresponding comments.\n\nTest: art/test.py\nChange-Id: I2a17ed15651bdbbe99270c1b81b4d78a1c2c132b\n" }, { "commit": "c73f05242a6688c8edec46c1ff257a1efbd4b519", "tree": "68b95952ec9710da3aabf7a686725692a9fd5cf5", "parents": [ "9e113dd00d94526d7e6e546ac9bd4f066db3a019" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Aug 14 15:16:50 2018 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Aug 14 15:20:33 2018 +0100" }, "message": "Document the use of the biased card table in ART\u0027s code generators.\n\nTest: n/a\nChange-Id: Ie03a6f6dc87fd0766fc2b685ec39a0a0ebe3fb57\n" }, { "commit": "9d479254d0dc4043a15ab26205f40439eca15493", "tree": "af8a9c9c6f2c28e723a971c9d39c9d1cebd1f814", "parents": [ "ca20fb6cc4dda392e63bdc8ec9de54d89793373e" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 24 11:35:20 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 03 11:43:30 2018 +0000" }, "message": "Rename type resolution entrypoints.\n\nRename the InitializeType and InitializeTypeAndVerifyAccess\nentrypoints to Resolve* to better match their semantics.\nKeep the InitializeStaticStorage name for now as the most\nappropriate name InitializeType would clash with the old\nname of the ResolveType entrypoint.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nChange-Id: Ide55b58c490d085ab37d8536f90699f7ed571d59\n" }, { "commit": "3232dbb6df866985089b13a36c56e2b39dd473ab", "tree": "055f3e8888bfb3cfd072a981e4733cfaad7b202c", "parents": [ "b27d874ebc0c067d96994a6ebe3c10eaeb2e4a75" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jul 25 15:42:46 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 03 08:59:07 2018 +0000" }, "message": "Do not save/restore regs in ClinitCheck slow path.\n\nThe entrypoint is kSaveEverything, so the only register that\nneeds to be saved is the argument/return value register.\n\nThe size of the aosp_taimen-userdebug prebuilts:\n - before:\n arm/boot*.oat: 16811692\n arm64/boot*.oat: 19801032\n oat/arm64/services.odex: 20232208\n - after:\n arm/boot*.oat: 16798804 (-12.6KiB, -0.08%)\n arm64/boot*.oat: 19804392 (+3.3KiB, +0.02%)\n oat/arm64/services.odex: 20227784 (-4.3KiB, -0.02%)\nNote that though there is less code, the metadata for the\narm64/boot*.oat outweighs the code size reduction because of\nthe register map encoding as value+shift introduced in\n https://android-review.googlesource.com/695682\nwhich it\u0027s ill-suited for kSaveEverything entrypoints. We\nshould reconsider that encoding.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nChange-Id: I5cd1deb90332a3b88a0a59d87925c557d9bff1ab\n" }, { "commit": "a9f303c089aa2b2fc82d97201352945678ef54ae", "tree": "0df0eb5294a3ee72aea8ca670762c02ca9ffa8dd", "parents": [ "1bfd891d06e276d602b4a6ccf1a9f70967195218" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jul 20 16:43:56 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Aug 02 17:41:21 2018 +0100" }, "message": "Rewrite Class init entrypoint to take a Class arg.\n\nFixes invalid type index being passed to the entrypoint for\nclass init check across dex files when the target type does\nnot have a TypeId in the compilation unit\u0027s DexFile.\n\nThe size of the aosp_taimen-userdebug prebuilts:\n - before:\n arm/boot*.oat: 16782748\n arm64/boot*.oat: 19764400\n oat/arm64/services.odex: 20162432\n - after:\n arm/boot*.oat: 16811692 (+28.3KiB, +0.17%)\n arm64/boot*.oat: 19801032 (+35.8KiB, +0.19%)\n oat/arm64/services.odex: 20232208 (+68.1KiB, +0.35%)\nThis increase comes from doing two runtime calls instead of\none for HLoadClass/kBssEntry that MustGenerateClinitCheck().\n\nTest: Additional test in 476-clinit-inline-static-invoke\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --jit\nTest: testrunner.py --jvm\nBug: 111433619\nChange-Id: I2fccd6944480ab4dac514f60d38e72c1014ae7b2\n" }, { "commit": "8e524ad3c690c183b1a71f6114796974a107c5dd", "tree": "6ee124814e8f33fd4706eb15fcad2cae0019546b", "parents": [ "5991b184a40e4ce181d67d683ced46caa6143b53" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jul 13 10:27:43 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jul 16 10:12:51 2018 +0100" }, "message": "Always produce PIC code for AOT compilation.\n\nChange sharpening to use PIC load kinds for AOT compilation\nand add \"Jit\" to the direct addressing load kind names. Use\nPIC code also for the Integer.valueOf() intrinsic codegen.\nRemove all support for non-PIC linker patches.\n\nThe dex2oat --compile-pic option is retained for now but\nignored by the compiler.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nBug: 77856493\nChange-Id: I54d666f6522f160a1b6ece4045a15d19363acbb6\n" }, { "commit": "d109e30eab8ba25f8d89be2a83d9036e2d541af2", "tree": "24df91603efe9ce8c4a2efd09ac402aceb10df4e", "parents": [ "c916736ca1e375c276df251446baf2ac8ff3eb13" ], "author": { "name": "Alex Light", "email": "allight@google.com", "time": "Wed Jun 27 10:25:41 2018 -0700" }, "committer": { "name": "Alex Light", "email": "allight@google.com", "time": "Tue Jul 10 08:44:51 2018 -0700" }, "message": "Don\u0027t use StringFactory.newEmptyString in compiled code\n\nWhen compiling debuggable code we would compile a new-instance String\ninstruction into a StringFactory.newEmptyString invoke. This\nadditional invoke could be observed using tracing and is inconsistent\nwith the interpreter, where the string is simply allocated directly.\nIn order to bring these two modes into alignment we added a new\nAllocStringObject quick entrypoint that will be used instead of the\nnormal AllocObject\u003c...\u003e entrypoints when allocating a string. This\nentrypoint directly allocates a new string in the same manner the\ninterpreter does.\n\nNeeds next CL for test to work.\n\nBug: 110884646\nTest: ./test/testrunner/testrunner.py --host --runtime-option\u003d-Xjitthreshold:0 --jit\nTest: Manual inspection of compiled code.\nChange-Id: I7b4b084bcf7dd9a23485c0e3cd2cd04a04b43d3d\n" }, { "commit": "6fd1606a3f3fc2dd53ab4f8b371e420b3e33c74f", "tree": "9f944d267ce3616eb969c027665e4a451c2b3879", "parents": [ "bb089b6bf850c87e0e42917a383cc7298dcb09c5" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 26 11:02:04 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 29 14:39:00 2018 +0100" }, "message": "Implement Integer.valueOf() intrinsic for boot image.\n\nAnd generate only one \"boot image live objects\" array rather\nthan one per boot*.art file.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nBug: 71526895\nChange-Id: I23af7f47fea5150805f801cd2512f2d152ee5b73\n" }, { "commit": "a043111e3a2c09b549708a6227a1f54d91da76aa", "tree": "393fe11cfceccebf474e4bdf36ff79b70b97f589", "parents": [ "213ee2da6a1c58d0fc12c937bbd9c9974ca00aca" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 25 09:32:54 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 25 18:43:19 2018 +0100" }, "message": "Move instruction_set_ to CompilerOptions.\n\nRemoves CompilerDriver dependency from ImageWriter and\nseveral other classes.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: m test-art-target-gtest\nTest: testrunner.py --target --optimizing\nChange-Id: I3c5b8ff73732128b9c4fad9405231a216ea72465\n" }, { "commit": "eebb821b1adaf2db7662fc1c3ff4e9fcfe59a694", "tree": "a3d3cf5f8c20d03fccdc0808537904da63e74938", "parents": [ "7e56bd41cde4e489a11050d9e340bf8b5692d9e8" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 05 14:57:24 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jun 21 16:12:28 2018 +0100" }, "message": "Implement Integer.valueOf() intrinsic for PIC.\n\nAnd fix the intrinsic for JIT even in case when someone\nmesses up the IntegerCache using reflection. Two cases are\nexposed with a regression test (one that previously failed\nrandomly and one that failed 100%) but other crashes were\npossible; for example, we would need a read barrier for\narray reads when elements are not guaranteed to be in the\nboot image.\n\nThe new approach loads references only from the boot image\nlive objects array which cannot be touched by reflection.\nThe referenced objects and IntegerCache.cache are exposed\nand can lead to weird behavior but not crashes.\n\nOn x86, the pc_relative_fixups_86 actually checks the cache\nan additional time but discrepancies between this check and\nthe location building at the beginning of codegen should be\nOK as the HIsX86ComputeBaseMethodAddress should be added\nfor PIC regardless of whether pc_relative_fixups_86 thinks\nthe method is intrinsified or not.\n\nTest: 717-integer-value-of\nTest: Pixel 2 XL boots.\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --pictest --npictest\nTest: testrunner.py --host --jit\nTest: testrunner.py --target --optimizing --pictest --npictest\nTest: testrunner.py --target --jit\nBug: 71526895\nChange-Id: I89b3245a62aba22980c86a99e2af480bfa250af1\n" }, { "commit": "4c8e12e66968929b36fac6a2237ca4b04160161e", "tree": "d8bbfd72a978c69ef2eef98c37e7869673c52295", "parents": [ "20c64f8d802cc575cc9a1a1f6c493a611b23e2ee" ], "author": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Fri May 18 08:33:20 2018 +0100" }, "committer": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Mon Jun 11 10:57:17 2018 +0100" }, "message": "ART: Adds an entrypoint for invoke-custom\n\nAdd support for the compiler to call into the runtime for\ninvoke-custom bytecodes.\n\nBug: 35337872\nTest: art/test.py --host -r -t 952\nTest: art/test.py --target --64 -r -t 952\nTest: art/test.py --target --32 -r -t 952\nChange-Id: I821432e7e5248c91b8e1d36c3112974c34171803\n" }, { "commit": "d02b23f7ee9664213216a82bfdcb0ee83824de04", "tree": "254b794533a6821c2ed2df31fab807abf7d508a4", "parents": [ "08231f6cb3095a7dbde29299a7da5413a5f992e4" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue May 29 23:27:22 2018 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed May 30 17:59:24 2018 +0100" }, "message": "Remove the CodeOffset helper class.\n\nI need to reduce the StackMapEntry to a POD type so that it\ncan be used in BitTableBuilder.\n\nTest: test-art-host-gtest-stack_map_test\nChange-Id: I5f9ad7fdc9c9405f22669a11aea14f925ef06ef7\n" }, { "commit": "dbaa5c7ba8935cf87ceb40a4054f9842929e9a51", "tree": "5037625c80cb97a0e13026dc450db28e59ff72ca", "parents": [ "51dda39549033b3c50a7fce5522ffc81325db54b" ], "author": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Thu May 10 08:22:46 2018 +0100" }, "committer": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Fri May 11 11:55:30 2018 +0100" }, "message": "ART: Compiler support for const-method-handle\n\nImplemented as a runtime call.\n\nBug: 66890674\nTest: art/test.py --target -r -t 979\nTest: art/test.py --target --64 -r -t 979\nTest: art/test.py --host -r -t 979\nChange-Id: I67f461c819a7d528d7455afda8b4a59e9aed381c\n" }, { "commit": "18259d7fb7164a5e029df4f883b3a79ccc2403e8", "tree": "ba378bfdef4127bb0607215186e3b150fd38bcdf", "parents": [ "922501b4bbf724e4259477a27764291684eedffb" ], "author": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Thu Apr 12 11:18:23 2018 +0100" }, "committer": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Thu May 10 15:04:09 2018 +0100" }, "message": "ART: Compiler support for const-method-type\n\nImplemented as a runtime call.\n\nBug: 66890674\nTest: art/test.py --target -r -t 979\nTest: art/test.py --target --64 -r -t 979\nTest: art/test.py --host -r -t 979\nChange-Id: I4b3d3969d455d0198cfe122eea8abd54e0ea20ee\n" }, { "commit": "175e7862dbdb44089ef327fc43ba00c791fd3838", "tree": "7b7ff4327b51b57e47e4b22af8d771edb9d462c1", "parents": [ "77c6fc7341143dd27c74cddd786398688d7b4c91" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Mar 27 09:03:13 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Mar 27 10:04:25 2018 +0100" }, "message": "Revert^4 \"Compiler changes for bitstring based type checks.\"\n\nDisabled the build time flag. (No image version bump needed.)\n\nBug: 26687569\nBug: 64692057\nBug: 76420366\n\nThis reverts commit 3fbd3ad99fad077e5c760e7238bcd55b07d4c06e.\n\nChange-Id: I5d83c4ce8a7331c435d5155ac6e0ce1c77d60004\n" }, { "commit": "3fbd3ad99fad077e5c760e7238bcd55b07d4c06e", "tree": "e8bc33fa60c38f7e1c85f8d4acf6a738df9b426a", "parents": [ "3f41323cc9da335e9aa4f3fbad90a86caa82ee4d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Mar 26 21:14:46 2018 +0000" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Mar 26 21:14:46 2018 +0000" }, "message": "Revert^3 \"Compiler changes for bitstring based type checks.\"\n\nThis reverts commit 3f41323cc9da335e9aa4f3fbad90a86caa82ee4d.\n\nReason for revert: Fails sporadically.\n\nBug: 26687569\nBug: 64692057\nBug: 76420366\nChange-Id: I84d1e9e46c58aeecf17591ff71fbac6a1e583909\n" }, { "commit": "3f41323cc9da335e9aa4f3fbad90a86caa82ee4d", "tree": "ce41c620d2cd411da3c20aa95fb9a69328e77c42", "parents": [ "9ec1e24ebc683b15bb9c6db5554ac2ff9458adae" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Feb 12 18:39:15 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Mar 22 12:12:39 2018 +0000" }, "message": "Revert^2 \"Compiler changes for bitstring based type checks.\"\n\nAdd extra output for debugging failures and re-enable\nthe bitstring type checks.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: testrunner.py --host -t 670-bitstring-type-check\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --jit\nTest: testrunner.py --target -t 670-bitstring-type-check\nBug: 64692057\nBug: 26687569\n\nThis reverts commit bff7a52e2c6c9e988c3ed1f12a2da0fa5fd37cfb.\n\nChange-Id: I090e241983f3ac6ed8394d842e17716087d169ac\n" }, { "commit": "9992e095643f6746361df03c4c98e742d9ad5899", "tree": "8abf49af54ee57fc0acebf2a3d9cafd87d6ec48e", "parents": [ "a5867bfeb34529dad71220046e7327cef23af207", "e47f60c482648172334aaca59e6c1ab7a3d42610" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Mar 09 10:17:11 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Mar 09 10:17:11 2018 +0000" }, "message": "Merge \"Retrieve String/Class references from .data.bimg.rel.ro.\"" }, { "commit": "8ba5641ddc43fc13cdb0158bd9f3237c4a90a356", "tree": "4dad508f24b675e87dd31ff26e597289a329c5cc", "parents": [ "66f40dbc3e56c7102820842ec49a55b70cf0e151", "b066d43b1d9184899aff32b1f243d092611ad9c6" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Mar 08 17:45:59 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Mar 08 17:45:59 2018 +0000" }, "message": "Merge \"Load ArtMethod* from .data.bimg.rel.ro entries.\"" }, { "commit": "e47f60c482648172334aaca59e6c1ab7a3d42610", "tree": "ae0672b12a6ad200e1c38962c77bccfc3e5cb531", "parents": [ "b066d43b1d9184899aff32b1f243d092611ad9c6" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Feb 21 13:43:28 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Mar 08 10:40:12 2018 +0000" }, "message": "Retrieve String/Class references from .data.bimg.rel.ro.\n\nFor PIC AOT-compiled app, use the .data.bimg.rel.ro to load\nthe boot image String/Class references instead of using the\nmmapped boot image ClassTable and InternTable.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --pictest --npictest\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --pictest --npictest\nBug: 71526895\nChange-Id: Id5703229777aecb589a933a41f92e44d3ec02a3d\n" }, { "commit": "b066d43b1d9184899aff32b1f243d092611ad9c6", "tree": "5409177f52b1f1c648297913cb0e0b2808b9048d", "parents": [ "fe491c7b9cdd64ff4ccc10f6b212cb92a59fc765" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jan 03 13:14:37 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Mar 08 10:40:10 2018 +0000" }, "message": "Load ArtMethod* from .data.bimg.rel.ro entries.\n\nIntroduce a new .data.bimg.rel.ro section in oat files where\nwe store offsets of boot image objects from the beginning of\nthe boot image. At runtime we relocate these entries using\nthe actual boot image address to turn offsets to pointers.\n\nUse the .data.bimg.rel.ro to prepare the boot image methods\nused by HInvokeStaticOrDirect for PIC AOT app compilation.\nLoading the ArtMethod* from .data.bimg.rel.ro instead of the\n.bss avoids the initial call to the resolution trampoline.\n\nTest: Additional test in 522-checker-sharpening\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --pictest --npictest\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --pictest --npictest\nBug: 71526895\nChange-Id: Ie5f5b1f622704877b36730377146e59092e46c0c\n" }, { "commit": "351df3e70521ebbe00ed6c7ac4ea25a0c26f4034", "tree": "8a22bf2eb06d2a5e57c6d6272ac070d368467118", "parents": [ "72efc159bf4e5cde85cd28e78316681effdceb5b" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 07 11:54:57 2018 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 07 12:00:42 2018 -0800" }, "message": "Minor cleanup of MIN/MAX code.\n\nRationale:\nShare the type dispatching code better.\n\nBug: b/65164101\n\nTest: test-art-host,target\nChange-Id: Ib06c915d570fd0a53f7734cdb316d2d16310db74\n" }, { "commit": "1f8d51bc03cbc607ae32fadf3a90f385adeffb95", "tree": "70e18902051ce47e0d524525b83709efbe6f250f", "parents": [ "7a02c66fd9ed174fc2e49ccc9f582dd661b7de9e" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Feb 15 10:42:37 2018 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 07 09:22:09 2018 -0800" }, "message": "Introduce MIN/MAX/ABS as HIR nodes.\n\nRationale:\nHaving explicit MIN/MAX/ABS operations (in contrast\nwith intrinsics) simplifies recognition and optimization\nof these common operations (e.g. constant folding, hoisting,\ndetection of saturation arithmetic). Furthermore, mapping\nconditionals, selectors, intrinsics, etc. (some still TBD)\nonto these operations generalizes the way they are optimized\ndownstream substantially.\n\nBug: b/65164101\n\nTest: test-art-host,target\n\nChange-Id: I69240683339356e5a012802f179298f0b04c6726\n" }, { "commit": "4927ba0f5011b7394e52dca2c3cec52f265f8529", "tree": "9214177a5617f2024dcf2b75b016e2b5c063d3c6", "parents": [ "7664e3473747565d438afb19f1cf7edb5a57e5e9", "3dad341ed027b760d9b4ee402cb2c93ac484a07a" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon Mar 05 17:53:15 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Mar 05 17:53:15 2018 +0000" }, "message": "Merge \"Introduce ABS as HIR nodes.\"" }, { "commit": "3dad341ed027b760d9b4ee402cb2c93ac484a07a", "tree": "a69817c3b2d455273b23d083267ef08c8b9adaee", "parents": [ "d961043ff1dd6fddb68aa90c1f939cfafec24219" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Feb 28 12:01:46 2018 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Mar 01 13:07:04 2018 -0800" }, "message": "Introduce ABS as HIR nodes.\n\nNOTE: step 1 of 2 for\n\"Introduce MIN/MAX/ABS as HIR nodes.\"\n\nRationale:\nHaving explicit MIN/MAX/ABS operations (in contrast\nwith intrinsics) simplifies recognition and optimization\nof these common operations (e.g. constant folding, hoisting,\ndetection of saturation arithmetic). Furthermore, mapping\nconditionals, selectors, intrinsics, etc. (some still TBD)\nonto these operations generalizes the way they are optimized\ndownstream substantially.\n\nBug: b/65164101\n\nTest: test-art-host,target\nChange-Id: I9c93987197216158ba02c8aca2385086adedabc4\n" }, { "commit": "3177e104e727b802770cebe59dd19d708e0942a7", "tree": "87c84f95bbea34aa8651ab478c4ec460a4f4dacb", "parents": [ "1ccfa59c180c62f88091048c3f7f65f1d511ed0c" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@mips.com", "time": "Wed Feb 28 11:32:40 2018 +0100" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@mips.com", "time": "Thu Mar 01 13:34:58 2018 +0100" }, "message": "MIPS: Use sltiu instead of LoadConst32() + sltu\n\nBltu is sltu + bnez so we can use sltiu + bnez without\nloading constant (if it is 16-bit constant).\n\nAdditionally, in VisitInvokeInterface() LoadConst32() is moved\nto before Jalr(T9) so the load can be taken into the delay slot.\n\nTest: ./testrunner.py --target --optimizing in QEMU\n\nChange-Id: Ic19f251aeba015be38b7d3690e78b2fe59e7c5ae\n" }, { "commit": "59eb30f96d87e3e72a060099a292ae14dd5fe1c8", "tree": "49f9334a44a28eef8d0c35c6061c61743d4db4a8", "parents": [ "5919f737facdebbe8b738272e681ae33e085de98" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Feb 20 11:52:34 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Feb 20 14:27:43 2018 +0000" }, "message": "ART: Clean up patching data in codegens.\n\nReuse PatchInfo\u003c\u003e for additional architectures and make the\nnaming more consistent across architectures. Change the\nDexFile reference to pointer in preparation for patching\nreferences to the upcoming .data.bimg.rel.ro section.\n\nUpdate obsolete comments; instead of referencing dex cache\narrays which were used in the past, reference the .bss and\nthe .data.bimg.rel.ro which shall be used in upcoming CLs.\n\nTest: Rely on TreeHugger.\nChange-Id: I03be4c4118918189e55c62105bb594500c6a42c1\n" }, { "commit": "bdaec34cc04cd21b699c3ad3185dc709ce4d9b4a", "tree": "c7b6dad6ece69d8c5db195e8ab0641d92acc5ebe", "parents": [ "faf76cbe55cc68836513d70b776481030fb2f677", "4b8025c448fa5ab703933de397489e770151300c" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon Feb 12 16:26:32 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Feb 12 16:26:32 2018 +0000" }, "message": "Merge \"MIPS32 Implement signed 64-bit division by powers of 2\"" }, { "commit": "feec1679fa9281f3e18916cbd01216bf6388c6af", "tree": "54b17519484f68be2b5b7575e90507a398e29e3b", "parents": [ "9b9458ae0bd76341b3f444ce27bb5f661188012c" ], "author": { "name": "Goran Jakovljevic", "email": "goran.jakovljevic@mips.com", "time": "Thu Feb 08 10:20:14 2018 +0100" }, "committer": { "name": "Goran Jakovljevic", "email": "goran.jakovljevic@mips.com", "time": "Thu Feb 08 10:20:14 2018 +0100" }, "message": "Add support for counting hotness in compiled code for MIPS\n\nThis is a follow up to I0f63c644527b74f6ef2649f481c2a1c731bb9f21.\nThis fixes 674-hotness-compiled test failures for MIPS32 and MIPS64.\n\nTest: ./testrunner.py --target --optimizing in QEMU\nChange-Id: I22eb02594518f315d9e3a3e5fa895a6833574bba\n" }, { "commit": "6831209ae9a8c73430183feaf045c1ab894990ee", "tree": "fb18f046f7c99338dde332a47927b428c89b2176", "parents": [ "2827ff64c7a385cfb9d6e01e6385708461eb65fc", "dfc30afd459e3b3c9d1af1bc5d08d50df4e6792e" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Feb 02 15:06:23 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Feb 02 15:06:23 2018 +0000" }, "message": "Merge \"MIPS: Clean up InstanceOf/CheckCast.\"" }, { "commit": "66c158ef6b2a16257f1590b3ace78848a7c2407b", "tree": "f17f7eee70aa43711c7eb764c1789f4ec17aef37", "parents": [ "92d0c8b68c24a2fa21f95d63a1ff2fb00fdb9aaf" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Jan 31 12:55:04 2018 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Feb 01 13:26:03 2018 -0800" }, "message": "Clean up signed/unsigned in vectorizer.\n\nRationale:\nCurrently we have some remaining ugliness around signed and unsigned\nSIMD operations due to lack of kUint32 and kUint64 in the HIR. By\n\"softly\" introducing these types, ABS/MIN/MAX/HALVING_ADD/SAD_ACCUMULATE\noperations can solely rely on the packed data types to distinguish\nbetween signed and unsigned operations. Cleaner, and also allows for\nsome code removal in the current loop optimizer.\n\nBug: 72709770\n\nTest: test-art-host test-art-target\nChange-Id: I68e4cdfba325f622a7256adbe649735569cab2a3\n" }, { "commit": "8d728324571b720a952b297787eed70c7a1d1acb", "tree": "f24a774aa56c236f2f756b1b439e4c61830bec56", "parents": [ "0530796b73d0a33a5df27e3a7765c0835994769a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 18 22:44:32 2018 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jan 29 09:34:05 2018 +0000" }, "message": "Add compiler option for counting hotness in compiled code.\n\nFor eventually easier profiling of boot classpath and\nsystem server.\n\nbug: 30934496\nTest: 674-hotness-compiled\n\nChange-Id: I0f63c644527b74f6ef2649f481c2a1c731bb9f21\n" }, { "commit": "dfc30afd459e3b3c9d1af1bc5d08d50df4e6792e", "tree": "f94e9c080ddf1bc8925ea4b29d4643c62afa4868", "parents": [ "5bfcc23d65009e8285acfbe7f7b1e952d94ad0c7" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@mips.com", "time": "Wed Jan 24 16:25:10 2018 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@mips.com", "time": "Thu Jan 25 14:49:30 2018 -0800" }, "message": "MIPS: Clean up InstanceOf/CheckCast.\n\nThis is a MIPS-specific follow-up to\nhttps://android-review.googlesource.com/567637\n\nTest: booted MIPS32R2 in QEMU\nTest: booted MIPS64R6 in QEMU\nTest: ./run-test --optimizing 603-checker-instanceof\n\nChange-Id: Ic5312d98e51aeff11c9f7371be394d5cad319bec\n" }, { "commit": "bff7a52e2c6c9e988c3ed1f12a2da0fa5fd37cfb", "tree": "e281a8dde61e396ed5f20c31d41086b1b1b18389", "parents": [ "83af48e9f4cdfcf3f0069c63561bab4c176bd2f1" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 25 13:33:07 2018 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 25 15:05:16 2018 +0000" }, "message": "Revert \"Compiler changes for bitstring based type checks.\"\n\nBug: 64692057\nBug: 71853552\nBug: 26687569\n\nThis reverts commit eb0ebed72432b3c6b8c7b38f8937d7ba736f4567.\n\nChange-Id: I7daeaa077960ba41b2ed42bc47f17501621be4be\n" }, { "commit": "4b8025c448fa5ab703933de397489e770151300c", "tree": "aeb58faa3a9ce9f51a173bda033bad12e5fef5ac", "parents": [ "b95eb37a04874a57046fba7fc09a8b197691e9a2" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@mips.com", "time": "Thu Dec 21 16:15:50 2017 +0100" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@mips.com", "time": "Thu Jan 25 09:23:26 2018 +0100" }, "message": "MIPS32 Implement signed 64-bit division by powers of 2\n\nTest: ./testrunner.py --target --optimizing in QEMU\n\nChange-Id: I662770eb31d557392588b637f6b03dd5aee96a83\n" }, { "commit": "eb0ebed72432b3c6b8c7b38f8937d7ba736f4567", "tree": "74d95eb4bfbf01ef6fd3a68695f5d7cec69338d7", "parents": [ "e57043081e6b091a9fd23a84043373148ae72f1f" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jan 10 18:26:38 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jan 23 13:02:59 2018 +0000" }, "message": "Compiler changes for bitstring based type checks.\n\nWe guard the use of this feature with a compile-time flag,\nset to true in this CL.\n\nBoot image size for aosp_taimen-userdebug in AOSP master:\n - before:\n arm boot*.oat: 63604740\n arm64 boot*.oat: 74237864\n - after:\n arm boot*.oat: 63531172 (-72KiB, -0.1%)\n arm64 boot*.oat: 74135008 (-100KiB, -0.1%)\n\nThe new TypeCheckBenchmark yields the following changes\nusing the little cores of taimen fixed at 1.4016GHz:\n 32-bit 64-bit\n timeCheckCastLevel1ToLevel1 11.48-\u003e15.80 11.47-\u003e15.78\n timeCheckCastLevel2ToLevel1 15.08-\u003e15.79 15.08-\u003e15.79\n timeCheckCastLevel3ToLevel1 19.01-\u003e15.82 17.94-\u003e15.81\n timeCheckCastLevel9ToLevel1 42.55-\u003e15.79 42.63-\u003e15.81\n timeCheckCastLevel9ToLevel2 39.70-\u003e14.36 39.70-\u003e14.35\n timeInstanceOfLevel1ToLevel1 13.74-\u003e17.93 13.76-\u003e17.95\n timeInstanceOfLevel2ToLevel1 17.02-\u003e17.95 16.99-\u003e17.93\n timeInstanceOfLevel3ToLevel1 24.03-\u003e17.95 24.45-\u003e17.95\n timeInstanceOfLevel9ToLevel1 47.13-\u003e17.95 47.14-\u003e18.00\n timeInstanceOfLevel9ToLevel2 44.19-\u003e16.52 44.27-\u003e16.51\nThis suggests that the bitstring typecheck should not be\nused for exact type checks which would be equivalent to the\n\"Level1ToLevel1\" benchmark. Whether the implementation is\na beneficial replacement for the kClassHierarchyCheck and\nkAbstractClassCheck on average depends on how many levels\nfrom the target class (or Object for a negative result) is\na typical object\u0027s class.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: testrunner.py --host -t 670-bitstring-type-check\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --jit\nTest: testrunner.py --target -t 670-bitstring-type-check\nBug: 64692057\nBug: 71853552\nBug: 26687569\nChange-Id: I538d7e036b5a8ae2cc3fe77662a5903d74854562\n" }, { "commit": "a8b8e9b12a9740d71cff2fa65d47825b74f72c37", "tree": "301275759cf145711175992a503fcc7d710c2d2f", "parents": [ "6d4c343ee5db18f039aeb3e07ff8d3c1fd37c3a0" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Jan 09 11:01:02 2018 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Jan 16 09:44:28 2018 -0800" }, "message": "Improve code sinking near \"always throwing\" method calls\n\nRationale:\nWith simple dex bytecode analysis, the inliner marks methods\nthat always throw to help subsequent code sinking. This reduces\noverhead of non-nullable enforcing calls found in e.g the Kotlin\nruntime library (1%-2% improvement on tree microbenchmark, about\n5% on Denis\u0027 benchmark).\n\nTest: test-art-host test-art-target\n\nChange-Id: I45348f049721476828eb5443738021720d2857c0\n" }, { "commit": "dc682aa9d0eae1a851af059434adb6f6cf8f06f8", "tree": "f93f00493ee5887b05b42a6a5dd99eb6794daad4", "parents": [ "d6b7e8c63f8eca25460f56f66dcae15eaa897ff0" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jan 04 18:42:57 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jan 10 14:30:26 2018 +0000" }, "message": "Use 28 bits for type check bit string.\n\nAnd reverse the order of fields in the Class::status_. This\navoids generated code size increase:\n - ClassStatus in high bits allows class initialization\n check using \"status_high_byte \u003c (kInitialized \u003c\u003c 4)\"\n which is unaffected by the low 4 bits of LHS instead of\n needing to extract the status bits,\n - the type check bit string in the bottom bits instead of\n somewehere in the middle allows the comparison on ARM\n to be done using the same code size as with the old\n layout in most cases (except when the compared value is\n 9-16 bits and not a modified immediate: 2 bytes less for\n 9-12 bits and sometimes 2 bytes more for 13-16 bits; the\n latter could be worked around using LDRH if the second\n character\u0027s boundary is at 16 bits).\n\nAdd one of the extra bits to the 2nd character to push its\nboundary to 16 bits so that we can test an implementation\nusing 16-bit loads in a subsequent CL, arbitrarily add the\nother three bits to the 3rd character. This CL is only\nabout making those bits available and allowing testing, the\ndetermination of how to use the additonal bits for the best\nimpact (whether to have a 4th character or distribute them\ndifferently among the three characters) shall be done later.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nBug: 64692057\nChange-Id: I38c59837e3df3accb813fb1e04dc42e9afcd2d73\n" }, { "commit": "2c64a837e62c2839521c89060b5bb0dcb237ddda", "tree": "65475ed2e313ff17354e741bac7e9c85739b8b95", "parents": [ "6cd0005698181e4cef2247b632d396e605d58fa3" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jan 04 11:31:56 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jan 05 11:27:50 2018 +0000" }, "message": "Change ClassStatus to fit into 4 bits.\n\nIn preparation for extending the type check bit string from\n24 to 28 bits, rewrite ClassStatus to fit into 4 bits. Also\nperform a proper cleanup of the ClassStatus, i.e. change it\nto an enum class, remove the \"Status\" word from enumerator\nnames, replace \"Max\" with \"Last\" in line with other\nenumerations and remove aliases from mirror::Class.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nBug: 64692057\nBug: 65318848\nChange-Id: Iec1610ba5dac2c527b36c12819f132e1a77f2d45\n" }, { "commit": "a556e6ba500ba54d1ca90d6a947dd962d9c287c7", "tree": "f9e747c6218ca741c7b0783a9d10dedf22dd36b3", "parents": [ "b0ddceb337f614dc2600d19b82fb4a6596aa7d4c" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@mips.com", "time": "Wed Dec 13 12:09:42 2017 +0100" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@mips.com", "time": "Wed Jan 03 17:40:01 2018 +0100" }, "message": "MIPS: InstructionCodeGeneratorMIPS*::DivRemByPowerOfTwo()\n\nReplace [d]sll+[d]srl with [d]ins on R2+.\n\nChange-Id: I7587e46c47c8ce413d81a5c6c29d91e32a14d855\n" }, { "commit": "e7de5ec3e4cd1d607b647d98ea64df105479b867", "tree": "d692c4d1dee08eea4beffd71bd8cdf1d106c059e", "parents": [ "bee510c94560703102ca553a08ec47119959c204" ], "author": { "name": "Goran Jakovljevic", "email": "goran.jakovljevic@mips.com", "time": "Thu Dec 14 10:25:20 2017 +0100" }, "committer": { "name": "Goran Jakovljevic", "email": "goran.jakovljevic@mips.com", "time": "Fri Dec 15 17:33:12 2017 +0100" }, "message": "MIPS: Support swaps between 128-bit locations\n\nAdd support for swaps between two SIMDStackSlots, two\nVectorRegisters (extended FpuRegister) and between a\nSIMDStackSlot and a VectorRegister.\n\nThis fixes test 623-checker-loop-regressions for\nMIPS64R6 and MIPS32R6.\n\nTest: ./testrunner.py --optimizing --target in QEMU (MIPS64R6)\nTest: ./testrunner.py --optimizing --target in QEMU (MIPS32R6)\n\nChange-Id: I36aa209f79790fb6c08b9a171f810769a6b40afc\n" }, { "commit": "3853017d05d5395250882c68482d8168a0392391", "tree": "a591eb83627e99a4d92108f26dd42629a1ebc360", "parents": [ "c5bf424c340e5610f6677b1ca0a2ae27df43d0d9" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@mips.com", "time": "Thu Nov 16 11:11:50 2017 +0100" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@mips.com", "time": "Mon Dec 04 11:47:18 2017 +0100" }, "message": "MIPS: Improve HandleBinaryOp (Add/Sub) for constant inputs\n\nTest: ./testrunner.py --optimizing --target\nChange-Id: I35154a85f16b4f46d3b4d5827b130b1e20153461\n" }, { "commit": "dbd4303b0da3bd30f53479c14ef541441c8d01f7", "tree": "30f71b12c47f9f148cd694dffdd0efe248aaf1d0", "parents": [ "d40e416f329fa7d7a3ad9cf1bcfbc5eb8137cbc4" ], "author": { "name": "Goran Jakovljevic", "email": "goran.jakovljevic@mips.com", "time": "Wed Nov 15 16:31:56 2017 +0100" }, "committer": { "name": "Goran Jakovljevic", "email": "goran.jakovljevic@mips.com", "time": "Fri Dec 01 17:46:04 2017 +0100" }, "message": "MIPS: Improve BoundsCheck for constant inputs\n\nNote: All tests were executed on CI20 (MIPS32R2) and in\n QEMU (MIPS32R6 and MIPS64R6).\n\nTest: ./testrunner.py --optimizing --target\nTest: mma test-art-target-gtest\n\nChange-Id: I012fb1013af43d5669a9b0080d481da28ffa7ef2\n" }, { "commit": "f3c52b42a035902245d00a619fed0275afb063d2", "tree": "c46dab07826be55e9ca92ab301eed586c2f307ca", "parents": [ "b360bff818ad0bf59668cd2bebaaeeaa8a3b5dfe" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Nov 17 17:32:12 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Nov 21 17:09:44 2017 +0000" }, "message": "Fill Class and String .bss slots in runtime.\n\nShift the responsibility for filling Class and String .bss\nslots from compiled code to runtime. This reduces the size\nof the compiled code.\n\nMake oatdump list .bss slot mappings (ArtMethod, Class and\nString) for each dex file.\n\naosp_taimen-userdebug boot image size:\n - before:\n arm boot*.oat: 36534524\n arm64 boot*.oat: 42723256\n - after:\n arm boot*.oat: 36431448 (-101KiB, -0.3%)\n arm64 boot*.oat: 42645016 (-76KiB, -0.2%)\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nTest: m dump-oat, manually inspect output.\nBug: 65737953\nChange-Id: I1330d070307410107e12c309d4c7f8121baba83c\n" }, { "commit": "3e5fecdeacdacf847d376adb05a9ad5587648139", "tree": "5a846ea9547a03a0aa52197058c7fdb5e922c0f6", "parents": [ "2202d56061941b4fecbdb018d84bcefb05b6c683" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@mips.com", "time": "Thu Nov 09 14:21:28 2017 -0800" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@mips.com", "time": "Thu Nov 09 14:24:37 2017 -0800" }, "message": "MIPS32: Use conditional moves to compute 64-bit shifts.\n\nUse conditional moves in\nInstructionCodeGeneratorMIPS::HandleShift()\u0027s 64-bit variable\nshifts to avoid conditional branches (Beqz(TMP, \u0026done)).\n\nAlso, on R6 use Beqzc(TMP, \u0026done, /* is_bare */ true) in place of\nBeqz(TMP, \u0026done).\n\nTest: Boot \u0026 run tests on MIPS32r6 QEMU \u0026 on CI-20 hardware (MIPS32r2).\nTest: test/testrunner/testrunner.py --target --optimizing\n\nChange-Id: I4d34a51cd2397c845f936af853cb5f30e82de438\n" }, { "commit": "cefd676fb79d225fcd7e8e8c0ef141d70a2f45b8", "tree": "be625fa0bc1255cbea5c5066dd878fb0b2a1c454", "parents": [ "dbc26ad5e8ded15688d20a39344c677077311279", "86083f7cd118f3d6c757191e83b4e4abaabdc5d7" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Wed Nov 08 03:26:30 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Nov 08 03:26:30 2017 +0000" }, "message": "Merge \"runtime: Bitstring implementation for subtype checking (4/4).\"" }, { "commit": "86083f7cd118f3d6c757191e83b4e4abaabdc5d7", "tree": "8e5b81ae0d09d41bfd90284a1b6b16b2332435e5", "parents": [ "495e783c9180c3fc033ce459ee0a783e633f7754" ], "author": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Fri Oct 27 10:59:04 2017 -0700" }, "committer": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Tue Nov 07 14:47:51 2017 -0800" }, "message": "runtime: Bitstring implementation for subtype checking (4/4).\n\nIntegrate the previous CLs into ART Runtime. Subsequent CLs to add\noptimizing compiler support.\n\nUse spare 24-bits from \"Class#status_\" field to\nimplement faster subtype checking in the runtime. Does not incur any extra memory overhead,\nand (when in compiled code) this is always as fast or faster than the original check.\n\nThe new subtype checking is O(1) of the form:\n\n src \u003c: target :\u003d\n (*src).status \u003e\u003e #imm_target_mask \u003d\u003d #imm_target_shifted\n\nBased on the original prototype CL by Zhengkai Wu:\nhttps://android-review.googlesource.com/#/c/platform/art/+/440996/\n\nTest: art/test.py -b -j32 --host\nBug: 64692057\nChange-Id: Iec3c54af529055a7f6147eebe5611d9ecd46942b\n" }, { "commit": "ea604b2a0e2e08c757e509879f6699df8945449d", "tree": "9fa1300027a848db5a1af2c9c432851052a8bc60", "parents": [ "71976e21f12d5886990eb40747dbdee778e31fc1", "a204591b4537141aa6b0fa01f81cc03d92a90456" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon Nov 06 12:02:23 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Nov 06 12:02:23 2017 +0000" }, "message": "Merge \"MIPS: Improve InstructionCodeGeneratorMIPS*::GenerateSuspendCheck().\"" }, { "commit": "a204591b4537141aa6b0fa01f81cc03d92a90456", "tree": "2f08659b74a1c3f76d47fd061837622394f28dd0", "parents": [ "a4d89d9bb911f7f3d0a6e4d3b45372e0aea6476d" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@mips.com", "time": "Thu Nov 02 12:39:54 2017 -0700" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@mips.com", "time": "Fri Nov 03 11:18:47 2017 -0700" }, "message": "MIPS: Improve InstructionCodeGeneratorMIPS*::GenerateSuspendCheck().\n\nRelax the only back-edge restriction. Implement optimization for\nMIPS32/MIPS64 which has already been done for the ARM \u0026 x86\narchitectures in\nhttps://android-review.googlesource.com/#/c/platform/art/+/149370/.\n\nTest: Boot \u0026 run tests on 32- \u0026 64-bit version of QEMU.\nTest: test/testrunner/testrunner.py --target --optimizing\nTest: test-art-host-gtest\nTest: test-art-target-gtest\n\nChange-Id: Ie0a4c19ee50ad532fe53933d5808f9d7a4f89b8e\n" }, { "commit": "72627a5f675b1c664beb2ad33d60a1c8dca80826", "tree": "03c363a13cfff3e7c7e9feb158cb2ba56c97ff8e", "parents": [ "ab13432123bc22c997f9dbb12596f05ce782561a", "e0eb48353ddf0c1b79bfec2ba15c899a413c2c70" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Nov 03 10:16:38 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Nov 03 10:16:38 2017 +0000" }, "message": "Merge \"Fix LSA hunt for original reference bug.\"" }, { "commit": "e0eb48353ddf0c1b79bfec2ba15c899a413c2c70", "tree": "71dfe896afa05c39d64373518d1e1e36cb8d8d43", "parents": [ "3e6c13997373efac343a65740da0c4f6e77338b9" ], "author": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Mon Oct 30 13:43:14 2017 +0000" }, "committer": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Thu Nov 02 16:17:17 2017 +0000" }, "message": "Fix LSA hunt for original reference bug.\n\nFix a bug in LSA where it doesn\u0027t take IntermediateAddress\ninto account during hunting for original reference.\n\nIn following example, original reference i0 can be transformed\nby NullCheck, BoundType, IntermediateAddress, etc.\n i0 NewArray\n i1 HInstruction(i0)\n i2 ArrayGet(i1, index)\n\nTest: test-art-host\nTest: test-art-target\nTest: load_store_analysis_test\nTest: 706-checker-scheduler\n\nChange-Id: I162dd8a86fcd31daee3517357c6af638c950b31b\n" }, { "commit": "33bff25bcd7a02d35c54f63740eadb1a4833fc92", "tree": "553db4f60878acf2a0fa7036a739d406df9a29b7", "parents": [ "321b3ca9a36d769283c64d4bdee0798db80af524" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Nov 01 14:35:42 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Nov 02 10:11:02 2017 +0000" }, "message": "ART: Make InstructionSet an enum class and add kLast.\n\nAdding InstructionSet::kLast shall make it easier to encode\nthe InstructionSet in fewer bits using BitField\u003c\u003e. However,\nintroducing `kLast` into the `art` namespace is not a good\nidea, so we change the InstructionSet to an enum class.\nThis also uncovered a case of InstructionSet::kNone being\nerroneously used instead of vixl32::Condition::None(), so\nit\u0027s good to remove `kNone` from the `art` namespace.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nChange-Id: I6fa6168dfba4ed6da86d021a69c80224f09997a6\n" }, { "commit": "715f43e1553330bc804cea2951be195473dc343d", "tree": "55e143005efe10e8448c91eff6b88a635af2a3f6", "parents": [ "9e842d3e7d6102d964178e36e5d596ca91895147" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Mon Oct 23 11:00:32 2017 -0700" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Mon Oct 23 11:00:32 2017 -0700" }, "message": "MIPS32: Improve stack alignment, use sdc1/ldc1, where possible.\n\n- Ensure that SP is a multiple of 16 at all times, and\n- Use ldc1/sdc1 to load/store FPU registers from/to 8-byte-aligned\n locations wherever possible.\n\nUse `export ART_MIPS32_CHECK_ALIGNMENT\u003dtrue` when building Android\nto enable the new runtime alignment checks.\n\nTest: Boot \u0026 run tests on 32-bit version of QEMU, and CI-20.\nTest: test/testrunner/testrunner.py --target --optimizing --32\nTest: test-art-host-gtest\nTest: test-art-target-gtest\n\nChange-Id: Ia667004573f419fd006098fcfadf5834239cb485\n" }, { "commit": "2e61a57988a9172d446a1638bbd61d94c86ed4d9", "tree": "d39b3405dcfadeb19e2c8cf64c082e2b9a693013", "parents": [ "59c5dfe792d3288c5df75a035f6614cb228d7352" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Mon Oct 23 08:58:15 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Mon Oct 23 08:58:15 2017 +0200" }, "message": "MIPS32: Do implicit null check properly\n\nThis fixes 122-npe test failure in debuggable mode for MIPS32.\n\nTest: ./testrunner.py --target --optimizing --debuggable --ndebuggable on CI20\nChange-Id: I7c5c1e72a92f29e750265b612079ab0bac2a1dc0\n" }, { "commit": "96b7474ebf313abdaf99e657e4ba9758e2467fb1", "tree": "175c7a007ef033c3fccc1e74da2e4424e74da336", "parents": [ "6247604714ae7fb2b64451b225cc0ecd3d4b716f", "174b2e27ebf933b80f4e8b64b4b024ab4306aaac" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 20 10:31:25 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Oct 20 10:31:25 2017 +0000" }, "message": "Merge \"Use ScopedArenaAllocator for code generation.\"" }, { "commit": "b277aa1385f7f4593c9978d8106669142d158f4f", "tree": "02b4919913ca6193db721f486062b949efb1fbfc", "parents": [ "dfce43569a32ed7da881796713647cd8051d0d4e", "61b922847403ac0e74b6477114c81a28ac2e01a0" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 19 09:21:21 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Oct 19 09:21:21 2017 +0000" }, "message": "Merge \"ART: Introduce Uint8 loads in compiled code.\"" }, { "commit": "61b922847403ac0e74b6477114c81a28ac2e01a0", "tree": "02674602fb2592f758f51389b3c7b276ab4df3ee", "parents": [ "6783118d2ad9d759f0617b1219a9e29a10a569f7" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 11 13:23:17 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 18 15:52:51 2017 +0100" }, "message": "ART: Introduce Uint8 loads in compiled code.\n\nSome vectorization patterns are not recognized anymore.\nThis shall be fixed later.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: testrunner.py --target --optimizing on Nexus 5X\nTest: Nexus 5X boots.\nBug: 23964345\nBug: 67935418\nChange-Id: I587a328d4799529949c86fa8045c6df21e3a8617\n" }, { "commit": "174b2e27ebf933b80f4e8b64b4b024ab4306aaac", "tree": "968cdd8d7fd68571115db77cc288807c3b257911", "parents": [ "6783118d2ad9d759f0617b1219a9e29a10a569f7" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 12 13:34:49 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Oct 17 11:12:08 2017 +0100" }, "message": "Use ScopedArenaAllocator for code generation.\n\nReuse the memory previously allocated on the ArenaStack by\noptimization passes.\n\nThis CL handles only the architecture-independent codegen\nand slow paths, architecture-dependent codegen allocations\nshall be moved to the ScopedArenaAllocator in a follow-up.\n\nMemory needed to compile the two most expensive methods for\naosp_angler-userdebug boot image:\n BatteryStats.dumpCheckinLocked() : 19.6MiB -\u003e 18.5MiB (-1189KiB)\n BatteryStats.dumpLocked(): 39.3MiB -\u003e 37.0MiB (-2379KiB)\n\nAlso move definitions of functions that use bit_vector-inl.h\nfrom bit_vector.h also to bit_vector-inl.h .\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nBug: 64312607\nChange-Id: I84688c3a5a95bf90f56bd3a150bc31fedc95f29c\n" }, { "commit": "3b8c82f4864624da8a1efd09f02bfec754413a20", "tree": "175a5835f4f62f539b5ae457a9e62ec3dcb91d13", "parents": [ "26d46e51a8c387d26e7971857e26f4582b936204" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Oct 10 23:01:34 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Oct 16 17:06:21 2017 -0700" }, "message": "MIPS32R2: Enable table-based switch in presence of irreducible loops\n\nTest: test-art-host-gtest\nTest: booted MIPS32R2 in QEMU\nTest: testrunner.py --target --optimizing --32\nTest: repeat all of the above with suppressed generation\n of HMipsPackedSwitch\n\nChange-Id: Ic8a27d88cd2d7eebaf5826ce8fd1a5607a024844\n" }, { "commit": "bea75ff0835324076fed6ff5d443b9e02c65d223", "tree": "61ae2e8fe552938fcae1e277f51823ba2a4f6e74", "parents": [ "567563a9c6ccc06c2c9889d1c3c4feaa3c2b2dab" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 11 20:39:54 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 12 10:58:02 2017 +0100" }, "message": "Fix using LiveIntervals beyond their lifetime.\n\nFixes a bug introduced by\n https://android-review.googlesource.com/504041\n\nTest: test-art-host-gtest\nTest: testrunner.py --host --optimizing\nBug: 64312607\nChange-Id: I7fd2d55c2a657f736eaed7c94c41d1237ae2ec0b\n" }, { "commit": "ca6fff898afcb62491458ae8bcd428bfb3043da1", "tree": "195a6b16d3a4b34acc2faf91ce56f448efb15e07", "parents": [ "aa7273e56fbafc2692c8d20a31b50d2f4bdd2aa1" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Oct 03 14:49:14 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 06 17:53:50 2017 +0100" }, "message": "ART: Use ScopedArenaAllocator for pass-local data.\n\nPasses using local ArenaAllocator were hiding their memory\nusage from the allocation counting, making it difficult to\ntrack down where memory was used. Using ScopedArenaAllocator\nreveals the memory usage.\n\nThis changes the HGraph constructor which requires a lot of\nchanges in tests. Refactor these tests to limit the amount\nof work needed the next time we change that constructor.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: Build with kArenaAllocatorCountAllocations \u003d true.\nBug: 64312607\nChange-Id: I34939e4086b500d6e827ff3ef2211d1a421ac91a\n" }, { "commit": "a290160f74ee53c0ffb51c7b3ac916d239c9556a", "tree": "0bfc9728ccee68dbd359b023319423f703448aac", "parents": [ "86d244ec33f333b32301a9ee09088300c8544a7b" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Thu Sep 21 13:50:52 2017 +0200" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Thu Oct 05 11:43:34 2017 +0200" }, "message": "MIPS32R2: Share address computation\n\nFor array accesses the element address has the following structure:\nAddress \u003d CONST_OFFSET + base_addr + index \u003c\u003c ELEM_SHIFT\n\nThe address part (index \u003c\u003c ELEM_SHIFT) can be shared across array\naccesses with the same data type and index.\n\nFor example, in the following loop 5 accesses can share address\ncomputation:\n\nvoid foo(int[] a, int[] b, int[] c) {\n for (i...) {\n a[i] \u003d a[i] + 5;\n b[i] \u003d b[i] + c[i];\n }\n}\n\nTest: test-art-host, test-art-target\nChange-Id: Id09fa782934aad4ee47669275e7e1a4d7d23b0fa\n" }, { "commit": "d5d2f2ce627aa0f6920d7ae05197abd1a396e035", "tree": "e8e780780c832e3614a22438a23fb60ee4960ca3", "parents": [ "efac0df8c738764823c637deeca1f3be33912064" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Sep 26 12:37:26 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Oct 03 10:40:51 2017 +0100" }, "message": "ART: Introduce Uint8 compiler data type.\n\nThis CL adds all the necessary codegen for the Uint8 type\nbut does not add code transformations that use that code.\nVectorization codegens are modified to use Uint8 as the\npacked type when appropriate. The side effects are now\ndisconnected from the instruction\u0027s type after the graph has\nbeen built to allow changing HArrayGet/H*FieldGet/HVecLoad\nto use a type different from the underlying field or array.\n\nNote: HArrayGet for String.charAt() is modified to have\nno side effects whatsoever; Strings are immutable.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: testrunner.py --target --optimizing on Nexus 6P\nTest: Nexus 6P boots.\nBug: 23964345\nChange-Id: If2dfffedcfb1f50db24570a1e9bd517b3f17bfd0\n" }, { "commit": "0ebe0d83138bba1996e9c8007969b5381d972b32", "tree": "a5ee66ebc5b587ade97e56ac8fc7d832fbbed4af", "parents": [ "e1e347dace0ded83774999bb26c37527dcdb1d5a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Sep 21 22:50:39 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Sep 25 15:45:01 2017 +0100" }, "message": "ART: Introduce compiler data type.\n\nReplace most uses of the runtime\u0027s Primitive in compiler\nwith a new class DataType. This prepares for introducing\nnew types, such as Uint8, that the runtime does not need\nto know about.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nBug: 23964345\nChange-Id: Iec2ad82454eec678fffcd8279a9746b90feb9b0c\n" }, { "commit": "994cfb3d1595e28b61b8831264c5fc0ebdb6d156", "tree": "701912858cd2e6cca5bae653fcab37d9afb2e0c2", "parents": [ "478abf08c6d2a95eef12e78d3b12857917a91872", "debb510e34b844cc6d80d0304db34c7530fbaf44" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Sep 21 21:29:42 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Sep 21 21:29:42 2017 +0000" }, "message": "Merge \"MIPS32R2: Allow all kinds of class/string loads and invokes\"" }, { "commit": "debb510e34b844cc6d80d0304db34c7530fbaf44", "tree": "d54afd723f4477a67a5aaef4eb1f639794fd75fe", "parents": [ "5402edd0630cb6f30d98ff712ed914eadce6586c" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Sep 21 14:24:06 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Sep 21 14:24:06 2017 +0200" }, "message": "MIPS32R2: Allow all kinds of class/string loads and invokes\n\nForce generating nal instruction before PC-relative addressing in the\npresence of irreducible loops (HMipsComputeBaseMethodAddress is not\nused in those situations).\n\nThis patch fixes a lot of JIT tests failures.\n\nTest: ./testrunner.py --target --optimizing --jit (CI20 and QEMU)\nTest: mma test-art-target-gtest (CI20 and QEMU)\n\nChange-Id: I1815a6bb5783f439c8263612abff557f797bfef1\n" }, { "commit": "d8dbc8da0e5cc6b5c2176ce2d3877e6194d72c0c", "tree": "af6e9fb02471d75ebdea46190a0aa3e9dbdb892d", "parents": [ "93780a60090356921b844dbefdc13442c9f18b52" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 20 13:37:47 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 20 15:55:10 2017 +0100" }, "message": "Refactor compiled_method.h .\n\nMove LinkerPatch to compiler/linker/linker_patch.h .\nMove SrcMapElem to compiler/debug/src_map_elem.h .\nIntroduce compiled_method-inl.h to reduce the number\nof `#include`s in compiled_method.h .\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nChange-Id: Id211cdf94a63ad265bf4709f1a5e06dffbe30f64\n" }, { "commit": "09659c22dc2f2c85a0ade965d1fc5160944b8692", "tree": "66fd5729395d27569c4d9d255a5ce9b44cb000bf", "parents": [ "4d159807a4854caa6396b708a38bbd6fa49d736f" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Sep 18 18:23:32 2017 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Sep 19 10:26:51 2017 -0700" }, "message": "ART: Remove heap poisoning from globals.h\n\nRemove mostly-unused include and move it to its users.\n\nTest: m\nChange-Id: Ibb40f919db64a490290c6e18cf1123aaf44199fc\n" }, { "commit": "fc8b422c286501346b5b797420fb616aaa5e952a", "tree": "61c857a895cdad9ce387a899f92824701259df32", "parents": [ "7090dfe84f78b1928fcbdfd664d0dd9ea52633ff" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Sun Sep 17 13:44:24 2017 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Mon Sep 18 10:57:06 2017 -0700" }, "message": "Clean up AtomicDexRefMap\n\nMake ClassReference, TypeReference, and MethodReference extend\nDexFileReference. This enables using all of these types as the key\nfor AtomicDexRefMap.\n\nTest: test-art-host\nBug: 63851220\nBug: 63756964\n\nChange-Id: Ida3c94cadb53272cb5057e5cebc5971c1ab4d366\n" }, { "commit": "94ec2db21332ee1dcdbbf254b99a9a999a304fe0", "tree": "6ced7e596731b61f95a3693f336527f55ea3cf3a", "parents": [ "6cfbdbc359ec5414d3e49f70d28f8c0e65b98d63" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 06 17:21:03 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Sep 11 15:12:51 2017 +0100" }, "message": "Use mmapped boot image class table for PIC app HLoadClass.\n\nImplement new HLoadClass load kind for boot image classes\nreferenced by PIC-compiled apps (i.e. prebuilts) that uses\nPC-relative load from a boot image ClassTable mmapped into\nthe apps .bss. This reduces the size of the PIC prebuilts\nthat reference boot image classes compared to the kBssEntry\nas we can completely avoid the slow path and stack map\nunless we need to do the class initialization check.\n\nPrebuilt services.odex for aosp_angler-userdebug (arm64):\n - before: 20312800\n - after: 19775352 (-525KiB)\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: testrunner.py --host --pictest\nTest: testrunner.py --target on Nexus 6P.\nTest: testrunner.py --target --pictest on Nexus 6P.\nTest: Nexus 6P boots.\nBug: 31951624\nChange-Id: I13adb19a1fa7d095a72a41f09daa6101876e77a8\n" }, { "commit": "6cfbdbc359ec5414d3e49f70d28f8c0e65b98d63", "tree": "f92b309ddc43c2254b6067346a653170fbbf7316", "parents": [ "0f3c7003e08a42a4ed8c9f8dfffb1bee1118de59" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 25 13:26:39 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Sep 07 17:52:35 2017 +0100" }, "message": "Use mmapped boot image intern table for PIC app HLoadString.\n\nImplement new HLoadString load kind for boot image strings\nreferenced by PIC-compiled apps (i.e. prebuilts) that uses\nPC-relative load from a boot image InternTable mmapped into\nthe apps .bss. This reduces the size of the PIC prebuilts\nthat reference boot image strings compared to the kBssEntry\nas we can completely avoid the slow path and stack map.\n\nWe separate the InternedStrings and ClassTable sections of\nthe boot image (.art) file from the rest, aligning the\nstart of the InternedStrings section to a page boundary.\nThis may actually increase the size of the boot image file\nby a page but it also allows mprotecting() these tables as\nread-only. The ClassTable section is included in\nanticipation of a similar load kind for HLoadClass.\n\nPrebuilt services.odex for aosp_angler-userdebug (arm64):\n - before: 20862776\n - after: 20308512 (-541KiB)\nNote that 92KiB savings could have been achieved by simply\navoiding the read barrier, similar to the HLoadClass flag\nIsInBootImage(). Such flag is now unnecessary.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: testrunner.py --host --pictest\nTest: testrunner.py --target on Nexus 6P.\nTest: testrunner.py --target --pictest on Nexus 6P.\nTest: Nexus 6P boots.\nBug: 31951624\nChange-Id: I5f2bf1fc0bb36a8483244317cfdfa69e192ef6c5\n" }, { "commit": "a663d9d5b32a525794a2b98fa43da54dd7c79e3b", "tree": "88c643ca5ebfb0dfe11f45a9b232f9a2592fb043", "parents": [ "b9463674919ba91fe131e65785ad67b4202e86b9" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Jul 31 18:43:18 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Fri Aug 18 15:29:31 2017 -0700" }, "message": "MIPS32: Allow some patched instructions in delay slots\n\nTest: test-art-host-gtest\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-gtest32\nTest: testrunner.py --target --optimizing --32\nTest: same tests as above on CI20\nTest: booted MIPS32R2 in QEMU\n\nChange-Id: I7e1ba59993008014d0115ae20c56e0a71fef0fb0\n" }, { "commit": "0cab65610a6a984a94ef4c3f232fe0273e78d95b", "tree": "669fa607f4cd9ad8eef9223bb124fb72265a06b3", "parents": [ "2e53f8f69f8c4175085e337445ec42aa045a2f7f" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Jul 25 15:19:36 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sun Jul 30 20:09:26 2017 -0700" }, "message": "MIPS: Eliminate hard-coded offsets in branches\n\nThe bulk of the change is in the assemblers and their\ntests.\n\nThe main goal is to introduce \"bare\" branches to labels\n(as opposed to the existing bare branches with relative\noffsets, whose direct use we want to eliminate).\nThese branches\u0027 delay/forbidden slots are filled\nmanually and these branches do not promote to long (the\nbranch target must be within reach of the individual\nbranch instruction).\n\nThe secondary goal is to add more branch tests (mainly\nfor bare vs non-bare branches and a few extra) and\nrefactor and reorganize the branch test code a bit.\n\nThe third goal is to improve idiom recognition in the\ndisassembler, including branch idioms and a few others.\n\nFurther details:\n- introduce bare branches (R2 and R6) to labels, making\n R2 branches available for use on R6\n- make use of the above in the code generators\n- align beqz/bnez with their GNU assembler encoding to\n simplify and shorten the test code\n- update the CFI test because of the above\n- add trivial tests for bare and non-bare branches\n (addressing existing debt as well)\n- add MIPS32R6 tests for long beqc/beqzc/bc (debt)\n- add MIPS64R6 long beqzc test (debt)\n- group branch tests together\n- group constant/literal/address-loading tests together\n- make the disassembler recognize:\n - b/beqz/bnez (beq/bne with $zero reg)\n - nal (bltzal with $zero reg)\n - bal/bgezal (bal \u003d bgezal with $zero reg)\n - move (or with $zero reg)\n - li (ori/addiu with $zero reg)\n - dli (daddiu with $zero reg)\n- disassemble 16-bit immediate operands (in andi, ori,\n xori, li, dli) as signed or unsigned as appropriate\n- drop unused instructions (bltzl, bltzall, addi) from\n the disassembler as there are no plans to use them\n\nTest: test-art-host-gtest\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-gtest\nTest: testrunner.py --target --optimizing\nTest: same tests as above on CI20\nTest: booted MIPS32R2 in QEMU\n\nChange-Id: I62b74a6c00ce0651528114806ba24a59ba564a73\n" }, { "commit": "4147fcc43c2ee019a06e55384985e3eaf82dcb8c", "tree": "11ec92efbfddf7736bbc74ed35fcfb3756bfcfb0", "parents": [ "e8f48da635c4d07bbe431e5819da8e1fad91a8ef" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sat Jun 17 19:57:27 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Jul 19 15:03:10 2017 -0700" }, "message": "MIPS: Reduce Baker read barrier code size overhead\n\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-gtest\nTest: testrunner.py --target --optimizing\nTest: same tests as above on CI20\nTest: booted MIPS32 and MIPS64 in QEMU with poisoning\n in configurations:\n - with Baker read barrier thunks\n - without Baker read barrier thunks\n - ART_READ_BARRIER_TYPE\u003dTABLELOOKUP\n\nChange-Id: I79f320bf8862a04215c76cfeff3118ebc87f7ef2\n" }, { "commit": "854df416f12c48b52239fe163ab8a7fcac4cddd3", "tree": "f5cf247f1e71a5242c797b8fab99ded21839267d", "parents": [ "e63a91111d13f33028c2988ded53a4659140ca2e" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Tue Jun 27 14:41:39 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Jul 13 10:17:07 2017 +0200" }, "message": "MIPS: TLAB allocation entrypoints\n\nAdd fast paths for TLAB allocation entrypoints for MIPS32 and MIPS64.\nAlso improve rosalloc entrypoints.\n\nNote: All tests are executed on CI20 (MIPS32R2) and in QEMU (MIPS32R6\n and MIPS64R6), with and without ART_TEST_DEBUG_GC\u003dtrue.\n\nTest: ./testrunner.py --optimizing --target\nTest: mma test-art-target-gtest\nTest: mma test-art-host-gtest\n\nChange-Id: I92195d2d318b26a19afc5ac46a1844b13b2d5191\n" }, { "commit": "97c46466aea25ab63a99b3d1afc558f0d9f55abb", "tree": "afd225f51d28a77329bc2590a025400e088f260c", "parents": [ "00cca3a275562d110a8b35094b9b12fac37f67ab" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu May 11 14:04:03 2017 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jul 11 17:43:27 2017 +0100" }, "message": "Introduce a Marking Register in ARM64 code generation.\n\nWhen generating code for ARM64, maintain the status of\nThread::Current()-\u003eGetIsGcMarking() in register X20,\ndubbed MR (Marking Register), and check the value of that\nregister (instead of loading and checking a read barrier\nmarking entrypoint) in read barriers.\n\nTest: m test-art-target\nTest: m test-art-target with tree built with ART_USE_READ_BARRIER\u003dfalse\nTest: ARM64 device boot test\nBug: 37707231\nChange-Id: Ibe9bc5c99a2176b0a0476e9e9ad7fcc9f745017b\n" }, { "commit": "ca8c2951ea25e8f93eea9decc70d81937b4361dd", "tree": "72c811abe58895b4972cd88ee267c8ca66155fd1", "parents": [ "2e0a7e5047fde08ddd220aaa1a0e64d44ecbb420" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Mon May 29 11:31:46 2017 +0200" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Thu Jul 06 14:06:33 2017 +0200" }, "message": "MIPS32: Saves 128-bit vector registers along SuspendCheckSlowPath\n\nWe need to save 128 bits of data. This is only done for vector\nregisters that are live, so overhead is not too big.\n\nTest: mma test-art-host-gtest\nTest: ./testrunner.py --optimizing --target in QEMU (MIPS)\nChange-Id: I0f792e9c98011be3e24d5fad35a8244faafcb9a0\n" }, { "commit": "8091ed8a26db4609c719ea8d905145ddfed7f498", "tree": "342d4459e8e9c61af7b69fc2ac2e0512592cf9f4", "parents": [ "61cfb15e2588ff1fe3c80efbfcf55973122b28cb", "5fa5c04ca39fb9c46bfef0e0807a18d0cd9a4ba7" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon Jul 03 11:48:56 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jul 03 11:48:56 2017 +0000" }, "message": "Merge \"MIPS: Shorten .bss string/class loads\"" }, { "commit": "8098da9cf3e3f7875546c2cd953f2337587b39db", "tree": "8f0b2d69f83a1de7a0bb80ce1c3f1412c429615d", "parents": [ "ebd4def76f4e60e442edb8d48f43a931bc3c773e" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Wed Jun 28 12:07:50 2017 +0200" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Wed Jun 28 17:42:17 2017 +0200" }, "message": "MIPS32: MoveLocation refactoring\n\nMove32 and Move64 are removed so MoveLocation now handles all cases.\nReason for this are 128-bit (SIMDStackSlot, VectorRegister) moves\nwhich will be added in follow-up patch.\n\nTest: mma test-art-host-gtest\nTest: ./testrunner.py --optimizing --target in QEMU\n\nChange-Id: I93496e74874f77337b11b2265aa4b470bc7c6ce2\n" }, { "commit": "5fa5c04ca39fb9c46bfef0e0807a18d0cd9a4ba7", "tree": "f902c5dad2486b8372c31989ac9b917715231fa8", "parents": [ "83b140474aa1759739c8ee4464bf226c4fa0f6d7" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Jun 01 21:07:52 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Jun 08 14:39:57 2017 -0700" }, "message": "MIPS: Shorten .bss string/class loads\n\nThis is a follow-up to\nhttps://android-review.googlesource.com/#/c/384033/.\n\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: testrunner.py --target --optimizing\nTest: same tests as above on CI20\nTest: booted MIPS32R2 and MIPS64 in QEMU in configurations:\n ART_USE_READ_BARRIER\u003dfalse,\n ART_READ_BARRIER_TYPE\u003dTABLELOOKUP\n\nChange-Id: I4cb2f4ded13c0d9fc960c7eac55396f7931c1e38\n" }, { "commit": "0eb882bfc5d260e8014c26adfda11602065aa5d8", "tree": "e66dbebfb1e9a254c20954a2f2f98541aebfd5af", "parents": [ "b5f5d746ac3f2c3088292395603cb1470e7749d2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 15 13:39:18 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jun 07 15:39:24 2017 +0100" }, "message": "Use ArtMethod* .bss entries for HInvokeStaticOrDirect.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: testrunner.py --target\nTest: Nexus 6P boots.\nTest: Build aosp_mips64-userdebug.\nBug: 30627598\nChange-Id: I0e54fdd2e91e983d475b7a04d40815ba89ae3d4f\n" }, { "commit": "3c8a91250b3e4e87548ec16bf1ab1ea46dbb84a4", "tree": "b5da100b358d1335eab403372e4f616c5c2d607c", "parents": [ "0a87f31513e5f9da27856af054d2241452898b22", "e7197bf7d58c705a048e13e241d7ca320502cd40" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jun 07 10:38:10 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jun 07 10:38:11 2017 +0000" }, "message": "Merge \"Replace invoke kind kDexCacheViaMethod with kRuntimeCall.\"" }, { "commit": "e7197bf7d58c705a048e13e241d7ca320502cd40", "tree": "496032b40145660b40002b9d5b7a78f1c2eeb44f", "parents": [ "4ee8e291a7d5b7b98f35f495eb97705836910871" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 02 17:00:23 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 06 15:26:42 2017 +0100" }, "message": "Replace invoke kind kDexCacheViaMethod with kRuntimeCall.\n\nIn preparation for replacing the dex cache method array\nwith a hash-based array, get rid of one unnecessary use.\nThis method load kind is currently used only on mips for\nirreducible loops and OSR, so this should have no impact\non x86/x86-64/arm/arm64.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: Repeat the above tests with manually changing\n kDexCachePcRelative to kRuntimeCall in sharpening.cc.\n (Ignore failures in 552-checker-sharpening.)\nBug: 30627598\nChange-Id: Ifce42645f2dcc350bbb88c2f4642e88fc5f98152\n" }, { "commit": "847e6ce98b4b822fd94c631975763845978ebaa3", "tree": "760e26dea1597d8219d8c515317d978b0213cdc1", "parents": [ "cff1b21b3e19c5d3a2d726fdb60dacd7de2a6f0d" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 02 13:55:07 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 02 14:03:28 2017 +0100" }, "message": "Rename kDexCacheViaMethod to kRuntimeCall for HLoadClass/String.\n\nThe old name does not reflect the actual code anymore.\n\nTest: testrunner.py --host\nChange-Id: I2e13cf727bba9d901c4d3fc821bb526d38a775b8\n" }, { "commit": "6079dca3058e58bb9e12a60a10324a5218a99274", "tree": "19e3a8ccf7a8ac831c27658e0470c4f83debef74", "parents": [ "0a5ace58e973da278049f837bf2cdbaf7b44849c" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sun May 28 19:10:28 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sun May 28 20:17:39 2017 -0700" }, "message": "MIPS32R2: Fix MethodLoadKind::kBootImageLinkTimePcRelative\n\nThis makes MIPS32 boot again.\n\nThe issue was introduced in commit\n6597946d29be9108e2cc51223553d3db9290a3d9:\nStatic invokes in slow paths would sometimes get\nHMipsComputeBaseMethodAddress from the stack into the\nsame register where the art method pointer would later\nbe loaded (A0) with the former being overwritten in the\nprocess of loading the latter.\n\nTest: booted MIPS32R2 in QEMU\n\nChange-Id: Ib584cf66795574175650f42b191c797fb3b3965f\n" }, { "commit": "6597946d29be9108e2cc51223553d3db9290a3d9", "tree": "cea6647a45cc59fa1423751179e647124f269990", "parents": [ "a654e0378a8d0bb149362399917e4da2959e6991" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri May 19 17:25:12 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 22 18:35:05 2017 +0100" }, "message": "Use PC-relative pointer to boot image methods.\n\nIn preparation for adding ArtMethod entries to the .bss\nsection, add direct PC-relative pointers to methods so that\nthe number of needed .bss entries for boot image is small.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: testrunner.py --target on Nexus 6P\nTest: Nexus 6P boots.\nTest: Build aosp_mips64-userdebug\nBug: 30627598\nChange-Id: Ia89f5f9975b741ddac2816e1570077ba4b4c020f\n" }, { "commit": "764d454d1d51448deb81f6e8d2d7d317c7f4d1b4", "tree": "029f9e65cfe7e953df55b7af45e099924ffdbbac", "parents": [ "7974468d32b817be1d49dfcf513605f646c481bc" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 16 10:31:41 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 16 15:08:55 2017 +0100" }, "message": "Remove LoadString/Class kind kBootImageLinkTimeAddress.\n\nWe no longer support non-PIC boot image compilation.\n\nAlso clean up some obsolete code for method patches\nand make JIT correctly report itself as non-PIC.\n\nTest: testrunner.py --host\nTest: testrunner.py --target\nBug: 33192586\nChange-Id: I593289c5c1b0e88b82b86a933038be97bbb15ad2\n" }, { "commit": "f4e23a8a671e27065bf1cbef7e41403de166f321", "tree": "d25d31f7c1c53f4baf746baafa76b891596c5d49", "parents": [ "d6705a0586377f1b0d7d14d3abe2b270bb0adb18" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Tue May 09 15:43:45 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri May 12 15:08:27 2017 +0200" }, "message": "MIPS: Drop unnecessary code for R6 (NAN2008)\n\nThe latest MIPS64R6 emulator supports NAN2008 standard (it correctly\nsets FCSR.NAN2008 to 1 as it is required from R6). Because of that,\nmany workarounds can be removed.\n\nThis simplifies code generator and intrinsics.\n\nTest: ./testrunner.py --target --optimizing in QEMU for MIPS64R6\nTest: ./testrunner.py --target --optimizing in QEMU for MIPS32R6\nTest: ./testrunner.py --target --optimizing in QEMU for MIPS32R2\n\nChange-Id: Ib5335835b61f55690ff574bca580ea8f809657bb\n" }, { "commit": "7d157fcaaae137cc98dbfb872aa1bdc0105a898f", "tree": "2b7d8affda23908e5bfbfaad446079db2ef1ee09", "parents": [ "58d7ddc678e5bcd2364c24c4bdc8a3cfbcfc5358" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 10 16:29:23 2017 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 11 11:14:54 2017 +0100" }, "message": "Clean up some uses of \"auto\".\n\nMake actual types more explicit, either by replacing \"auto\"\nwith actual type or by assigning std::pair\u003c\u003e elements of\nan \"auto\" variable to typed variables. Avoid binding const\nreferences to temporaries. Avoid copying a container.\n\nTest: m test-art-host-gtest\nChange-Id: I1a59f9ba1ee15950cacfc5853bd010c1726de603\n" }, { "commit": "ddc38fe3e5618e3922ecc445193dacb2f39ef736", "tree": "090cf77abda6a5755371673966ceea83f858048c", "parents": [ "45f9865cc974d344c9a859508c8ec8ce101f4c52", "4e92c3ce7ef354620a785553bbada554fca83a67" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed May 10 10:55:45 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed May 10 10:55:47 2017 +0000" }, "message": "Merge \"Add runtime reasons for deopt.\"" }, { "commit": "4e92c3ce7ef354620a785553bbada554fca83a67", "tree": "42029deff4d3ba7f89b5fdbf79ff410da575f431", "parents": [ "549844e9ccf432d1396b19af890eedb602b8ba04" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 08 09:34:26 2017 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed May 10 09:27:33 2017 +0100" }, "message": "Add runtime reasons for deopt.\n\nCurrently to help investigate. Also:\n1) Log when deoptimization happens (which method and what reason)\n2) Trace when deoptimization happens (to make it visible in systrace)\n\nbug:37655083\nTest: test-art-host test-art-target\nChange-Id: I0c2d87b40db09e8e475cf97a7c784a034c585e97\n" }, { "commit": "bf2dd4baecee0e82608a83eca9738205446bcb03", "tree": "a321c0bfb58a3d8caa1e4f95b1860656ab2fad97", "parents": [ "b9c3a99096c746b09af611e55e11b86600374011", "6d482aa01d2190e7f972553f359df7958d31af57" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon May 08 14:47:09 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon May 08 14:47:11 2017 +0000" }, "message": "Merge \"MIPS32: Implement branchless HCondition for longs\"" }, { "commit": "f3fb1fc453c253a075050910a558c89c1330b5af", "tree": "ca758f050dc3a892e360af094f36fde056e40fef", "parents": [ "9459127abb57b0892d3ddeb1e30ac0bf28c93761", "c61c0761150340263160b568d8a952e9a3d80d56" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu May 04 14:46:32 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu May 04 14:46:33 2017 +0000" }, "message": "Merge \"MIPS: Change remaining entrypoints to save everything.\"" }, { "commit": "d01745ef88bfd25df574a885d90a1a7785db5f5b", "tree": "058eb1593dbb0fe8a8e26b901909bec8aa01d474", "parents": [ "a57c334075b193de9690fff97acf6c1b1d1283fc" ], "author": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Wed Apr 05 16:40:31 2017 -0700" }, "committer": { "name": "Igor Murashkin", "email": "iam@google.com", "time": "Tue May 02 09:45:45 2017 -0700" }, "message": "optimizing: constructor fence redundancy elimination - remove dmb after LSE\n\nPart one of a few upcoming CLs to optimize constructor fences.\n\nThis improves load-store-elimination; all singleton objects that are not\nreturned will have their associated constructor fence removed.\n\nIf the allocation is removed, so is the fence. Even if allocation is not\nremoved, fences can sometimes be removed.\n\nThis change is enabled by tracking the \"this\" object associated with the\nconstructor fence as an input. Fence inputs are considered weak; they do not keep\nthe \"this\" object alive; if the instructions for \"this\" are all deleted,\nthe fence can also be deleted.\n\nBug: 36656456\nTest: art/test.py --host \u0026\u0026 art/test.py --target\nChange-Id: I05659ab07e20d6e2ecd4be051b722726776f4ab1\n" }, { "commit": "c61c0761150340263160b568d8a952e9a3d80d56", "tree": "105418862af2193d590fc5da868e4c72da7d6e6a", "parents": [ "a57c334075b193de9690fff97acf6c1b1d1283fc" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Apr 10 13:54:23 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sun Apr 30 15:30:58 2017 -0700" }, "message": "MIPS: Change remaining entrypoints to save everything.\n\nThis also fixes two issues:\n1. Missing restore of the callee-clobbered gp register on\n MIPS32\n2. Incorrect DCHECK causing test 916-obsolete-jit to fail\n on MIPS32 in the ART_READ_BARRIER_TYPE\u003dTABLELOOKUP\n configuration\n\nTest: booted MIPS32R2 in QEMU\nTest: test-art-target-gtest\nTest: testrunner.py --target --optimizing\nTest: booted MIPS64 (with 2nd arch MIPS32R2) in QEMU\nTest: same tests as above for both MIPS32R6 and MIPS64R6\nTest: repeat all of the above in two configurations:\n ART_READ_BARRIER_TYPE\u003dTABLELOOKUP,\n ART_USE_READ_BARRIER\u003dfalse.\n\nChange-Id: I06a3c24579242a632ec8c373c233217d558a8401\n" }, { "commit": "cd0295d81b6d53bbade117a0531b2453e8cb7c7f", "tree": "eceada4e7329ce8fc2e993f414f515c186b81f10", "parents": [ "ef6787bd892b55588ebb2835cc3a3bc4e9e08d04" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Fri Mar 31 15:26:54 2017 -0700" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Mon Apr 10 10:19:30 2017 -0700" }, "message": "MIPS: Use Lsa/Dlsa when possible.\n\nFor MIPS32R6 replace instances of \"sll/addu\" to calculate the\naddress of an item in an array with \"lsa\". For other versions of\nMIPS32 use the \"sll/addu\" sequence. Encapsulate this logic in an\nassembler method to eliminate having a lot of statements like\n\"if (IsR6()) { ... } else { ... }\" scattered throughout the code.\n\nMIPS64 always supports R6. This means that all instances of\n\"dsll/daddu\" used to calculate the address of an item in an array\ncan be replaced by \"dlsa\" so there is no need to encapsulate\nconditional logic in a special method. The code can just emit\n\"dlsa\" directly.\n\nTest: mma -j2 ART_TEST_OPTIMIZING\u003dtrue test-art-target-run-test\nTested on MIPS32, and MIPS64 QEMU.\nTest: \"make test-art-target-gtest32\" on CI20 board.\nTest: \"cd art; test/testrunner/testrunner.py --target --optimizing --32\"\n on CI20 board.\n\nChange-Id: Ibe5facc1bc2a6a7a6584e23d3a48e163ae38077d\n" }, { "commit": "1595815c2a914a78df7dfb6f0082f47d4e82bb36", "tree": "8fd53c3c91158b33e744e43cc655b2e2a180a3fc", "parents": [ "4ba18fdfc2581a2328ab745c2707e3ed375d9e64" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Feb 09 19:08:30 2017 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Mar 28 23:35:34 2017 -0700" }, "message": "MIPS: Implement read barriers.\n\nThis is the core functionality. Further improvements\nwill be done separately.\n\nThis also adds/moves memory barriers where they belong and\nremoves the UnsafeGetLongVolatile and UnsafePutLongVolatile\nMIPS32 intrinsics as they need to load/store a pair of\nregisters atomically, which is not supported directly by\nthe CPU.\n\nTest: booted MIPS32R2 in QEMU\nTest: test-art-target-run-test\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: \"testrunner.py --target --optimizing -j1\"\nTest: same MIPS64 boot/test with ART_READ_BARRIER_TYPE\u003dTABLELOOKUP\nTest: \"testrunner.py --target --optimizing --32 -j2\" on CI20\nTest: same CI20 test with ART_READ_BARRIER_TYPE\u003dTABLELOOKUP\n\nChange-Id: I0ff91525fefba3ec1cc019f50316478a888acced\n" }, { "commit": "68fdd5a22024f70a65159bcb8929296fc93b807d", "tree": "d0d5256fde2f91b61bde97d0632436cabb0b23db", "parents": [ "02a4d7ff633e67d0a5113f0fc742116dcdc5b7f6", "c52f3034b06c03632e937aff07d46c2bdcadfef5" ], "author": { "name": "Richard Uhler", "email": "ruhler@google.com", "time": "Thu Mar 09 08:33:03 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Mar 09 08:33:04 2017 +0000" }, "message": "Merge \"Remove --include-patch-information option from dex2oat.\"" }, { "commit": "f02253d12be42a5b980791265f0eb61d875396e3", "tree": "1f908e9a9523658bf2e244b90508852e1885a222", "parents": [ "d419beb312816edbf2186c12b15321d11c29996d", "66b69ad6d1a2ddd38bf533a3c887c5cdaf512634" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Wed Mar 08 23:58:25 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Mar 08 23:58:25 2017 +0000" }, "message": "Merge \"MIPS: Optimize code generation of check-cast and instance-of.\"" }, { "commit": "c52f3034b06c03632e937aff07d46c2bdcadfef5", "tree": "031e4d1b2ca0961014e57e4987d80d7aa2c435b0", "parents": [ "ef81e988d0eb4db390e576aac346701b2d820916" ], "author": { "name": "Richard Uhler", "email": "ruhler@google.com", "time": "Thu Mar 02 13:45:45 2017 +0000" }, "committer": { "name": "Richard Uhler", "email": "ruhler@google.com", "time": "Wed Mar 08 10:55:17 2017 +0000" }, "message": "Remove --include-patch-information option from dex2oat.\n\nBecause we no longer support running patchoat on npic oat files, which\nmeans the included patch information is unused .\n\nBug: 33192586\nTest: m test-art-host\n\nChange-Id: I9e100c4e47dc24d91cd74226c84025e961d30f67\n" } ], "next": "6d482aa01d2190e7f972553f359df7958d31af57" }