)]}' { "log": [ { "commit": "a0130e8d2842a9a82e4fd4e811ee699272eb2e0b", "tree": "1468e015b7c4b001e40d847cf1448311706516e7", "parents": [ "75c8b635178d0c59691c2bc22f3bd1101d5516b5" ], "author": { "name": "Andra Danciu", "email": "andradanciu@google.com", "time": "Thu Jul 23 12:34:56 2020 +0000" }, "committer": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Fri Jul 24 10:11:54 2020 +0000" }, "message": "Prepare compiler for adding VarHandle support.\n\nThis commit prepares the ground for adding VarHandle support\nin the compiler. The intrinsic locations builder and code\ngenerator are now triggered for HInvokePolymorphic nodes.\nVarHandle and MethodHandle intrinsics are marked as unimplemented\nrather than unreachable.\n\nSince the Varhandle intrinsics are not implemented yet, the\nfunctionality is not changed (i.e. the intrinsics are evaluated\nat runtime and not compiled). I manually tested that the intrinsic\nVisit* methods are triggered for the VarHandle methods.\n\nBug: b/65872996\nTest: art/test.py --host -r -t 713-varhandle-invokers\nTest: art/test.py --host --all-compiler -r\n\nChange-Id: I3333728c5f16d8dc4f92ceae2738ed59b3e31e6a\n" }, { "commit": "f9388416a3315b93d0cf14eeaf8df49a7c4da176", "tree": "f90d73c779cc16bf2a532b102820a2c7ecdd30e9", "parents": [ "af92a0f06fe3ab2618ccc220df3dacc3a20d8bb1" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Thu Jul 02 15:25:13 2020 +0100" }, "committer": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Thu Jul 02 17:23:25 2020 +0100" }, "message": "ARM: Optimize Div/Rem by positive const for non-negative dividends\n\nWhen a constant divisor is positive and it can be proved that dividends\nare non-negative, there is no need to generate instructions correcting\nthe result.\n\nThe CL implements this optimization for ARM32/ARM64.\n\nTest: 411-checker-hdiv-hrem-const\nTest: test.py --host --optimizing --jit --gtest --interpreter\nTest: test.py -target --optimizing --jit --interpreter\nTest: run-gtests.sh\nChange-Id: Idf9aa740f14700000948b5ca58311be403a269ee\n" }, { "commit": "af92a0f06fe3ab2618ccc220df3dacc3a20d8bb1", "tree": "a1825765fba713b9805a26b35743506907cdefe8", "parents": [ "8d799686ff11ef800a8489272f4e0b36b6ab21b3" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Fri Jun 26 13:28:33 2020 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jul 02 10:49:08 2020 +0000" }, "message": "ARM: Optimize Div/Rem by 2^n for non-negative dividends\n\nWhen it can be proved that dividends are non-negative or the min integer\nif their type is integral, there is no need to generate instructions\ncorrecting the result.\n\nThe CL implements this optimization for ARM32/ARM64.\n\nTest: 411-checker-hdiv-hrem-pow2\nTest: test.py --host --optimizing --jit --gtest --interpreter\nTest: test.py -target --optimizing --jit --interpreter\nTest: run-gtests.sh\n\nChange-Id: I11211a42918b5801fce8e78f305e69549739c23c\n" }, { "commit": "dec7817522eeaf8f88dcae9ce065969aeebda3b3", "tree": "a15fd16ccb4a1929ec60584ead8f095b565c9e3e", "parents": [ "ea4d7d2d52dd9795cf39eccd46cb07551c62392f" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 19 15:31:23 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 22 08:05:28 2020 +0000" }, "message": "Optimizing: Introduce {Increase,Decrease}Frame().\n\nAnd use it to clean up code generators.\n\nAlso fix CFI in MaybeIncrementHotness() for arm/arm64/x86.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: testrunner.py --host --debuggable --ndebuggable \\\n --optimizing --jit --jit-on-first-use -t 178\nTest: aosp_cf_x86_phone-userdebug boots.\nTest: aosp_cf_x86_phone-userdebug/jitzygote boots.\nTest: # On blueline:\n testrunner.py --target --debuggable --ndebuggable \\\n --optimizing --jit --jit-on-first-use -t 178\nBug: 112189621\nChange-Id: I524e6c3054ffe1b05e2860fd7988cd9995df2963\n" }, { "commit": "86c8752f64629325026945cd4eabd1dcea224acb", "tree": "9dc2be978f9e784a3ce16fa29d46941a94ac1c94", "parents": [ "f97a859e85f703644d897f0e3e1bc54315557aaa" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 11 16:55:55 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 19 08:26:46 2020 +0000" }, "message": "Direct calls to @CriticalNative methods.\n\nEmit direct calls from compiled managed code to the native\ncode registered with the method, avoiding the JNI stub.\n\nGolem results:\nart-opt-cc x86 x86-64 arm arm64\nNativeDowncallStaticCritical +12.5% +62.5% +75.9% +41.7%\nNativeDowncallStaticCritical6 +55.6% +87.5% +72.1% +35.3%\nart-opt x86 x86-64 arm arm64\nNativeDowncallStaticCritical +28.6% +85.6% +76.4% +38.4%\nNativeDowncallStaticCritical6 +44.6% +44.6% +74.6% +32.2%\n\nTest: Covered by 178-app-image-native-method.\nTest: m test-art-host-gtest\nTest: testrunner.py --host --debuggable --ndebuggable \\\n --optimizing --jit --jit-on-first-use\nTest: run-gtests.sh\nTest: testrunner.py --target --optimizing\nTest: testrunner.py --target --debuggable --ndebuggable \\\n --optimizing --jit --jit-on-first-use -t 178\nTest: aosp_cf_x86_phone-userdebug boots.\nTest: aosp_cf_x86_phone-userdebug/jitzygote boots.\nBug: 112189621\nChange-Id: I8b37da51e8fe0b7bc513bb81b127fe0416068866\n" }, { "commit": "6587d9110bd7f836e43db16f3f676da996218aef", "tree": "437d06a8e60fd70aaafaf2b167dfe636a303c68a", "parents": [ "1912a5c7b9400009e361b0db52da77cc78f1cd77" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Fri Jun 12 10:51:43 2020 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 17 08:00:58 2020 +0000" }, "message": "ART: Simplify HRem to reuse existing HDiv\n\nA pattern seen in libcore and SPECjvm2008 workloads is a pair of HRem/HDiv\nhaving the same dividend and divisor. The code generator processes\nthem separately and generates duplicated instructions calculating HDiv.\n\nThis CL adds detection of such a pattern to the instruction simplifier.\nThis optimization affects HInductionVarAnalysis and HLoopOptimization\npreventing some loop optimizations. To avoid this the instruction simplifier\nhas the loop_friendly mode which means not to optimize HRems if they are in a loop.\n\nA microbenchmark run on Pixel 3 shows the following improvements:\n\n | little cores | big cores\narm32 Int32 | +21% | +40%\narm32 Int64 | +46% | +44%\narm64 Int32 | +27% | +14%\narm64 Int64 | +33% | +27%\n\nTest: 411-checker-instruct-simplifier-hrem\nTest: test.py --host --optimizing --jit --gtest --interpreter\nTest: test.py --target --optimizing --jit --interpreter\nTest: run-gtests.sh\n\nChange-Id: I376a1bd299d7fe10acad46771236edd5f85dfe56\n" }, { "commit": "9922f00cf68aac69209216a0726a45eb6338763c", "tree": "7e43b55e85ed17443af1c6be6532dafbb8550495", "parents": [ "16527e892b13c9e1fb34f8d2e9993e58a72ac662" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 08 15:05:15 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 09 10:03:58 2020 +0000" }, "message": "arm/arm64: Clean up intrinsic slow paths.\n\nGeneralize and use the slow path template IntrinsicSlowPath\nfrom intrinsics_utils.h.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_taimen-userdebug boot image is unchanged.\nChange-Id: Ia8fa4e1b31c1f190fc5f02671336caec15e4cf4d\n" }, { "commit": "695348f4b0541f4373b46eac5830cdd87f71c076", "tree": "f2f6019f0c394f99aaaf9f2f7deec16bf6116b0f", "parents": [ "1f5300a211202442a07607830c6550773ca50b50" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue May 19 14:42:02 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 20 08:41:09 2020 +0000" }, "message": "Add compiler type to CompilerOptions.\n\nLet CompilerOptions hold the information whether it is AOT\nor JIT compilation, or Zygote JIT for shared code.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: aosp_taimen-userdebug boots.\nChange-Id: Id9200572406f8e43d99b8b61ef0e3edf43b52fff\n" }, { "commit": "0ddb338f084b1c46efbfa7a79ad6aa1b63a24ded", "tree": "e36eaa49dd79914622fff402f6ca2e829646c3fb", "parents": [ "8bcba2264f5ba66ef8820e3963e838a67bd6215f" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Mon May 18 11:15:46 2020 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 18 15:10:40 2020 +0000" }, "message": "ARM64: Combine LSR+ADD into ADD_shift for Int32 HDiv/HRem\n\nHDiv/HRem having a constant divisor are optimized by using\nmultiplication of the dividend by a sort of reciprocal of the divisor.\nIn case of Int32 the multiplication is done into a 64-bit register\nhigh 32 bits of which are only used.\nThe multiplication result might need some ADD/SUB corrections.\nCurrently it is done by extracting high 32 bits with LSR and applying\nADD/SUB. However we can do correcting ADD/SUB on high 32 bits and extracting\nthose bits with the final right shift. This will eliminate the\nextracting LSR instruction.\n\nThis CL implements this optimization.\n\nTest: test.py --host --optimizing --jit\nTest: test.py --target --optimizing --jit\nChange-Id: I5ba557aa283291fd76d61ac0eb733cf6ea975116\n" }, { "commit": "1439e573517bb9f0b115aef5d3bbd9090751ebd6", "tree": "d6a1a4aed01719e988a8ac0fb81ed2843667d75f", "parents": [ "4be256069c494550037c81272ca4c27bd4a139df" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Tue May 12 12:43:09 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 18 09:11:30 2020 +0000" }, "message": "ART: Optimize ADD/SUB+ADD_shift into ADDS/SUBS+CINC for HDiv/HRem\n\nHDiv/HRem having a constant divisor are optimized by using\nmultiplication of the dividend by a sort of reciprocal of the divisor.\nThe multiplication result might need some corrections to be finalized.\nThe last correction is to increment by 1, if the result is negative.\nCurrently it is done with \u0027add result, temp_result, temp_result, lsr #31 or #63\u0027.\nSuch ADD usually has latency 2, e.g. on Cortex-A55.\nHowever if one of the corrections is ADD or SUB, the sign can be detected\nwith ADDS/SUBS. They set the N flag if the result is negative.\nThis allows to use CINC which has latency 1:\n adds temp_result, temp_result, dividend\n cinc out, temp_result, mi\n\nThis CL implements this optimization.\n\nTest: test.py --host --optimizing --jit\nTest: test.py --target --optimizing --jit\nChange-Id: Ia6aac6771908e992c86e32fe1694a82bd1b7af0b\n" }, { "commit": "f91fc1220f1b77c55317ff50f4dde8e6b043858f", "tree": "3b8416a4fa9b9278d1114d4002485e0cb1c704bf", "parents": [ "33c091eaaa0febedc93cff820def75b122fde867" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 13 09:21:00 2020 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri May 15 14:09:54 2020 +0000" }, "message": "Optimizing: Run gtests without creating the Runtime.\n\nThe only Optimizing test that actually needs a Runtime is\nthe ReferenceTypePropagationTest, so we make it subclass\nCommonCompilerTest explicitly and change OptimizingUnitTest\nto subclass CommonArtTest for the other tests.\n\nOn host, each test that initializes the Runtime takes ~220ms\nmore than without initializing the Runtime. For example, the\nConstantFoldingTest that has 10 individual tests previously\ntook over 2.2s to run but without the Runtime initialization\nit takes around 3-5ms. On target, running 32-bit gtests on\ntaimen with run-gtests.sh (single-threaded) goes from\n~28m47s to ~26m13s, a reduction of ~9%.\n\nTest: m test-art-host-gtest\nTest: run-gtests.sh\nChange-Id: I43e50ed58e52cc0ad04cdb4d39801bfbae840a3d\n" }, { "commit": "968db3c09e5059e30044d69f1a5fd9bcd937392e", "tree": "5496a327556b30ac2cd1877b515fa852688036bd", "parents": [ "2750a9884d7579f301c7ff65a6daaf8520af7902" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Thu May 07 12:44:10 2020 +0100" }, "committer": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Tue May 12 10:35:49 2020 +0100" }, "message": "ARM64: Combine LSR+ASR into ASR for Int32 HDiv/HRem\n\nHDiv/HRem having a constant divisor are optimized by using\nmultiplication of the dividend by a sort of reciprocal of the divisor.\nThe multiplication is done by multiplying 32-bit numbers into a 64-bit\nresult. The high 32 bits of the result are used. In case of Int32 LSR\nis used to get those bits. After that there might be correction\noperations and ASR. When there are no correction operations between LSR\nand ASR they can be combined into one ASR.\n\nThis CL implements this optimization.\n\nImprovements (Pixel 3):\n little core big core\n jit_aot/LoadCheck.RandomSumInvokeStaticMethod 7.1% 8.3%\n jit_aot/LoadCheck.RandomSumInvokeUserClass 4.6% 12.0%\n benchmarksgame/fasta 3.3% 1.0%\n benchmarksgame/fasta_4 2.4% 2.6%\n benchmarksgame/fastaredux 2.2% 2.2%\n SPECjvm2k8 MPEGAudio 1.7% 1.0%\n\nTest: test.py --host --optimizing --jit\nTest: test.py --target --optimizing --jit\nChange-Id: I5267b38d3a58319e24152917fabe836d5b346bce\n" }, { "commit": "a6653d304faa3bbd981507570a4ac1107760c6a7", "tree": "6dc333f6f19b932c0fd739b4862c3800b3a51b45", "parents": [ "4d0f795aaa9abd1b36e2704b3851b2cc39c70cdd" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Tue May 05 16:30:24 2020 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu May 07 09:04:21 2020 +0000" }, "message": "ART: Refactor InstructionCodeGeneratorARM64::GenerateDivRemWithAnyConstant\n\nInstructionCodeGeneratorARM64::GenerateDivRemWithAnyConstant handles\nboth Int32 and Int64 cases. However Int32 cases can have additional\noptimizations. Having them in GenerateDivRemWithAnyConstant makes code\ndifficult to read.\n\nThis CL splits the code of GenerateDivRemWithAnyConstant to:\n* GenerateInt32DivRemWithAnyConstant\n* GenerateInt64DivRemWithAnyConstant\n* GenerateResultDivRemWithAnyConstant\n\nTest: test.py --host --optimizing --jit\nTest: test.py --target --optimizing --jit\nChange-Id: I267331c026e87d6a233b593586f1b74759382896\n" }, { "commit": "1a719e4de83532a1dcd9ddfad2c92d4130f28ea9", "tree": "445026effb3298ca8e962701ee01f65785be6fe6", "parents": [ "e33dca6d44463606168330d2f84bc616e8c147f6" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Jul 18 14:24:55 2019 +0100" }, "committer": { "name": "Ulyana Trafimovich", "email": "skvadrik@google.com", "time": "Mon May 04 08:19:17 2020 +0000" }, "message": "RFC: ARM64: Split arm64 codegen into scalar and vector (SVE and NEON).\n\nThis is a first CL in the series of introducing arm64 SVE support\nin ART. The patch splits the codegen functionality into scalar and\nvector ones and for the latter introduces NEON and SVE\nimplementations. SVE one currently is an exact copy of NEON one -\nfor the sake of testing and an easy diff when the next CL comes\nwith an actual SVE instructions support.\n\nThe patch effectively doesn\u0027t change any behavior; NEON mode is\nused for vector instructions, tests pass.\n\nTest: test-art-target.\nChange-Id: I5f7f2c8218330998e5a733a56f42473526cd58e6\n" }, { "commit": "c8150b5def82058c23df377a5006a78e7668afeb", "tree": "8f0e15b91cd55b978ca7f152206f0a550353810a", "parents": [ "b2028739a2db03623ed76f5028ede1333c48f4c9" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Wed Jul 31 18:28:00 2019 +0100" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Apr 17 10:35:45 2020 +0000" }, "message": "ART: Refactor SIMD slots and regs size processing.\n\nART vectorizer assumes that there is single size of SIMD\nregister used for the whole program. Make this assumption explicit\nand refactor the code.\n\nNote: This is a base for the future introduction of SIMD slots of\nsize other than 8 or 16 bytes.\n\nTest: test-art-target, test-art-host.\nChange-Id: Id699d5e3590ca8c655ecd9f9ed4e63f49e3c4f9c\n" }, { "commit": "c1cd1330c65e8b9b13bcd93bd9634eed6453c5dc", "tree": "4fe4f02f8107e761f246745259260356a3bac12f", "parents": [ "08a1d1ba90c69e4b39f2df90eacee2c5413f8b4e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sat Jan 25 13:08:24 2020 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sat Jan 25 13:08:24 2020 +0000" }, "message": "Fix braino in arm64 codegen.\n\nPointers are 64bit there...\n\nBug: 148303458\nTest: 597-deopt-busy-loop\nChange-Id: Iee003f883665e4a668068b8e056380abc2f5fab4\n" }, { "commit": "796aa2cfcde9c88fa0a3176899e25bab3468ebd2", "tree": "9f4be44ef08e5abbdcb16ed6e8d15459bb743222", "parents": [ "57cacb720e6f995aa1a42df6e2e6470a9ec57261" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 17 10:20:05 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 17 11:31:30 2019 +0000" }, "message": "[baseline] Check that the profiling info is not null.\n\nZygote cannot allocate profiling infos.\n\nTest: 689-zygote-jit-deopt\nChange-Id: I85e8b7f16b81ba4de435a5417dbb2588c34414b0\n" }, { "commit": "57cacb720e6f995aa1a42df6e2e6470a9ec57261", "tree": "bb73a113c94bc397cd7c99a4c64e033bf29b9803", "parents": [ "013d1ee96b928f3bda9031e94d4a69f827133ce6" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sun Dec 08 22:07:08 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 17 09:48:00 2019 +0000" }, "message": "Refactor OSR related code to prepare for \"true\" OSR.\n\n- Make the compiler restore all callee-save registers.\n- Make the compiler return any value in a core register: this simplifies\n the current stub, and will also avoid having to look at the return\n type (and reading the shorty) when returning to an nterp frame.\n- Add OsrData and offsets of its members to be used by nterp.\n\nTest: test.py\nBug: 27094810\nChange-Id: Ifa4f4877ab8b1f0c6a96feccea30c909942eb2fa\n" }, { "commit": "9b5271e53a76cbe3d269d1b70da7f13b9d944db1", "tree": "ff89e3a40d274e812f5727d7ff7930d19d447d35", "parents": [ "a00b54b74bee06c006b8bebfbef85e2801de293c" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Dec 04 14:39:46 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Dec 04 14:39:46 2019 +0000" }, "message": "Get the baseline information from the graph.\n\nBaseline could be set by the compiler options or the JIT.\n\nTest: test.py\nBug: 119800099\nChange-Id: I702bd7642dfd3353c9ad99cb6ac425c090e16101\n" }, { "commit": "a59af8aeaad8fe7d68d8f8de63eab9cf85b6ab31", "tree": "83195c74b135731cc4555254763a8f449691c1b0", "parents": [ "5c8cc64b5f1580faf510f27527e7e22987174963" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 27 17:42:32 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 03 14:32:09 2019 +0000" }, "message": "JIT baseline: trigger optimized compilation on hotness threshold.\n\n- Add a new hotness count in the ProfilingInfo to not conflict with\ninterpreter hotness which may use it for OSR.\n- Add a baseline flag in the OatQuickMethodHeader to identify baseline\ncompiled methods.\n- Add a -Xusetieredjit flag to experiment and test.\n\nBug: 119800099\nTest: test.py with Xusetieredjit to true\n\nChange-Id: I8512853f869f1312e3edc60bf64413dee9143c52\n" }, { "commit": "20036d80f246b564331e0943aa07ec3b50fc15d9", "tree": "68c421f9da0c7ff7453ba5093203b94f9ec283c6", "parents": [ "36ec598a4d887746291d003c97c2cb28b5987768" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Nov 28 16:15:00 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Nov 28 17:16:57 2019 +0000" }, "message": "JIT baseline: don\u0027t update inline caches for intrinsics.\n\nWe already know the target.\n\nBug: 119800099\nTest: test.py --baseline\nChange-Id: I14cdafe233fec83a1f69e307326858c591309c34\n" }, { "commit": "e2a3aa988630b3c2952ac44943f03dde60454195", "tree": "acee7012af6e2b161c91e6cd8b7b4d12eb5aa927", "parents": [ "a2c4d61e482a15974e3e220bcd62a64043ee536f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Nov 25 17:52:58 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 27 14:04:43 2019 +0000" }, "message": "Baseline JIT: update inline caches in compiled code.\n\nIn trying to remove profiling from interpreter, to speed up\ninterpreter performance.\n\nBug: 119800099\nTest: test.py --baseline\nChange-Id: Ica1fa41a889b31262d9f5691b30a31fbcec01b34\n" }, { "commit": "7d48dcd51db4b950c22ec78ef3caa53fdf4214d3", "tree": "72600968b1daf5682018880f20ca07610e62b8e7", "parents": [ "f05f04b429a63eb036f501866a863109f05b95b2" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Wed Oct 16 12:46:28 2019 +0100" }, "committer": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Oct 31 14:56:52 2019 +0000" }, "message": "ARM64: Move from FPRegister to VRegister based API\n\nVIXL has had FPRegister as an alias for VRegister for backward\ncompatibility. In the latest upstream VIXL the alias has been removed and all\nFPRegister based API has became VRegister based. As AOSP VIXL is being\nupdated to the latest upstream VIXL all uses of FPRegister based API\nmust be replaced with VRegister based API.\nThis CL moves ART from FPRegister based API to VRegister based API.\n\nTest: test.py --host --optimizing --jit --gtest\nTest: test.py --target --optimizing --jit\nTest: run-gtests.sh\nChange-Id: I12541c16d0557835ea19c8667ae18c6601359b05\n" }, { "commit": "0a51605ddd81635135463dab08b6f7c21b58ffb0", "tree": "820f338333010f4d6e4b543ffea47e9ff7d2dd3f", "parents": [ "e2727154f25e0db9a5bb92af494d8e47b181dfcf" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 14 13:00:44 2019 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 14 13:00:44 2019 +0000" }, "message": "Revert \"Make compiler/optimizing/ symbols hidden.\"\n\nThis reverts commit e2727154f25e0db9a5bb92af494d8e47b181dfcf.\n\nReason for revert: Breaks ASAN tests (ODR violation).\nBug: 142365358\n\nChange-Id: I38103d74a1297256c81d90872b6902ff1e9ef7a4\n" }, { "commit": "e2727154f25e0db9a5bb92af494d8e47b181dfcf", "tree": "0ddc6eec3ad9508d7eb1f2b941786dd0ed7d2cd8", "parents": [ "c78860b91ae07eed92f86876e7a03132adea6fcd" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 10 10:46:42 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 14 08:22:00 2019 +0000" }, "message": "Make compiler/optimizing/ symbols hidden.\n\nMake symbols in compiler/optimizing hidden by a namespace\nattribute. The unit intrinsic_objects.{h,cc} is excluded as\nit is needed by dex2oat.\n\nAs the symbols are no longer exported, gtests are now linked\nwith the static version of the libartd-compiler library.\n\nlibart-compiler.so size:\n - before:\n arm: 2396152\n arm64: 3345280\n - after:\n arm: 2016176 (-371KiB, -15.9%)\n arm64: 2874480 (-460KiB, -14.1%)\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nBug: 142365358\nChange-Id: I1fb04a33351f53f00b389a1642e81a68e40912a8\n" }, { "commit": "2bb44fe818f2bf1d867a6ae490ef69c7f3a51e97", "tree": "c1860179daba52ab0d53707650c1e85194399629", "parents": [ "59770df741b87b201e83ef81cbcfac9df048d19b" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 04 12:28:14 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 09 08:25:22 2019 +0000" }, "message": "ARM64: Change code emitted by ClinitCheck.\n\nChange the code from MVN+CBNZ to CMP+BLO. The latter is\nbetter optimized in ARM64 CPUs. To avoid increasing code\nsize, this requires the preceding load to be changed from\nLDR to LDRB for a single byte of the 32-bit field.\n\nThis shows small but measurable improvement on a few Golem\nbenchmarks, for example MicroLambda, KotlinAutoReversiBench\nand KotlinImgProc-GaussianBlurOpt.\n\nTest: testrunner.py --target --optimizing\nBug: 36692143\nChange-Id: Ia73f791d7026220ef38e73bd5ee19fcc4877564d\n" }, { "commit": "988c3911671598d7c840c65bf1cdfafa1e05c582", "tree": "2ee476b2dbd75fa9c36cfdb28dbcede539eac195", "parents": [ "4bbc62ba98a74885dcc7fd21b468808774db5a8b" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Sep 25 19:33:35 2019 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Oct 01 12:20:13 2019 +0000" }, "message": "Fix null checks on volatile reference field loads on ARM64.\n\nART\u0027s compiler adds a null check HIR instruction before each field\nload HIR instruction created in the instruction builder phase. When\nimplicit null checks are allowed, the compiler elides the null check\nif it can be turned into an implicit one (i.e. if the offset is within\na system page range).\n\nOn ARM64, the Baker read barrier thunk built for field reference loads\nneeds to check the lock word of the holder of the field, and thus\nincludes an explicit null check if no null check has been done before.\nHowever, this was not done for volatile loads (implemented with a\nload-acquire instruction on ARM64). This change adds this missing null\ncheck.\n\nTest: art/test/testrunner/testrunner.py --target --64 -t 1004-checker-volatile-ref-load\nBug: 140507091\nBug: 36141117\nChange-Id: Ie94f2e73d2f439ae4460549d7b71848401602a21\n" }, { "commit": "7f8678ec4d2abec1f540fb441be60604bec86b6e", "tree": "e36b4d32dfc47fcebadf0ee5c7e4d1e3d51412a6", "parents": [ "84e5bb990d48263849bab132d80d753495bc7204" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri Aug 30 16:22:28 2019 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri Sep 06 18:40:59 2019 +0000" }, "message": "Revert^2 \"Prevent overflow for AOT hotness counters\"\n\nFixed bug where sbc usage was incorrect. sbc does -1 + carry.\n\nTest: test/run-test --always-clean --runtime-option -Xcheck:jni --64 674-hotness-compiled\nTest: test/run-test --always-clean --runtime-option -Xcheck:jni 674-hotness-compiled\nBug: 139883463\n\nThis reverts commit 7ab07777b08db86dda2891f3e7ae15df8f25a599.\n\nChange-Id: I6f8ac0320592a94314386b04cdb0c7e0e6da6994\n" }, { "commit": "7ab07777b08db86dda2891f3e7ae15df8f25a599", "tree": "1b0b2fa585e49e4a7913c09d67794763197c6490", "parents": [ "154445799432cb53d23cd011485132be07c39b5a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Aug 30 08:26:59 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Aug 30 08:57:20 2019 +0000" }, "message": "Revert \"Prevent overflow for AOT hotness counters\"\n\nThis reverts commit 79e6eb8b79be6249358b7801bc511290dacf10d0.\n\nBug: 139883463\n\nReason for revert: 674-hotness-compiled fails on target.\n\nChange-Id: I02fce74d70a4ae69dd5b4ae3924aa11728d9e16f\n" }, { "commit": "79e6eb8b79be6249358b7801bc511290dacf10d0", "tree": "1a04d214dd6223423abd442d8d9b0b61a3db2336", "parents": [ "bae88c0759d48acf29b58d960ad2665e3462dfda" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Mon Aug 26 12:33:46 2019 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Thu Aug 29 16:05:52 2019 +0000" }, "message": "Prevent overflow for AOT hotness counters\n\nPrevious, the addition did not have a check for overflow and might wrap\naround since the counter is only 16 bits.\n\nModified the test to exercise this.\n\nThe slowdown from fixing the overflow is 2% average on golem arm32/64.\nOverall this brings the slowdown from the counter to ~15% from ~13%.\n\nThe benchmarks that regress the most are loopy ones that I would\nconsider non-representative. Code size increases by 0.6%.\n\nBug: 139883463\nTest: test/run-test --host --64 --prebuild 674-hotness-compiled\nTest: test/run-test --host --prebuild 674-hotness-compiled\nTest: test/run-test --64 --prebuild 674-hotness-compiled\nTest: test/run-test ---prebuild 674-hotness-compiled\n\nChange-Id: Icf0ab2aedbc40ab10c9d952ce0f9c7b5e5feaf15\n" }, { "commit": "be53085e183be3edafdf03cac58624c87383e7e9", "tree": "7406d4ff01c6d01e82a9a5119e57968bd33fec1a", "parents": [ "5a75277056c8d528b0f68b7dbbb11609d0c91528" ], "author": { "name": "Georgia Kouveli", "email": "georgia.kouveli@linaro.org", "time": "Thu Jan 17 10:46:41 2019 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Aug 14 08:20:56 2019 +0000" }, "message": "ARM64: Improve BoundsCheck for constant inputs.\n\nThis is a port of 2dd053d to ARM64.\n\nOriginal author: Georgia Kouveli \u003cgeorgia.kouveli@linaro.org\u003e\nCommitted by: David Horstmann \u003cdavid.horstmann@linaro.org\u003e\n\nTest: test-art-target, test-art-host\nTest: 1960-checker-bounds-codegen\nTest: 449-checker-bce\n\nChange-Id: I6564e4d147a0f40665b37c604487159a9d9aeae5\n" }, { "commit": "9df37b9f0fc2046ceabeea0d0638ac286bfc0f37", "tree": "7f1bf36d2373c6666c24f8a35509f929c7e16944", "parents": [ "92fc2c0241590e475a2a37c9864633b88f97b280" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Tue Jul 23 16:41:54 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jul 31 08:16:27 2019 +0000" }, "message": "ART: ARM64: Fix saved fpu stack offsets for SIMD.\n\nFix the bug when a wrong stack offset was recorded for a FP\nsaved in a SlowPathCode: this happened when graph had SIMD\nloops and some regular FP registers live across a slow path.\n\nTest: test-art-target, test-art-host.\n\nChange-Id: I08b32c9877fcd468dafa6027c156e544d730f1f7\n" }, { "commit": "44ca0754b3c6f11303bac876a9175bbfa95609ef", "tree": "6f669466e6b0e750a075108cc6f8fe0a67b66658", "parents": [ "f3677471a58c2738a3d9dd05f07f01c18a5e61be" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jul 29 10:18:25 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 30 14:49:54 2019 +0000" }, "message": "Compiler changes for boot image extension.\n\nTest: m test-art-host-gtest\nTest: testrunnner.py --host --optimizing\nTest: aosp_taimen-userdebug boots.\nTest: run-gtest.sh\nTest: testrunner.py --target --optimizing\nChange-Id: I8e999c96ec908f26d8c529edc9d2a3be49a9379a\n" }, { "commit": "bf12191214c0d6215a98dfe846a51230d995dad9", "tree": "085c1059014ce66fdb7eceb6e8502d906f0eacbd", "parents": [ "78342419743cb6d0f17dc2d4c0cd99d18d9c83d6" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 04 13:49:05 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jul 26 11:10:26 2019 +0000" }, "message": "Implement ClassStatus::kVisiblyInitialized.\n\nPreviously all class initialization checks involved a memory\nbarrier to ensure appropriate memory visibility. We change\nthat by introducing the kVisiblyInitialized status which can\nbe checked without a memory barrier. Before we mark a class\nas visibly initialized, we run a checkpoint on all threads\nto ensure memory visibility. This is done in batches for up\nto 32 classes to reduce the overhead.\n\nAvoiding memory barriers in the compiled code reduces code\nsize and improves performance. This is also the first step\ntoward fixing a long-standing synchronization bug 18161648.\n\nPrebuilt sizes for aosp_taimen-userdebug:\n - before:\n arm/boot*.oat: 19150696\n arm64/boot*.oat: 22574336\n oat/arm64/services.odex: 21929800\n - after:\n arm/boot*.oat: 19134508 (-16KiB)\n arm64/boot*.oat: 22553664 (-20KiB)\n oat/arm64/services.odex: 21888760 (-40KiB)\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_taimen-userdebug boots\nTest: run-gtests.sh -j4\nTest: testrunner.py --target --optimizing\nTest: Manually diff `m dump-oat-boot` output from before\n with output after this CL without codegen changes,\n with `sed` replacements for class status. Check that\n only checksums and the oatdump runtime values of\n DexCache.dexFile differ.\nBug: 18161648\nBug: 36692143\nChange-Id: Ida10439d347e680a0abf4674546923374ffaa957\n" }, { "commit": "1a225a76ee6bc29833aee048b6cfae20242bdc8b", "tree": "069bfc01d827fcbf9aa4415c4d63d354648f396c", "parents": [ "323844002e54243e295497e7f829e46a533da621" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jul 05 13:37:42 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 18 13:37:15 2019 +0000" }, "message": "ARM/ARM64: Improve frame entry/exit codegen.\n\nOn ARM64, use STP pre-index for the method and the lowest\nspilled core register for method entry if there\u0027s no gap or\nFP spills in between. On exit, use LDP post-index to restore\nin this case, ignoring the method by loading to XZR. Thus,\nwe save one instruction for both entry end exit for such\nmethods and the performance should be the same or better.\n\nOn ARM, use a single PUSH/POP for method entry and core\nspills if the gap between them is 2 words or less and and we\nhave one or no FP spill, spill args as filler if needed. On\nexit, load the FP spill if any and do a single POP for core\nregisters and return in this situation, clobbering as many\nregisters from r2-r4 as needed; these caller-save registers\nare not used to pass return values. If we cannot do this\nbecause of FP spills but the gap between the method and FP\nspills is 2 words or less, we adjust SP and save the method\nin one PUSH after spilling; there is no similar handling\nfor method exit as the method does not need to be restored.\nThis may improve or degrade performance a bit depending on\nthe particular situation; in the worst case we PUSH/POP\nthree additional registers as a cost for smaller code size.\n\naosp_taimen-userdebug prebuils:\n - before:\n arm/boot*.oat: 19147484\n arm64/boot*.oat: 22558344\n oat/arm/services.odex: 21922256\n - after:\n arm/boot*.oat: 19105436 (-41KiB, -0.2%)\n arm64/boot*.oat: 22549624 (-9KiB, -0.04%)\n oat/arm/services.odex: 21914128 (-8KiB, -0.04%)\n\nTest: aosp_taimen-userdebug boots.\nTest: run-gtests.sh\nTest: testrunner.py --target --optimizing\nBug: 136144107\nChange-Id: Id36c67b4e735418fb18bcd3269b72b25695fbaa2\n" }, { "commit": "2d06e029b1c84916154b5960d2acd1c84706dc04", "tree": "31dca979adebd2ed3a058b23a12a3c91ce2874d1", "parents": [ "7cde45800e21c270945b43a8989334ffc7422c32" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jul 08 15:45:19 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 16 08:22:46 2019 +0000" }, "message": "Clean up linker patches in codegens.\n\nIn preparation for introducing boot image extension, make\nsure that we can use both kBootImageLinkTimePcRelative and\nkBootImageRelRo load kinds at the same time.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_taimen-userdebug boots\nTest: run-gtests.sh\nTest: testrunner.py --target --optimizing\nChange-Id: I340f2d7d19e1c20699b37b0304d2e487d497da98\n" }, { "commit": "d5fd5c3bbb44880e440c6920ce5ed56b5383c788", "tree": "2cf8a6354e5509c5a5e0bc2937c24fe7e03a12b1", "parents": [ "1a6f9fcce199f437a5945dfe0163188b923adb28" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 02 14:46:32 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 04 08:17:30 2019 +0000" }, "message": "Make .bss stores atomic release operations.\n\nAnd rely on architecture-dependent behavior for the .bss\nentry loads.\n\nThis fixes theoretical races when one thread updates the\n.bss entry and another uses it immediately thereafter;\npreviously we did not ensure correct memory visibility.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_taimen-userdebug boots.\nTest: run-gtests.sh\nTest: testrunner.py --target --optimizing\nChange-Id: Ie7b7969eb355025b9c9205f8c936e702861943f4\n" }, { "commit": "f667508a2103cfafd1582df6aeea144490f1d11d", "tree": "7394cec1f1463a86deb75dcecca9f3eacd8ecb03", "parents": [ "8fa839cfe6f72adabdf79f938c57300e589e0803" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri May 17 12:05:28 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 23 11:47:28 2019 +0000" }, "message": "ARM/ARM64: Use trampolines for slow-path entrypoint calls.\n\nThis reduces the size of the generated code. We do this only\nfor AOT compilation where we get the most benefit.\n\nSizes of aosp_taimen-userdebug prebuilts:\n - before:\n arm/boot*.oat: 19624804\n arm64/boot*.oat: 23265752\n oat/arm64/services.odex: 22417968\n - after:\n arm/boot*.oat: 19460500 (-160KiB)\n arm64/boot*.oat: 22957928 (-301KiB)\n oat/arm64/services.odex: 21957864 (-449KiB)\n\nTest: m test-art-host-gtest\nTest: aosp_taimen-userdebug boots.\nTest: run-gtests.sh\nTest: testrunner.py --target --optimizing\nBug: 12607709\nChange-Id: Ie9dbd1ba256173e4e439e8bbb8832a791965cbe6\n" }, { "commit": "8fa839cfe6f72adabdf79f938c57300e589e0803", "tree": "b940832441ef1b0c724c1383228225845e5d72d1", "parents": [ "3cddf4538a8df429a6084f7176c07d55e1e0ec67" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 16 12:50:47 2019 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 23 11:47:28 2019 +0000" }, "message": "Revert^2 \"Improve ArraySet codegen.\"\n\nThis reverts commit 0dda8c84938d6bb4ce5a1707e5e109ea187fc33d.\n\nThe original change had two issues that have been fixed.\nFirst, for heap poisoning, the null branch skipped over the\nreference poisoning instructions which copy and poison the\nvalue, thus writing whatever was left in the register.\nSecond, the change erroneously assumed that the slow path\nperformed only the assignability check and bound the slow\npath exit label before the actual array store, unnecessarily\nre-doing the store.\n\nChange-Id: I9f380efa12aa807b4f566a932dbc9dae824fb25a\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_taimen-userdebug boots.\nTest: testrunner.py --target --optimizing\nTest: Repeat the above with\n ART_USE_READ_BARRIER\u003dfalse ART_HEAP_POISONING\u003dtrue\nBug: 32489401\n" }, { "commit": "552a13415573da19eafa46e1ac00fb0eb68f2b23", "tree": "8cae5f3602d8f8e65cd3cbc349af17d785128605", "parents": [ "0dda8c84938d6bb4ce5a1707e5e109ea187fc33d" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Oct 31 10:56:47 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 16 14:44:09 2019 +0000" }, "message": "ART: Optimize StringBuilder append pattern.\n\nRecognize appending with StringBuilder and replace the\nentire expression with a runtime call that perfoms the\nappend in a more efficient manner.\n\nFor now, require the entire pattern to be in a single block\nand be very strict about the StringBuilder environment uses.\nAlso, do not accept StringBuilder/char[]/Object/float/double\narguments as they throw non-OOME exceptions and/or require a\ncall from the entrypoint back to a helper function in Java;\nthese shall be implemented later.\n\nBoot image size for aosp_taimen-userdebug:\n - before:\n arm/boot*.oat: 19653872\n arm64/boot*.oat: 23292784\n oat/arm64/services.odex: 22408664\n - after:\n arm/boot*.oat: 19432184 (-216KiB)\n arm64/boot*.oat: 22992488 (-293KiB)\n oat/arm64/services.odex: 22376776 (-31KiB)\nNote that const-string in compiled boot image methods cannot\nthrow, but for apps it can and therefore its environment can\nprevent the optimization for apps. We could implement either\na simple carve-out for const-string or generic environment\npruning to allow this pattern to be applied more often.\n\nResults for the new StringBuilderAppendBenchmark on taimen:\n timeAppendLongStrings: ~700ns -\u003e ~200ns\n timeAppendStringAndInt: ~220ns -\u003e ~140ns\n timeAppendStrings: ~200ns -\u003e 130ns\n\nBug: 19575890\nTest: 697-checker-string-append\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_taimen-userdebug boots.\nTest: run-gtests.sh\nTest: testrunner.py --target --optimizing\nTest: vogar --benchmark art/benchmark/stringbuilder-append/src/StringBuilderAppendBenchmark.java\nChange-Id: I51789bf299f5219f68ada4c077b6a1d3fe083964\n" }, { "commit": "0dda8c84938d6bb4ce5a1707e5e109ea187fc33d", "tree": "3d0b4f35ef4d00aa18eba0e417655d43bc44bf5a", "parents": [ "0ece86491008837a9814f7a2e0d7961c74ef4195" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 16 12:47:40 2019 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 16 12:47:40 2019 +0000" }, "message": "Revert \"Improve ArraySet codegen.\"\n\nThis reverts commit 0ece86491008837a9814f7a2e0d7961c74ef4195.\n\nReason for revert: Breaks heap poisoning tests.\n\nBug: 32489401\nChange-Id: Ied4150829eea848d0f967866d87c6aa7dafd39a1\n" }, { "commit": "0ece86491008837a9814f7a2e0d7961c74ef4195", "tree": "590aa02d76255d9e9c4c1329b4a7278c4c8ff018", "parents": [ "3a8ab36cdfc9535bf79057cb9efe787ec8a491d2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 13 11:49:17 2019 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 16 08:23:57 2019 +0000" }, "message": "Improve ArraySet codegen.\n\nSimplify the reference case to emit fewer instructions and\ntake at most one branch in the main path.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: aosp_taimen-userdebug boots.\nTest: testrunner.py --target --optimizing\nBug: 32489401\nChange-Id: I9d76b7795ec01e6245ed3184cd8d384389e5070d\n" }, { "commit": "403aafa9f286e13ee2a64748514d33af39b55ab0", "tree": "fe9e5a5eed0081c2ac03dec0d616ed32d162b99c", "parents": [ "8809c9cd8d7f477e0a74f68537c864e3b7a35db3" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Mar 06 18:04:14 2019 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Mar 12 14:11:25 2019 +0000" }, "message": "Fix non-deterministic compilation for const-string...\n\n... in inlined methods that are not in the boot profile.\nIf such string is not in the boot image for other reasons,\ndo not resolve the string and use the kBssEntry load kind.\n\nBoot image sizes for aosp_taimen-userdebug:\n - before:\n arm/boot*.art: 12349440\n arm/boot*.oat: 19862024\n arm64/boot*.art: 16609280\n arm64/boot*.oat: 23568592\n - after:\n arm/boot*.art: 12324864 (-24KiB)\n arm/boot*.oat: 19936612 (+73KiB)\n arm64/boot*.art: 16580608 (-28KiB)\n arm64/boot*.oat: 23642120 (+72KiB)\n\nTest: aosp_taimen-userdebug boots.\nTest: m test-art-host-gtest\nBug: 26687569\nChange-Id: I3e0b72cd5e8c67904517856208f25a6c379ab601\n" }, { "commit": "3db70689e3e1c92344d436a8ea4265046bdef449", "tree": "3db08743e968062ed5bdc143233cdb3c4564696b", "parents": [ "1650dafad62578a1766bd617d78458a4cf1e2a9a" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Dec 26 15:12:03 2018 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Dec 27 12:56:39 2018 -0800" }, "message": "ART: Refactor for bugprone-argument-comment\n\nHandles compiler.\n\nBug: 116054210\nTest: WITH_TIDY\u003d1 mmma art\nChange-Id: I5cdfe73c31ac39144838a2736146b71de037425e\n" }, { "commit": "aa6f48362b3258a5df5e527987ffe7e068eb4a79", "tree": "0fa8cfbebb77d2e7796084721c836b44114bdc97", "parents": [ "8bda21f1d8bbc1060bf693f5d1666d3396d1cb69" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Wed Nov 21 18:57:54 2018 +0000" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Mon Dec 03 18:43:48 2018 +0000" }, "message": "ART: ARM64: Pass ISA features to VIXL macroassembler.\n\nVIXL macroassembler should be initialized properly\nto support Armv8.X features in order to emit corresponding\ninstructions.\n\nTest: codegen_test.cc, relative_patcher_arm64_test.\nTest: test-art-host, test-art-target.\nChange-Id: I2f9e155c28b4d2252a3cfb19717f5d25824d5e11\n" }, { "commit": "c1896c9a0e15df3a1b9a3a19bcd2a933b654fe06", "tree": "b68a5f5163f8da0da87d671a225addaa2a13095f", "parents": [ "f2970cd870948a6ee1c8ecd30c9c3147d05aa0be" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Thu Nov 29 11:33:18 2018 -0800" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Thu Nov 29 11:33:18 2018 -0800" }, "message": "C++17 compatibility: make WITH_TIDY\u003d1 happy again.\n\nBug: http://b/111067277\nTest: builds\nChange-Id: I8b69ea3815e14bb6eb27f40c0dd01a85b340a355\n" }, { "commit": "57e7dbfbe34188de05f90bb0ec8520ba66383149", "tree": "1dbbfaa1d0afbc44cbb429ba72b65db37efd8ed6", "parents": [ "4fc843c4fc9f33c4ba49c1303d526d0e0e6a3788", "0806f589a8a8e1fca573069b37761c320660aa63" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Nov 06 17:13:01 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Nov 06 17:13:01 2018 +0000" }, "message": "Merge \"ARM64: Support interm. address for object arrays.\"" }, { "commit": "0806f589a8a8e1fca573069b37761c320660aa63", "tree": "51a26fc5e59cca70a3f6875ece57aee39962221f", "parents": [ "02338775e33b553be51d44ff60bb1ef8e527bd94" ], "author": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Oct 11 20:14:20 2018 +0100" }, "committer": { "name": "Artem Serov", "email": "artem.serov@linaro.org", "time": "Thu Oct 25 18:33:55 2018 +0100" }, "message": "ARM64: Support interm. address for object arrays.\n\nSupport IntermediateAddress on arm64 for object\narray reads in Baker read barrier configuration.\n\nThe patch brings minor boot.oat size reduction and\nperformance improvement on Puzzle benchmark.\n\nTest: test-art-target, test-art-host, gc_stress.\nTest: 527-checker-array-access-split.\n\nBug: 26601270\nBug: 32578862\n\nChange-Id: I781a911905038b36428964a990771fdf74e99bbd\n" }, { "commit": "fe89f170fd454188902ae0b80e08c0888158c60e", "tree": "3862cd1e16d25696505da841c127f13e0e08fdfd", "parents": [ "5314caec5a2c61fa96a2d6ee134706c085c18b11", "bd8e10c586fca1c99f29eff27f66d483a18b0ccf" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Oct 25 11:51:43 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Oct 25 11:51:43 2018 +0000" }, "message": "Merge \"Block the platform register, x18.\"" }, { "commit": "b546163926889130354ccdbcccb80c0331c13f3c", "tree": "b4a3fb30e11e2abc671fb0b4b8098acd8fc49ce2", "parents": [ "8db807252e1d4d0bab7785be231e20a1e5fd8e74" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Oct 15 14:24:21 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Oct 16 10:47:24 2018 +0100" }, "message": "Fix HNewArray with unresolved primitive array type.\n\nAnd enable test 920-objects that was crashing because\nof this bug.\n\nTest: testrunner.py --host --jit-on-first-use -t 920\nTest: testrunner.py --host --optimizing\nTest: m test-art-host-gtest\nBug: 117638896\nChange-Id: I47dc893b121c82de537b3147c86d37a6eecf2d62\n" }, { "commit": "a2da9b99fa1ea3d25d52da71308a623b2aae216c", "tree": "5533be23eee7c24b68b1b72272cbae3f35a708cb", "parents": [ "dc3b4670b170b39a8bd6498d4de69c1513af1db2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 10 14:21:55 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Oct 10 15:25:26 2018 +0100" }, "message": "ART: Completely remove the --compile-pic option.\n\nAnd the PIC-related fields from image header.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nBug: 77856493\nChange-Id: I3787369378f12d8cd9003bebeae62830a67def33\n" }, { "commit": "bdb2ecc8cfd0d6fc2f3f4fa4c65cca84b358cd61", "tree": "a7660c98c22d28bf508fe208845957418e0dee40", "parents": [ "4bd4d2c199c9e0e522526c40303652e29bc7c631" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Sep 18 14:33:55 2018 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Sep 19 14:46:04 2018 +0100" }, "message": "Remove sharpening as an optimization pass.\n\nMake the last sharpening helper (methods) like the other\nhelpers: being invoked by the instruction builder.\n\nTest: test.py\nChange-Id: Ic80a454f9b59b0b4ef7825590b24402500ba851c\n" }, { "commit": "bd8e10c586fca1c99f29eff27f66d483a18b0ccf", "tree": "ac228db5c0a3cbcc82c665bd2c1653d7e351c09e", "parents": [ "4613c8a3a549213240f3ffc46514b600d872938e" ], "author": { "name": "Peter Collingbourne", "email": "pcc@google.com", "time": "Thu Apr 12 16:39:55 2018 -0700" }, "committer": { "name": "Peter Collingbourne", "email": "pcc@google.com", "time": "Thu Sep 06 01:18:33 2018 +0000" }, "message": "Block the platform register, x18.\n\nBug: 77982665\nTest: run-libcore-tests.sh, sailfish boots\nChange-Id: I5bc4c77f76bb6747a002bff2e16d83c679beeb32\n" }, { "commit": "bbc6e7edb5fca4a61ac53dd9bce79cb4f0bb3403", "tree": "0fbce767bc383358cf4cd65aafc74140e1850982", "parents": [ "19379b58bd433da91230e4fe6cd96e7416d16adc" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Aug 24 16:58:47 2018 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Aug 28 11:06:07 2018 +0100" }, "message": "Use \u0027final\u0027 and \u0027override\u0027 specifiers directly in ART.\n\nRemove all uses of macros \u0027FINAL\u0027 and \u0027OVERRIDE\u0027 and replace them with\n\u0027final\u0027 and \u0027override\u0027 specifiers. Remove all definitions of these\nmacros as well, which were located in these files:\n- libartbase/base/macros.h\n- test/913-heaps/heaps.cc\n- test/ti-agent/ti_macros.h\n\nART is now using C++14; the \u0027final\u0027 and \u0027override\u0027 specifiers have\nbeen introduced in C++11.\n\nTest: mmma art\nChange-Id: I256c7758155a71a2940ef2574925a44076feeebf\n" }, { "commit": "75eec5d14039d4cbc4ec9b96485b743573665627", "tree": "db9e4158d5cbfb84d2f0c0f6157e5b0edad8587a", "parents": [ "d3678dc2531f95ced2d015b800ecd9018ce96c73", "61ba8d2421a98e9b16510be4f9af7ca7bc4c9055" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Aug 24 14:07:24 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 24 14:07:24 2018 +0000" }, "message": "Merge \"Fix longstanding bug around implicit NPEs and GC, version 2.\"" }, { "commit": "61ba8d2421a98e9b16510be4f9af7ca7bc4c9055", "tree": "9a79331dd5ebd46ed46f853b24ab072f43debf28", "parents": [ "eb369ce3669be74dd89b21f8b3ab31ace4a47086" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Aug 07 09:55:57 2018 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Aug 20 17:18:31 2018 +0100" }, "message": "Fix longstanding bug around implicit NPEs and GC, version 2.\n\nThe TODO has been there since M (so forever :)):\nhttps://android-review.googlesource.com/c/platform/art/+/122794/13//COMMIT_MSG#13\n\nWe hardly see the issue in our tests as we need to have:\n1) A GC happening while creating the NPE object.\n2) ParallelMoves between the NullCheck and implicit null check operation\n that moves references.\n\nThe CL piggy backs on the \"IsEmittedAtUseSite\" flag, to set implicit\nnull checks with it. The liveness analysis then special cases implicit\nnull checks to record environment uses at the location of the actual\ninstruction that will do the implicit null check.\n\nTest: test.py --gcstress\nTest: run-libcore-tests --gcstress\nbug: 111545159\nChange-Id: I3ecea4fe0d7e483e93db83281ca10db47da228c5\n" }, { "commit": "14e5a29a8c5dcd971376a4a04b3c3b05100b3f86", "tree": "81c607cde36b6481ed2cd2d8b41293f62a5521f8", "parents": [ "e0943873483cb2169e5360e1f746931a3371aa24" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jun 28 12:00:56 2018 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Aug 14 18:01:43 2018 +0100" }, "message": "Rename art::ReadBarrier::WhiteState as art::ReadBarrier::NonGrayState.\n\nThe read barrier state recorded in object\u0027s lockword used to be a\nthree-state value (white/gray/black), which was turned into a\ntwo-state value (white/gray), where the \"black\" state was conceptually\nmerged into the \"white\" state. This change renames the \"white\" state\nas \"non-gray\" and adjusts corresponding comments.\n\nTest: art/test.py\nChange-Id: I2a17ed15651bdbbe99270c1b81b4d78a1c2c132b\n" }, { "commit": "e0943873483cb2169e5360e1f746931a3371aa24", "tree": "c5fdf8d02f8bb23218513c9159090ff783df0ef0", "parents": [ "6e1faf4af246ebfb05505cebd8ca0db48aa3bae6", "c73f05242a6688c8edec46c1ff257a1efbd4b519" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Aug 14 16:55:40 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Aug 14 16:55:40 2018 +0000" }, "message": "Merge \"Document the use of the biased card table in ART\u0027s code generators.\"" }, { "commit": "94796f8e1b1d920c6107ffddf4efdabcf85e1da4", "tree": "e6c068b622bc60b1570eb1c54d3ddeea4972b1a2", "parents": [ "248141f724cbb9d436f13181b5301172c4385cc2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 08 15:15:33 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 14 16:36:39 2018 +0100" }, "message": "ARM64: Reimplement the UnsafeCASObject intrinsic.\n\nFor the UnsafeCASObject with Baker read barriers, drop the\nold code updating the field. Perform the main path CAS loop\nand redirect the flow for failure to a slow path that marks\nthe old value and compares it with the expected value (if\nnot marking, this is just a few instructions to determine\nthat they differ). If it\u0027s the same, the old value is known\nto be the from-space reference to the expected object and\nthe slow path performs a modified CAS loop checking for both\nexpected object references (from-space and to-space).\n\nTest: Already covered by the 160-read-barrier-stress.\nTest: m test-art-host-gtest\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --64\nTest: ART_HEAP_POISONING\u003dtrue testrunner.py --target --optimizing --64\nBug: 36141117\nChange-Id: I175806dbc003640c9bb6759be6788311bcc9310c\n" }, { "commit": "c73f05242a6688c8edec46c1ff257a1efbd4b519", "tree": "68b95952ec9710da3aabf7a686725692a9fd5cf5", "parents": [ "9e113dd00d94526d7e6e546ac9bd4f066db3a019" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Aug 14 15:16:50 2018 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Aug 14 15:20:33 2018 +0100" }, "message": "Document the use of the biased card table in ART\u0027s code generators.\n\nTest: n/a\nChange-Id: Ie03a6f6dc87fd0766fc2b685ec39a0a0ebe3fb57\n" }, { "commit": "248141f724cbb9d436f13181b5301172c4385cc2", "tree": "8828a0e319fa692c4a80e8cecadff7b68a845faa", "parents": [ "6e99db490fabbc38d96cc618a7aa82a99b3d07cf" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 10 10:40:07 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 10 13:05:12 2018 +0100" }, "message": "ARM/ARM64: Introspection Baker RB for intrinsics.\n\nNamely Unsafe.getObject/-Volatile().\n\nTest: Additional tests in 160-read-barrier-stress.\nTest: m test-art-host-gtest\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nTest: ART_HEAP_POISONING\u003dtrue testrunner.py --target --optimizing\nBug: 36141117\nChange-Id: I7305d75ab0ae8c9621843f9a382ad3a5e0aefa0b\n" }, { "commit": "0ecac681bd0f55fad16027fe341f55edd632e3db", "tree": "016727b357ef37b9be41451359f5ca1c1edea8dd", "parents": [ "008e09f35541bcce782cd172d0745b802a720033" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 07 10:40:38 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 07 16:27:17 2018 +0100" }, "message": "ARM64: Introspection Baker RB for volatile fields.\n\nTest: Already covered by 160-read-barrier-stress.\nTest: m test-art-host-gtest\nTest: Pixel 2 XL boots.\nTest: m test-art-target-gtest\nTest: testrunner.py --target --optimizing --jit --64\nBug: 36141117\nChange-Id: I2f9a707587d1ee27c0efb19d77becba7ec7ffec4\n" }, { "commit": "008e09f35541bcce782cd172d0745b802a720033", "tree": "8a75f77ac9f24196763038a53208266d70e3b584", "parents": [ "f5705e3502183e6dfd03facada5f5cbfab116ec7" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Aug 06 15:42:43 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Aug 06 18:05:05 2018 +0100" }, "message": "ARM/ARM64: Clean up Baker RB introspection codegen.\n\nRemove the guard flags and remove unused code.\n\nAvoid unnecessary temporaries for JIT. This was missed in\n https://android-review.googlesource.com/725705\n\nTest: m test-art-host-gtest\nTest: Pixel 2 XL boots.\nTest: m test-art-target-gtest\nTest: testrunner.py --target --optimizing --jit\nBug: 36141117\nChange-Id: Ic1bdc640db3f18d7169b0e62644f190e65a98d38\n" }, { "commit": "a21eca6a7ddc7f986651261359f821771494c61e", "tree": "5afeffa6ea8384ab50e3e4f87c6b76d195b13134", "parents": [ "d925742e6c52237a262b4430f8b6b679ff1cc80e", "966b46fcba43764267069b6e19bcb2a092260418" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 03 16:41:58 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 03 16:41:58 2018 +0000" }, "message": "Merge \"Revert^2 \"ARM/ARM64: Use introspection marking for JITted code.\"\"" }, { "commit": "9d479254d0dc4043a15ab26205f40439eca15493", "tree": "af8a9c9c6f2c28e723a971c9d39c9d1cebd1f814", "parents": [ "ca20fb6cc4dda392e63bdc8ec9de54d89793373e" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 24 11:35:20 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 03 11:43:30 2018 +0000" }, "message": "Rename type resolution entrypoints.\n\nRename the InitializeType and InitializeTypeAndVerifyAccess\nentrypoints to Resolve* to better match their semantics.\nKeep the InitializeStaticStorage name for now as the most\nappropriate name InitializeType would clash with the old\nname of the ResolveType entrypoint.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nChange-Id: Ide55b58c490d085ab37d8536f90699f7ed571d59\n" }, { "commit": "966b46fcba43764267069b6e19bcb2a092260418", "tree": "fe89667cbb09a981e67ebd1196d324038a6413ff", "parents": [ "98afa11c3cd8517bd28d1cad7aacaf0179c905f0" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 03 10:20:19 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 03 12:35:34 2018 +0100" }, "message": "Revert^2 \"ARM/ARM64: Use introspection marking for JITted code.\"\n\nThis reverts commit 756e722c323c69a7c9891892602730e9c94b78f9.\n\nFix the introspection code to avoid avoid macro instructions\nfor unpoisoning references inside ExactAssemblyScope.\n\nChange-Id: I6effadb84de74aba0236ab84b52ca85770daf5be\nTest: m test-art-host-gtest\nTest: Pixel 2 XL boots.\nTest: m test-art-target-gtest\nTest: testrunner.py --target --optimizing --jit\nTest: ART_HEAP_POISONING\u003dtrue m test-art-target-gtest\nTest: ART_HEAP_POISONING\u003dtrue testrunner.py --target --optimizing --jit\nBug: 36141117\n" }, { "commit": "3232dbb6df866985089b13a36c56e2b39dd473ab", "tree": "055f3e8888bfb3cfd072a981e4733cfaad7b202c", "parents": [ "b27d874ebc0c067d96994a6ebe3c10eaeb2e4a75" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jul 25 15:42:46 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 03 08:59:07 2018 +0000" }, "message": "Do not save/restore regs in ClinitCheck slow path.\n\nThe entrypoint is kSaveEverything, so the only register that\nneeds to be saved is the argument/return value register.\n\nThe size of the aosp_taimen-userdebug prebuilts:\n - before:\n arm/boot*.oat: 16811692\n arm64/boot*.oat: 19801032\n oat/arm64/services.odex: 20232208\n - after:\n arm/boot*.oat: 16798804 (-12.6KiB, -0.08%)\n arm64/boot*.oat: 19804392 (+3.3KiB, +0.02%)\n oat/arm64/services.odex: 20227784 (-4.3KiB, -0.02%)\nNote that though there is less code, the metadata for the\narm64/boot*.oat outweighs the code size reduction because of\nthe register map encoding as value+shift introduced in\n https://android-review.googlesource.com/695682\nwhich it\u0027s ill-suited for kSaveEverything entrypoints. We\nshould reconsider that encoding.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nChange-Id: I5cd1deb90332a3b88a0a59d87925c557d9bff1ab\n" }, { "commit": "b27d874ebc0c067d96994a6ebe3c10eaeb2e4a75", "tree": "3084a0b326e98115f5d0621362d5b7c368775669", "parents": [ "8f5992d8c81d4d9a0805c649cdcf859328d5c1b6", "a9f303c089aa2b2fc82d97201352945678ef54ae" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 03 08:57:16 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Aug 03 08:57:16 2018 +0000" }, "message": "Merge \"Rewrite Class init entrypoint to take a Class arg.\"" }, { "commit": "756e722c323c69a7c9891892602730e9c94b78f9", "tree": "a2bf360d95f0aef84f3bce43f43871910a0b7ed9", "parents": [ "450f1d0fa0c40198e63c3e016f02e40ac854b0cb" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Aug 02 17:53:46 2018 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Aug 02 17:53:46 2018 +0000" }, "message": "Revert \"ARM/ARM64: Use introspection marking for JITted code.\"\n\nThis reverts commit 450f1d0fa0c40198e63c3e016f02e40ac854b0cb.\n\nReason for revert: breaks poisoning configuration\n\nBug: 36141117\nChange-Id: I198c20ca1db6d7d7602aa5318616e2b149de8772\n" }, { "commit": "a9f303c089aa2b2fc82d97201352945678ef54ae", "tree": "0df0eb5294a3ee72aea8ca670762c02ca9ffa8dd", "parents": [ "1bfd891d06e276d602b4a6ccf1a9f70967195218" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jul 20 16:43:56 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Aug 02 17:41:21 2018 +0100" }, "message": "Rewrite Class init entrypoint to take a Class arg.\n\nFixes invalid type index being passed to the entrypoint for\nclass init check across dex files when the target type does\nnot have a TypeId in the compilation unit\u0027s DexFile.\n\nThe size of the aosp_taimen-userdebug prebuilts:\n - before:\n arm/boot*.oat: 16782748\n arm64/boot*.oat: 19764400\n oat/arm64/services.odex: 20162432\n - after:\n arm/boot*.oat: 16811692 (+28.3KiB, +0.17%)\n arm64/boot*.oat: 19801032 (+35.8KiB, +0.19%)\n oat/arm64/services.odex: 20232208 (+68.1KiB, +0.35%)\nThis increase comes from doing two runtime calls instead of\none for HLoadClass/kBssEntry that MustGenerateClinitCheck().\n\nTest: Additional test in 476-clinit-inline-static-invoke\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --jit\nTest: testrunner.py --jvm\nBug: 111433619\nChange-Id: I2fccd6944480ab4dac514f60d38e72c1014ae7b2\n" }, { "commit": "450f1d0fa0c40198e63c3e016f02e40ac854b0cb", "tree": "0606a5c722be0d706242c015cb1218021c5c1309", "parents": [ "da6220a29fae95f17edd5374dc6bc2d4870a84da" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 25 17:27:45 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jul 25 18:34:19 2018 +0100" }, "message": "ARM/ARM64: Use introspection marking for JITted code.\n\nImpact on Golem benchmarks is within noise.\n\nTest: m test-art-host-gtest\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --jit\nBug: 36141117\nChange-Id: Idf5177ee5cd34e2034d298a7907240b3e3e12d82\n" }, { "commit": "bd39d145e4986217bcb8dce1d4a9631d926a2781", "tree": "52dfd3307ab5279e960f9a1bf6e474e47440a3d8", "parents": [ "6f4cf6e8fa15de2f9bf7c6a649ea7a2fabef886a" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jul 19 11:14:42 2018 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jul 19 11:37:05 2018 -0700" }, "message": "ART: Clean up unused using declarations\n\nMake tidy happy, and enable checking.\n\nTest: mmma art\nChange-Id: I9e18e80b3f37dd2aeb8ecd1c25abe4d5cf2f1c45\n" }, { "commit": "59d0872519e8abd1ec17003c17b5c3780ed831df", "tree": "718c0ff45c67d962a822527ae003eb75e720c4a4", "parents": [ "79deffcd99bb3c87ea1c2c36509ef156d4010b2e", "8e524ad3c690c183b1a71f6114796974a107c5dd" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Jul 19 15:18:47 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 19 15:18:47 2018 +0000" }, "message": "Merge \"Always produce PIC code for AOT compilation.\"" }, { "commit": "8e524ad3c690c183b1a71f6114796974a107c5dd", "tree": "6ee124814e8f33fd4706eb15fcad2cae0019546b", "parents": [ "5991b184a40e4ce181d67d683ced46caa6143b53" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jul 13 10:27:43 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jul 16 10:12:51 2018 +0100" }, "message": "Always produce PIC code for AOT compilation.\n\nChange sharpening to use PIC load kinds for AOT compilation\nand add \"Jit\" to the direct addressing load kind names. Use\nPIC code also for the Integer.valueOf() intrinsic codegen.\nRemove all support for non-PIC linker patches.\n\nThe dex2oat --compile-pic option is retained for now but\nignored by the compiler.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nBug: 77856493\nChange-Id: I54d666f6522f160a1b6ece4045a15d19363acbb6\n" }, { "commit": "f58dc65c52f5e3f15eaaa1e25d7259e64649ade3", "tree": "4485299d9959a658909879b5a234fd807d7627ff", "parents": [ "0b4a439f808f4602c7b97364e49c5546f5100d51" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Mon Jun 25 17:54:07 2018 +0100" }, "committer": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Fri Jul 13 16:30:32 2018 +0100" }, "message": "ART: Delete code optimizing a%1 and a%-1 from InstructionCodeGeneratorARM64\n\nIn InstructionWithAbsorbingInputSimplifier there is code optimizing a%1\nand a%-1. So the code in InstructionCodeGeneratorARM64 optimizing such\ncases can be deleted.\n\nThis patch deletes the code from InstructionCodeGeneratorARM64 and adds\nadditional tests.\n\nTest: 012-math, 014-math3, 411-optimizing-arith, 411-checker-hdiv-hrem-pow2\nTest: 701-easy-div-rem, 442-checker-constant-folding\nTest: test-art-host, test-art-target\nChange-Id: Ib80c0aa4c3e28b07fa79bb43783274c9d7fc456a\n" }, { "commit": "d109e30eab8ba25f8d89be2a83d9036e2d541af2", "tree": "24df91603efe9ce8c4a2efd09ac402aceb10df4e", "parents": [ "c916736ca1e375c276df251446baf2ac8ff3eb13" ], "author": { "name": "Alex Light", "email": "allight@google.com", "time": "Wed Jun 27 10:25:41 2018 -0700" }, "committer": { "name": "Alex Light", "email": "allight@google.com", "time": "Tue Jul 10 08:44:51 2018 -0700" }, "message": "Don\u0027t use StringFactory.newEmptyString in compiled code\n\nWhen compiling debuggable code we would compile a new-instance String\ninstruction into a StringFactory.newEmptyString invoke. This\nadditional invoke could be observed using tracing and is inconsistent\nwith the interpreter, where the string is simply allocated directly.\nIn order to bring these two modes into alignment we added a new\nAllocStringObject quick entrypoint that will be used instead of the\nnormal AllocObject\u003c...\u003e entrypoints when allocating a string. This\nentrypoint directly allocates a new string in the same manner the\ninterpreter does.\n\nNeeds next CL for test to work.\n\nBug: 110884646\nTest: ./test/testrunner/testrunner.py --host --runtime-option\u003d-Xjitthreshold:0 --jit\nTest: Manual inspection of compiled code.\nChange-Id: I7b4b084bcf7dd9a23485c0e3cd2cd04a04b43d3d\n" }, { "commit": "6fd1606a3f3fc2dd53ab4f8b371e420b3e33c74f", "tree": "9f944d267ce3616eb969c027665e4a451c2b3879", "parents": [ "bb089b6bf850c87e0e42917a383cc7298dcb09c5" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 26 11:02:04 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 29 14:39:00 2018 +0100" }, "message": "Implement Integer.valueOf() intrinsic for boot image.\n\nAnd generate only one \"boot image live objects\" array rather\nthan one per boot*.art file.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nBug: 71526895\nChange-Id: I23af7f47fea5150805f801cd2512f2d152ee5b73\n" }, { "commit": "86c84f7edbe58a7a18ac40abba0ef268ed367271", "tree": "84c8c19fd2f50bd9bc385df3ab2a339d908c0ef3", "parents": [ "de4efa65db3c38df49c680159bedf72afcc1fc71", "f9e90541479502840c19274cf4d5b7ff22e51193" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Wed Jun 27 13:18:12 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jun 27 13:18:12 2018 +0000" }, "message": "Merge \"ART: Refactor Int64ConstantFrom to use Int64FromConstant; rename it to Int64FromLocation\"" }, { "commit": "f9e90541479502840c19274cf4d5b7ff22e51193", "tree": "a5ba846c0d493aae7db126ee91d635765250a6e9", "parents": [ "a3234e96206a841c83f9f5bf0d4e14fb07b72a5e" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Mon Jun 25 13:43:53 2018 +0100" }, "committer": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Wed Jun 27 13:24:35 2018 +0100" }, "message": "ART: Refactor Int64ConstantFrom to use Int64FromConstant; rename it to Int64FromLocation\n\nInt64ConstantFrom function duplicates code of the Int64FromConstant. Its\ncode can be replaced with a call: Int64FromConstant(location.getConstant()).\n\nThe patch removes the duplicating code. It also changes the function name to\nInt64FromLocation to be consistent with its usage.\n\nTest: test-art-host, test-art-target\nChange-Id: I5624259aa72523f97ca8fc132a6152f338425c8e\n" }, { "commit": "f07d5617770c37d87447c8bddf105eb0469ab093", "tree": "e6b15b904e591a3b805b292ce9afd9b0cecbf40d", "parents": [ "2dc252e37d4df0c4160cd20b6fc852f5f28b7b87", "a043111e3a2c09b549708a6227a1f54d91da76aa" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jun 27 12:23:54 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jun 27 12:23:54 2018 +0000" }, "message": "Merge \"Move instruction_set_ to CompilerOptions.\"" }, { "commit": "a3234e96206a841c83f9f5bf0d4e14fb07b72a5e", "tree": "b71bab3d76984daa0def172ac9811a1f72c758e7", "parents": [ "a84b53a0a5404f4049f24300dbc81bc859b12105" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Tue Jun 19 23:26:15 2018 +0100" }, "committer": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Wed Jun 27 10:03:49 2018 +0100" }, "message": "ARM64: Optimization of HRem and HDiv when a denominator is power of 2\n\nOn ARM64 when a denominator is a power of 2 fewer instructions can be\nused to represent HDiv and HRem. For example, a/2 can be lowered to\nadd+asr; a%2 to cmp+and+csneg. Currently four instructions\nare always used for the division by a power of 2 and five instructions for the\nremainder.\n\nThis patch optimizes the division by 2 (lowering to two instructions),\nthe remainder from the division by 2 (lowering to three instructions)\nand the remainder from the division by a power of 2 (lowering to four\ninstructions).\n\nOn Pixel 2, performance improvements, geomean of diff for a benchmark group (%),\nmax - the maximum seen diff of a single case in a benchmark group, higher better:\nBig core:\nalgorithm 0.664 (max: 1.6)\nintrinsics 5.813 (max: 19.0)\nmicro 4.734 (max: 22.0)\n\nLittle core:\nalgorithm 2.097 (max: 5.4)\nintrinsics 14.610 (max: 27.3)\nmicro 12.687 (max: 35.6)\n\nTest: 012-math, 014-math3, 411-optimizing-arith, 411-checker-hdiv-hrem-pow2\nTest: test-art-host, test-art-target\nChange-Id: Iaaec6dc8fc0ec5df2b2d0e8692d5dea573b8d284\n" }, { "commit": "a043111e3a2c09b549708a6227a1f54d91da76aa", "tree": "393fe11cfceccebf474e4bdf36ff79b70b97f589", "parents": [ "213ee2da6a1c58d0fc12c937bbd9c9974ca00aca" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 25 09:32:54 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 25 18:43:19 2018 +0100" }, "message": "Move instruction_set_ to CompilerOptions.\n\nRemoves CompilerDriver dependency from ImageWriter and\nseveral other classes.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing\nTest: Pixel 2 XL boots.\nTest: m test-art-target-gtest\nTest: testrunner.py --target --optimizing\nChange-Id: I3c5b8ff73732128b9c4fad9405231a216ea72465\n" }, { "commit": "ccfc88af4ab94ff91f9b241d5113dfe7cb1f2b34", "tree": "68198426ee1a8ff1f4ee06f131be1e75fd961968", "parents": [ "ef3f32487a8a9a8b4272ea5ae372642c721ee41a", "eebb821b1adaf2db7662fc1c3ff4e9fcfe59a694" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 22 09:03:30 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jun 22 09:03:30 2018 +0000" }, "message": "Merge \"Implement Integer.valueOf() intrinsic for PIC.\"" }, { "commit": "bf711e388998c9233b9fc930bcf02511b6943706", "tree": "eeb66747dff7329516d85e29da22795ae51947b7", "parents": [ "5774f57afc997ffe765c32199bd0d5e55d23005a", "878f17d7737a91235013ed16ebe057a12367941b" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jun 21 16:28:30 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jun 21 16:28:30 2018 +0000" }, "message": "Merge \"ARM64: Splitting GenerateDivRem* functions into GenerateIntDiv and GenerateIntRem functions\"" }, { "commit": "eebb821b1adaf2db7662fc1c3ff4e9fcfe59a694", "tree": "a3d3cf5f8c20d03fccdc0808537904da63e74938", "parents": [ "7e56bd41cde4e489a11050d9e340bf8b5692d9e8" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 05 14:57:24 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jun 21 16:12:28 2018 +0100" }, "message": "Implement Integer.valueOf() intrinsic for PIC.\n\nAnd fix the intrinsic for JIT even in case when someone\nmesses up the IntegerCache using reflection. Two cases are\nexposed with a regression test (one that previously failed\nrandomly and one that failed 100%) but other crashes were\npossible; for example, we would need a read barrier for\narray reads when elements are not guaranteed to be in the\nboot image.\n\nThe new approach loads references only from the boot image\nlive objects array which cannot be touched by reflection.\nThe referenced objects and IntegerCache.cache are exposed\nand can lead to weird behavior but not crashes.\n\nOn x86, the pc_relative_fixups_86 actually checks the cache\nan additional time but discrepancies between this check and\nthe location building at the beginning of codegen should be\nOK as the HIsX86ComputeBaseMethodAddress should be added\nfor PIC regardless of whether pc_relative_fixups_86 thinks\nthe method is intrinsified or not.\n\nTest: 717-integer-value-of\nTest: Pixel 2 XL boots.\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --pictest --npictest\nTest: testrunner.py --host --jit\nTest: testrunner.py --target --optimizing --pictest --npictest\nTest: testrunner.py --target --jit\nBug: 71526895\nChange-Id: I89b3245a62aba22980c86a99e2af480bfa250af1\n" }, { "commit": "2227fe49558c5c5fc4820acb2cf357479e74b518", "tree": "bbfb6546c5da802132405569d2f06b459f12a0c3", "parents": [ "111b895dfaa271d8e9c32d1186615a0b73c106b5" ], "author": { "name": "Petre-Ionut Tudor", "email": "petre-ionut.tudor@linaro.org", "time": "Fri Apr 20 17:12:05 2018 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 14 07:42:40 2018 +0000" }, "message": "Small refactor of MIN/MAX compiler code.\n\nIntegrate instruction code generation and location creation with\nHandleBinaryOp. Code generation has been improved for constant\ninputs 0, 1 and -1.\n\nTest: 679-checker-minmax\nTest: test-art-host, test-art-target.\n\nChange-Id: Ib34eb8a4b29d22a2491d21656e1f64011ef9f986\n" }, { "commit": "878f17d7737a91235013ed16ebe057a12367941b", "tree": "f18731e59850baf5d0535a1253643884237e889b", "parents": [ "32e83b36601e080b01712aeb6e9ebaa512eb0f33" ], "author": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Fri Jun 01 16:53:58 2018 +0100" }, "committer": { "name": "Evgeny Astigeevich", "email": "evgeny.astigeevich@linaro.org", "time": "Wed Jun 13 21:47:36 2018 +0100" }, "message": "ARM64: Splitting GenerateDivRem* functions into GenerateIntDiv and GenerateIntRem functions\n\nVisitDiv and VisitRem call GenerateDivRemIntegral.\nGenerateDivRemIntegral does not know whether it is invoked for HDiv or\nHRem and has to check this. As a result all GenerateDivRem* functions\nhave such checks. Code for optimizing HRem and HDiv, e.g. a denominator is\npower of 2, can be specific for HRem or HDiv. So having it in\nGenerateDivRem would create issues with code maintenance.\n\nThis patch split GenerateDivRem* functions into GenerateIntDiv* and\nGenerateIntRem. BTW \u0027Integral\u0027 meaning is not \u0027Integer\u0027. So changed it\nas well. It also removes the case \u0027division by 1 or -1\u0027 because the case\nis handled in InstructionSimplifierVisitor. As there is a commonly used\nfunction Int64ConstantFrom(Location) it is used instead of\nInt64FromConstant(HConstant). This removes some code as well.\n\nTest: 012-math, 014-math3, 411-optimizing-arith\nTest: test-art-host, test-art-target\nChange-Id: I972129b24a206c8230d304be551cd2c18dbc7c9c\n" }, { "commit": "4c8e12e66968929b36fac6a2237ca4b04160161e", "tree": "d8bbfd72a978c69ef2eef98c37e7869673c52295", "parents": [ "20c64f8d802cc575cc9a1a1f6c493a611b23e2ee" ], "author": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Fri May 18 08:33:20 2018 +0100" }, "committer": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Mon Jun 11 10:57:17 2018 +0100" }, "message": "ART: Adds an entrypoint for invoke-custom\n\nAdd support for the compiler to call into the runtime for\ninvoke-custom bytecodes.\n\nBug: 35337872\nTest: art/test.py --host -r -t 952\nTest: art/test.py --target --64 -r -t 952\nTest: art/test.py --target --32 -r -t 952\nChange-Id: I821432e7e5248c91b8e1d36c3112974c34171803\n" }, { "commit": "dbaa5c7ba8935cf87ceb40a4054f9842929e9a51", "tree": "5037625c80cb97a0e13026dc450db28e59ff72ca", "parents": [ "51dda39549033b3c50a7fce5522ffc81325db54b" ], "author": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Thu May 10 08:22:46 2018 +0100" }, "committer": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Fri May 11 11:55:30 2018 +0100" }, "message": "ART: Compiler support for const-method-handle\n\nImplemented as a runtime call.\n\nBug: 66890674\nTest: art/test.py --target -r -t 979\nTest: art/test.py --target --64 -r -t 979\nTest: art/test.py --host -r -t 979\nChange-Id: I67f461c819a7d528d7455afda8b4a59e9aed381c\n" }, { "commit": "18259d7fb7164a5e029df4f883b3a79ccc2403e8", "tree": "ba378bfdef4127bb0607215186e3b150fd38bcdf", "parents": [ "922501b4bbf724e4259477a27764291684eedffb" ], "author": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Thu Apr 12 11:18:23 2018 +0100" }, "committer": { "name": "Orion Hodson", "email": "oth@google.com", "time": "Thu May 10 15:04:09 2018 +0100" }, "message": "ART: Compiler support for const-method-type\n\nImplemented as a runtime call.\n\nBug: 66890674\nTest: art/test.py --target -r -t 979\nTest: art/test.py --target --64 -r -t 979\nTest: art/test.py --host -r -t 979\nChange-Id: I4b3d3969d455d0198cfe122eea8abd54e0ea20ee\n" }, { "commit": "7a69505c2f65aef8f016891456c35475f8264d46", "tree": "3926019c2d1407da1ecba7282ede28bb2c430265", "parents": [ "6c3533991522d036cbb5a656c44f63bf633a2925" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Apr 12 10:26:50 2018 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Apr 12 13:09:38 2018 +0100" }, "message": "Rewrite null checks in read barrier introspection thunks.\n\nRely on the implicit null check in the fast path.\n\nTest: Manual; run-test --gdb 160, break in the introspection\n entrypoint, find the mf.testField0000 read barrier\n code in the caller (this one has a stack map for null\n check, most other reads do not need one), break there,\n step into the thunk, overwrite the base register with\n 0 and observe the NPE being thrown. Repeat with --64.\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing\nBug: 36141117\nChange-Id: I61f879f22f5697a4108f1021eb0e3add742c8755\n" }, { "commit": "ca1e038eb94694f0f1f94ed3781572411c85d365", "tree": "90ad2c2494821c2f3d904eb42e61fbecd7acaf9d", "parents": [ "3f967b25650e44cd61f5a1112727a8218f2b0804" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 11 09:58:41 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 11 11:10:10 2018 +0100" }, "message": "Revert^2 \"Compile link-time thunks in codegen.\"\n\nThe linker crash (the reason for revert) is flaky and maybe\nwe shall not see it with this CL now that unrelated source\ncode has changed.\n\nTest: Rely on TreeHugger\nBug: 36141117\nBug: 77581732\n\nThis reverts commit 5806a9ec99b5494b511e84c74f494f0b3a8ebec5.\n\nChange-Id: I3a4a058847dff601681ba391abf45833424fa06d\n" }, { "commit": "5806a9ec99b5494b511e84c74f494f0b3a8ebec5", "tree": "bb50d00ff0890c2e10f351f462b47b56b01e78ea", "parents": [ "c9dd2207dfdab42586b1d6a5e7f11cf2fcea3a7a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 04 17:23:28 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 04 17:23:28 2018 +0000" }, "message": "Revert \"Compile link-time thunks in codegen.\"\n\nReason for revert: This caused clang linker crash\nin several branches.\n\nBug: 77581732\n\nThis reverts commit c9dd2207dfdab42586b1d6a5e7f11cf2fcea3a7a.\n\nChange-Id: I1923809083cf41c4f19e3e60df03ae80517aaedb\n" }, { "commit": "c9dd2207dfdab42586b1d6a5e7f11cf2fcea3a7a", "tree": "879df31fd10658093b8931117ee617064ce82519", "parents": [ "30a2d9c61da75359dee4ce90236d19fc6341b07a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Nov 23 16:05:19 2017 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Apr 04 10:34:36 2018 +0100" }, "message": "Compile link-time thunks in codegen.\n\nPrepare for experimenting with Baker read barrier marking\nintrospection entrypoints for JIT.\n\nTest: m test-art-host-gtest\nTest: Compare compiled boot*.oat before and after (no diff).\nTest: Pixel 2 XL boots.\nBug: 36141117\nChange-Id: Idb413a31b158db4bf89a8707ea46dd167a06f110\n" }, { "commit": "175e7862dbdb44089ef327fc43ba00c791fd3838", "tree": "7b7ff4327b51b57e47e4b22af8d771edb9d462c1", "parents": [ "77c6fc7341143dd27c74cddd786398688d7b4c91" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Mar 27 09:03:13 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Mar 27 10:04:25 2018 +0100" }, "message": "Revert^4 \"Compiler changes for bitstring based type checks.\"\n\nDisabled the build time flag. (No image version bump needed.)\n\nBug: 26687569\nBug: 64692057\nBug: 76420366\n\nThis reverts commit 3fbd3ad99fad077e5c760e7238bcd55b07d4c06e.\n\nChange-Id: I5d83c4ce8a7331c435d5155ac6e0ce1c77d60004\n" }, { "commit": "3fbd3ad99fad077e5c760e7238bcd55b07d4c06e", "tree": "e8bc33fa60c38f7e1c85f8d4acf6a738df9b426a", "parents": [ "3f41323cc9da335e9aa4f3fbad90a86caa82ee4d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Mar 26 21:14:46 2018 +0000" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Mar 26 21:14:46 2018 +0000" }, "message": "Revert^3 \"Compiler changes for bitstring based type checks.\"\n\nThis reverts commit 3f41323cc9da335e9aa4f3fbad90a86caa82ee4d.\n\nReason for revert: Fails sporadically.\n\nBug: 26687569\nBug: 64692057\nBug: 76420366\nChange-Id: I84d1e9e46c58aeecf17591ff71fbac6a1e583909\n" }, { "commit": "3f41323cc9da335e9aa4f3fbad90a86caa82ee4d", "tree": "ce41c620d2cd411da3c20aa95fb9a69328e77c42", "parents": [ "9ec1e24ebc683b15bb9c6db5554ac2ff9458adae" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Feb 12 18:39:15 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Mar 22 12:12:39 2018 +0000" }, "message": "Revert^2 \"Compiler changes for bitstring based type checks.\"\n\nAdd extra output for debugging failures and re-enable\nthe bitstring type checks.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --jit\nTest: testrunner.py --host -t 670-bitstring-type-check\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --jit\nTest: testrunner.py --target -t 670-bitstring-type-check\nBug: 64692057\nBug: 26687569\n\nThis reverts commit bff7a52e2c6c9e988c3ed1f12a2da0fa5fd37cfb.\n\nChange-Id: I090e241983f3ac6ed8394d842e17716087d169ac\n" }, { "commit": "9992e095643f6746361df03c4c98e742d9ad5899", "tree": "8abf49af54ee57fc0acebf2a3d9cafd87d6ec48e", "parents": [ "a5867bfeb34529dad71220046e7327cef23af207", "e47f60c482648172334aaca59e6c1ab7a3d42610" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Mar 09 10:17:11 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Mar 09 10:17:11 2018 +0000" }, "message": "Merge \"Retrieve String/Class references from .data.bimg.rel.ro.\"" }, { "commit": "8ba5641ddc43fc13cdb0158bd9f3237c4a90a356", "tree": "4dad508f24b675e87dd31ff26e597289a329c5cc", "parents": [ "66f40dbc3e56c7102820842ec49a55b70cf0e151", "b066d43b1d9184899aff32b1f243d092611ad9c6" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Mar 08 17:45:59 2018 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Mar 08 17:45:59 2018 +0000" }, "message": "Merge \"Load ArtMethod* from .data.bimg.rel.ro entries.\"" }, { "commit": "e47f60c482648172334aaca59e6c1ab7a3d42610", "tree": "ae0672b12a6ad200e1c38962c77bccfc3e5cb531", "parents": [ "b066d43b1d9184899aff32b1f243d092611ad9c6" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Feb 21 13:43:28 2018 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Mar 08 10:40:12 2018 +0000" }, "message": "Retrieve String/Class references from .data.bimg.rel.ro.\n\nFor PIC AOT-compiled app, use the .data.bimg.rel.ro to load\nthe boot image String/Class references instead of using the\nmmapped boot image ClassTable and InternTable.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host --optimizing --pictest --npictest\nTest: Pixel 2 XL boots.\nTest: testrunner.py --target --optimizing --pictest --npictest\nBug: 71526895\nChange-Id: Id5703229777aecb589a933a41f92e44d3ec02a3d\n" } ], "next": "b066d43b1d9184899aff32b1f243d092611ad9c6" }