)]}' { "log": [ { "commit": "d43b3ac88cd46b8815890188c9c2b9a3f1564648", "tree": "6c599c3f40d57e92786bd7f41c0541d9eaa2643b", "parents": [ "a109632b240f3c9355ca95500f6f48e4478e3c51" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Wed Apr 01 14:03:04 2015 -0700" }, "committer": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Wed Apr 01 14:05:13 2015 -0700" }, "message": "Revert \"Revert \"Deoptimization-based bce.\"\"\n\nThis reverts commit 0ba627337274ccfb8c9cb9bf23fffb1e1b9d1430.\n\nChange-Id: I1ca10d15bbb49897a0cf541ab160431ec180a006\n" }, { "commit": "b51cdb32acd8b056752375e5f01d243033ec360c", "tree": "c7221ede22a2f7fe6191f34eceb42df63bbd35db", "parents": [ "a3d40d5f764adfde8fa40d826cd93ba36cd15437" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Sun Mar 29 17:32:48 2015 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Mar 30 08:00:37 2015 -0700" }, "message": "ART: Arm32 optimizing compiler backend should honor sdiv\n\nWe still support architectures that do not have sdiv.\n\nIssue: https://code.google.com/p/android/issues/detail?id\u003d162257\nChange-Id: I6d43620b7599f70a630668791a796a1703b62912\n" }, { "commit": "d75948ac93a4a317feaf136cae78823071234ba5", "tree": "7593fb8c1ba2b67decdaa967b6348501f58d8b9d", "parents": [ "b3665e3dfdd23cc7a2f17a0b53bb16205bf4151f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 27 09:53:16 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 27 12:01:40 2015 +0000" }, "message": "Intrinsify String.compareTo.\n\nChange-Id: Ia540df98755ac493fe61bd63f0bd94f6d97fbb57\n" }, { "commit": "39b4bf99a1167cd9d5e5454059dd360e67f1eac1", "tree": "1536a13873faa1031901d003fb987522598c381f", "parents": [ "3679a47027b40290018d0ccc50b996a15645dfef", "ab4a2f5995b79c2b5b28c91b419a2c91cb88e377" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Mar 25 17:15:21 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Mar 25 17:15:22 2015 +0000" }, "message": "Merge changes I4b3b4d90,I70e0d78f,I2848636f\n\n* changes:\n Forbid the use of shifts in ShifterOperand in Thumb2\n Make subs and adds alter flags when rn is an immediate\n Inline long shift code\n" }, { "commit": "b2bd1c5f9171f35fa5b71ada42d1a9e11189428d", "tree": "db9165b3daa18d1d430b690b78c2d125bade3021", "parents": [ "11e99b19f48576f1bb6d0993635b34b6e09c9832" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Wed Mar 25 11:17:37 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Wed Mar 25 12:30:26 2015 +0000" }, "message": "ART: Formatting and comments in BooleanSimplifier\n\nChange-Id: I9a5aa3f2aa8b0a29d7b0f1e5e247397cf8e9e379\n" }, { "commit": "fd18f5ac060365286616cce773f8702d6246e4ca", "tree": "23f63ca2dddadd2da573b027d6a7b632235a3b7f", "parents": [ "72fad8dd9653c4c79b8a43f4c1d466282ec80cc6" ], "author": { "name": "Guillaume \"Vermeille\" Sanchez", "email": "guillaumesa@google.com", "time": "Wed Mar 11 14:57:40 2015 +0000" }, "committer": { "name": "Guillaume \"Vermeille\" Sanchez", "email": "guillaumesa@google.com", "time": "Wed Mar 25 10:19:26 2015 +0000" }, "message": "Inline long shift code\n\nChange-Id: I2848636f892e276507d04f4313987b9f4c80686b\n" }, { "commit": "46e2a3915aa68c77426b71e95b9f3658250646b7", "tree": "2b0a4470b05291894db73c631fe94f0fdff8c46b", "parents": [ "bce0855ca1dbb1fa226c5b6a81760272ce0b64ef" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Mar 16 17:31:52 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Mar 24 17:28:37 2015 +0000" }, "message": "ART: Boolean simplifier\n\nThe optimization recognizes the negation pattern generated by \u0027javac\u0027\nand replaces it with a single condition. To this end, boolean values\nare now consistently assumed to be represented by an integer.\n\nThis is a first optimization which deletes blocks from the HGraph and\ndoes so by replacing the corresponding entries with null. Hence,\nexisting code can continue indexing the list of blocks with the block\nID, but must check for null when iterating over the list.\n\nChange-Id: I7779da69cfa925c6521938ad0bcc11bc52335583\n" }, { "commit": "0ba627337274ccfb8c9cb9bf23fffb1e1b9d1430", "tree": "0e1d0813c1d8d1c7239a900c1653296975713df0", "parents": [ "e295e6ec5beaea31be5d7d3c996cd8cfa2053129" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Mar 24 02:39:46 2015 +0000" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Mar 24 02:39:46 2015 +0000" }, "message": "Revert \"Deoptimization-based bce.\"\n\nThis breaks compiling the core image:\n\n Error after BCE: art::SSAChecker: Instruction 219 in block 1 does not dominate use 221 in block 1.\n\nThis reverts commit e295e6ec5beaea31be5d7d3c996cd8cfa2053129.\n\nChange-Id: Ieeb48797d451836ed506ccb940872f1443942e4e\n" }, { "commit": "e295e6ec5beaea31be5d7d3c996cd8cfa2053129", "tree": "4d8a657d23d511743ce35bee596544d7f652efdb", "parents": [ "d24ba2c44c76a2b2dd13aafe8f7981c15be31a98" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Sat Mar 07 06:37:59 2015 -0800" }, "committer": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Mon Mar 23 16:39:37 2015 -0700" }, "message": "Deoptimization-based bce.\n\nA mechanism is introduced that a runtime method can be called\nfrom code compiled with optimizing compiler to deoptimize into\ninterpreter. This can be used to establish invariants in the managed code\nIf the invariant does not hold at runtime, we will deoptimize and continue\nexecution in the interpreter. This allows to optimize the managed code as\nif the invariant was proven during compile time. However, the exception\nwill be thrown according to the semantics demanded by the spec.\n\nThe invariant and optimization included in this patch are based on the\nlength of an array. Given a set of array accesses with constant indices\n{c1, ..., cn}, we can optimize away all bounds checks iff all 0 \u003c\u003d min(ci) and\nmax(ci) \u003c array-length. The first can be proven statically. The second can be\nestablished with a deoptimization-based invariant. This replaces n bounds\nchecks with one invariant check (plus slow-path code).\n\nChange-Id: I8c6e34b56c85d25b91074832d13dba1db0a81569\n" }, { "commit": "202d164d97c1e0322188706c222911f8370dd194", "tree": "b1f0e65127e4a9ca87f4843490a1993dd250e148", "parents": [ "cadf090da2dc91a3d6b842324e85f12ea6fef2ef", "f3b4aebd0f5ce6c82bfd6284919a5c5e91955124" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Mar 17 21:18:07 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Mar 17 21:18:08 2015 +0000" }, "message": "Merge \"Revert \"Inline long shift code\"\"" }, { "commit": "f3b4aebd0f5ce6c82bfd6284919a5c5e91955124", "tree": "ea27dd630728cfa994ce2c5da522538744a7a8a9", "parents": [ "09895ebf2d98783e65930a820e9288703bb1a50b" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Mar 17 21:16:38 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Mar 17 21:16:38 2015 +0000" }, "message": "Revert \"Inline long shift code\"\n\nThis reverts commit 09895ebf2d98783e65930a820e9288703bb1a50b.\n\nChange-Id: I7544022d896ef4353bc2cdf4b036403ed20c956d\n" }, { "commit": "cadf090da2dc91a3d6b842324e85f12ea6fef2ef", "tree": "60cd1c1c8982b6c10074e6c7385e55d9ab042657", "parents": [ "1d2868c081f6d523d4fe2d88fe321074e53f68e5", "09895ebf2d98783e65930a820e9288703bb1a50b" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Mar 17 18:50:54 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Mar 17 18:50:55 2015 +0000" }, "message": "Merge \"Inline long shift code\"" }, { "commit": "09895ebf2d98783e65930a820e9288703bb1a50b", "tree": "5fa8d5baf27ac8f18b80291a47ca62d19fa2dd7d", "parents": [ "e8e42f3548fd894f860912bb1b71ce6fa2d7daf3" ], "author": { "name": "Guillaume \"Vermeille\" Sanchez", "email": "guillaumesa@google.com", "time": "Wed Mar 11 14:57:40 2015 +0000" }, "committer": { "name": "Guillaume Sanchez", "email": "guillaumesa@google.com", "time": "Tue Mar 17 18:49:53 2015 +0000" }, "message": "Inline long shift code\n\nChange-Id: I96887c295eb9a23dad4c9cc05d0a0e3ba17f674d\n" }, { "commit": "68e15009173f92fe717546a621b56413d5e9fba1", "tree": "460f18693f53bcbcc6f79b03f8a211f271c973a7", "parents": [ "1311ef7226f6147f2ef8c491321972a79d73914a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Mar 17 16:16:49 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Mar 17 16:23:17 2015 +0000" }, "message": "PREOPT compiles using dex2oatd so don\u0027t emit debug instructions.\n\nChange-Id: I8d2ab8d956ad0ce313928918c658d49f490ad081\n" }, { "commit": "eeefa1276e83776f08704a3db4237423b0627e20", "tree": "d7c647ca77703f3712f567704f40b00d59a125de", "parents": [ "02c0bac34c246c1bd974dbb86d292d4b52ba98e4" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 18:52:59 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Mar 16 10:48:21 2015 +0000" }, "message": "Update locations of registers after slow paths spilling.\n\nChange-Id: Id9aafcc13c1a085c17ce65d704c67b73f9de695d\n" }, { "commit": "a8ac9130b872c080299afacf5dcaab513d13ea87", "tree": "2bd0a2a88cbb6e7a3ae79dff84c466bed9189eb5", "parents": [ "cc22e3946baf035c8732e9417ab132bfe663aa45" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 16:36:36 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 16:47:44 2015 +0000" }, "message": "Refactor code in preparation of correct stack maps in slow path.\n\nMove the logic of saving/restoring live registers in slow path\nin the SlowPathCode method. Also add a RecordPcInfo helper to\nSlowPathCode, that will act as the placeholder of saving correct\nstack maps.\n\nChange-Id: I25c2bc7a642ef854bbc8a3eb570e5c8c8d2d030c\n" }, { "commit": "dc5ac731f6369b53b42f1cee3404f3b3384cec34", "tree": "72a90f1da01185014551628078b98a79e5d5230e", "parents": [ "0e5e728a4a4f042f157e1897cc8bbc2b0bb110b1" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Wed Feb 25 11:28:05 2015 -0800" }, "committer": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Tue Mar 03 13:24:03 2015 -0800" }, "message": "Opt compiler: enhance gvn for commutative ops.\n\nChange-Id: I415b50d58b30cab4ec38077be22373eb9598ec40\n" }, { "commit": "d8ef2e991a1a65f47a26a1eb8c6b34c92b775d6b", "tree": "d3aa88b42db86584724a2566da304aff70be5613", "parents": [ "a48c573d2351177d878e36e003f0cdf4d7f9328f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Feb 24 16:02:06 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Feb 24 16:04:07 2015 +0000" }, "message": "not-int can also take non-int (byte and short) instructions.\n\nSo we should use the result-type instead if the input type\nfor knowning what instruction to use.\n\nBug: 19454010\nChange-Id: I88782ad27ae8c8e1b7868afede5057d26f14685a\n" }, { "commit": "b1498f67b444c897fa8f1530777ef118e05aa631", "tree": "7ff4709329b0ba752a6111103a76fcea896a3adb", "parents": [ "acf735c13998ad2a175f5a17e7bfce220073279d" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Feb 16 13:13:29 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Feb 20 14:26:08 2015 +0000" }, "message": "Improve type propagation with if-contexts\n\nThis works by adding a new instruction (HBoundType) after each `if (a\ninstanceof ClassA) {}` to bound the type that `a` can take in the True-\ndominated blocks.\n\nChange-Id: Iae6a150b353486d4509b0d9b092164675732b90c\n" }, { "commit": "d6138ef1ea13d07ae555542f8898b30d89e9ac9a", "tree": "a8ffd5fd966512fd280bc1b3214f4e57a9e1805f", "parents": [ "92095533ac28879ddd8b44b559d700527ca12b8a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Feb 18 14:48:53 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Feb 19 14:01:18 2015 +0000" }, "message": "Ensure the graph is correctly typed.\n\nWe used to be forgiving because of HIntConstant(0) also being\nused for null. We now create a special HNullConstant for such uses.\n\nAlso, we need to run the dead phi elimination twice during ssa\nbuilding to ensure the correctness.\n\nChange-Id: If479efa3680d3358800aebb1cca692fa2d94f6e5\n" }, { "commit": "ffe8a577a4c644a2c5387f1e8efe92fb0efac43f", "tree": "f750bf49bd7c618ddf124cbfac0cc9e91be34cf9", "parents": [ "aa874e0bbfb21aec0661b93cb1c2ce065bc20302" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Feb 11 01:10:39 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Feb 13 15:36:28 2015 +0000" }, "message": "Optimize double/float immediate loading on arm.\n\nAlso reserve a D register for temp.\n\nChange-Id: I6584d9005b0f5685c3afcd8e9153b4c87b56aa8e\n" }, { "commit": "1d6957f0b9d560c75a1901a83a45b4f3510a1015", "tree": "36a174d4b12ef46744c5f3e80f8afeb46809a2e6", "parents": [ "0525d6aa15cb9db70e26c01f7e7a695bae377268", "f7a0c4e421b5edaad5b7a15bfff687da28d0b287" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Feb 10 19:33:22 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Feb 10 19:33:23 2015 +0000" }, "message": "Merge \"Improve ParallelMoveResolver to work with pairs.\"" }, { "commit": "f7a0c4e421b5edaad5b7a15bfff687da28d0b287", "tree": "5423a2357661b80d75cb2e3a2b5395a3fe3cd9b5", "parents": [ "0f2433bfcb02a662fe739e8e2b068abc2958e4c1" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Feb 10 17:08:47 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Feb 10 19:12:59 2015 +0000" }, "message": "Improve ParallelMoveResolver to work with pairs.\n\nChange-Id: Ie2a540ffdb78f7f15d69c16a08ca2d3e794f65b9\n" }, { "commit": "391b87ee8d939b60385fde9c48fda8a334ab9ae3", "tree": "c3880480f452cc85cad1b3cc4443ca83f67a248a", "parents": [ "0aac867161c4207aace8ae0d0b2abe02bfb8c3d9", "2bcf9bf784a0021630d8fe63d7230d46d6891780" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Feb 09 21:09:41 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Feb 09 21:09:42 2015 +0000" }, "message": "Merge \"ART: Arm intrinsics for Optimizing compiler\"" }, { "commit": "2bcf9bf784a0021630d8fe63d7230d46d6891780", "tree": "167d773b796c5e63d84c205a8ae9a2fe3585d06a", "parents": [ "61fdf5bca503c30ba1e4dcaf333a8d3299f3bde6" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jan 29 09:56:07 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Feb 09 13:08:39 2015 -0800" }, "message": "ART: Arm intrinsics for Optimizing compiler\n\nAdd arm32 intrinsics to the optimizing compiler.\n\nChange-Id: If4aeedbf560862074d8ee08ca4484b666d6b9bf0\n" }, { "commit": "c0572a451944f78397619dec34a38c36c11e9d2a", "tree": "2cc6f3c6f5ad45b4b85fb62627e797fe7e7734e1", "parents": [ "0f2433bfcb02a662fe739e8e2b068abc2958e4c1" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Feb 06 14:35:25 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Feb 06 17:37:57 2015 +0000" }, "message": "Optimize leaf methods.\n\nAvoid suspend checks and stack changes when not needed.\n\nChange-Id: I0fdb31e8c631e99091b818874a558c9aa04b1628\n" }, { "commit": "829280cc90b7a84db42864589b4bafb4c94a79d9", "tree": "8c6f0235011e046bc711ebf795678f6d1a2fedda", "parents": [ "69d69ea40fe64ff2e70daffc365a2fffe5964fcc" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 28 10:20:37 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Feb 04 09:11:40 2015 +0000" }, "message": "Finally implement Location::kNoOutputOverlap.\n\nThe [i, i + 1) interval scheme we chose for representing\nlifetime positions is not optimal for doing this optimization.\nIt however doesn\u0027t prevent recognizing a non-split interval\nduring the TryAllocateFreeReg phase, and try to re-use\nits inputs\u0027 registers.\n\nChange-Id: I80a2823b0048d3310becfc5f5fb7b1230dfd8201\n" }, { "commit": "cb1b00aedd94785e7599f18065a0b97b314e64f6", "tree": "fdde101b239c66325243bcc60d3d94f07ff56492", "parents": [ "9544368685b4aa65e746332e602491a3e8e5b247" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 28 14:50:01 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 30 17:43:16 2015 +0000" }, "message": "Use the non access check entrypoint when possible.\n\nChange-Id: I0b53d63141395e26816d5d2ce3fa6a297bb39b54\n" }, { "commit": "1cf95287364948689f6a1a320567acd7728e94a3", "tree": "70a8b60c768894d635cf63b0a480baa5073d2bed", "parents": [ "4a50662eeaa0b1a26be66e7584fb765151dabc59" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Dec 12 19:22:03 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 29 10:52:14 2015 +0000" }, "message": "Small optimization for recursive calls: avoid dex cache.\n\nChange-Id: I044757a2f06e535cdc1480c4fc8182b89635baf6\n" }, { "commit": "a0bb2bd5b6a049ad806c223f00672d1f0210db67", "tree": "206723aac52d4ccdf692f1d6a3c82c059f1cf6a1", "parents": [ "2dadc9df0ffb822870a150f81257792b83241c77" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jan 26 12:49:35 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jan 26 12:52:16 2015 +0000" }, "message": "Fix codegen_test.\n\nNative and ART do not have the same calling convention for ART,\nso we need to adjust blocked and allocated registers.\n\nChange-Id: I606b2620c0e5a54bd60d6100a137c06616ad40b4\n" }, { "commit": "4dee636d21d9ce54386cdfbb824e5eb2a9c1af0d", "tree": "ee8650cc14ec18ce0d7abf089c7d2e0dfc9e079d", "parents": [ "336247fa6deba2948f5ede1df806f48cf67c790a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 23 18:23:14 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sat Jan 24 14:34:01 2015 +0000" }, "message": "Support callee-save registers on ARM.\n\nChange-Id: I7c519b7a828c9891b1141a8e51e12d6a8bc84118\n" }, { "commit": "d97dc40d186aec46bfd318b6a2026a98241d7e9c", "tree": "5cf0257eda25e2722a1adafb9de22690c06a56d8", "parents": [ "c698b78a17043d8898deb817098181595fbe734e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 22 13:50:01 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 23 09:20:42 2015 +0000" }, "message": "Support callee save floating point registers on x64.\n\n- Share the computation of core_spill_mask and fpu_spill_mask\n between backends.\n- Remove explicit stack overflow check support: we need to adjust\n them and since they are not tested, they will easily bitrot.\n\nChange-Id: I0b619b8de4e1bdb169ea1ae7c6ede8df0d65837a\n" }, { "commit": "988939683c26c0b1c8808fc206add6337319509a", "tree": "876e94428276547a29c27ccf17509a42dfe7cda1", "parents": [ "59add47cabce3735ccd470cd3b5dac8b112e09ab" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 12:32:32 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 18:50:25 2015 +0000" }, "message": "Enable core callee-save on x64.\n\nWill work on other architectures and FP support in other CLs.\n\nChange-Id: I8cef0343eedc7202d206f5217fdf0349035f0e4d\n" }, { "commit": "b6b114c02b8bacd3b5d64e646fdaefa03c069c61", "tree": "cd702f32a9241c94d9e0d12828f3bcb0291b087b", "parents": [ "73d8fe409fbf2cb9665779690660ccc852d60431", "fa93b504b324784dd9a96e28e6e8f3f1b1ac456a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 17:33:43 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jan 21 17:33:43 2015 +0000" }, "message": "Merge \"Do not use HNot for creating !bool.\"" }, { "commit": "fa93b504b324784dd9a96e28e6e8f3f1b1ac456a", "tree": "8a3e691268657db75a69c8d644e5a963abee66d6", "parents": [ "1147eeed2ffc82ac9b1405f9fb0a6cbc8560c42b" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 15:44:16 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 17:03:29 2015 +0000" }, "message": "Do not use HNot for creating !bool.\n\nHNot folds to ~, not !.\n\nChange-Id: I681f968449a2ade7110b2f316146ad16ba5da74c\n" }, { "commit": "6c2dff8ff8e1440fa4d9e1b2ba2a44d036882801", "tree": "da2d48b3d84733ac6b29194cb2f624693a643d48", "parents": [ "22c9285142169691eb2a9e2d4a49751fc7e57c2a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 14:56:54 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 15:19:06 2015 +0000" }, "message": "Revert \"Revert \"Fully support pairs in the register allocator.\"\"\n\nThis reverts commit c399fdc442db82dfda66e6c25518872ab0f1d24f.\n\nChange-Id: I19f8215c4b98f2f0827e04bf7806c3ca439794e5\n" }, { "commit": "77520bca97ec44e3758510cebd0f20e3bb4584ea", "tree": "2e3be6fdc182e5cf5ae390019457af5e9c1ed242", "parents": [ "4d2c611bf17ff309abfa152e56c0b98a21ec8787" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Jan 12 18:45:46 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Jan 21 14:26:35 2015 +0000" }, "message": "Record implicit null checks at the actual invoke time.\n\nImplicitNullChecks are recorded only for instructions directly (see NB\nbelow) preceeded by NullChecks in the graph. This way we avoid recording\nredundant safepoints and minimize the code size increase.\n\nNB: ParallalelMoves might be inserted by the register allocator between\nthe NullChecks and their uses. These modify the environment and the\ncorrect action would be to reverse their modification. This will be\naddressed in a follow-up CL.\n\nChange-Id: Ie50006e5a4bd22932dcf11348f5a655d253cd898\n" }, { "commit": "c399fdc442db82dfda66e6c25518872ab0f1d24f", "tree": "6f0841ad5e8e80b09e34e084ae8eac336bce73a2", "parents": [ "41aedbb684ccef76ff8373f39aba606ce4cb3194" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 12:42:57 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 12:42:57 2015 +0000" }, "message": "Revert \"Fully support pairs in the register allocator.\"\n\nLibcore tests fail.\n\nThis reverts commit 41aedbb684ccef76ff8373f39aba606ce4cb3194.\n\nChange-Id: I2572f120d4bbaeb7a4d4cbfd47ab00c9ea39ac6c\n" }, { "commit": "41aedbb684ccef76ff8373f39aba606ce4cb3194", "tree": "94929237a0fe9b24dda7409d9433f07e82af4461", "parents": [ "97c89e4c081dcf4bacbde70b6609e366c9da417e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 14 10:49:16 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 11:27:57 2015 +0000" }, "message": "Fully support pairs in the register allocator.\n\nEnabled on ARM for longs and doubles.\n\nChange-Id: Id8792d08bd7ca9fb049c5db8a40ae694bafc2d8b\n" }, { "commit": "93edf73a5fecd526920fbd870068fa592376ac8a", "tree": "c24e0223e6ff0d1ec2eefeb1d863c1c32ca5f65c", "parents": [ "97d9f286971a4c1eec70e08f9f18f990d21780d5" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Jan 20 20:14:07 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Jan 20 20:14:07 2015 +0000" }, "message": "Use CompilerOptions for implicit stack overflow checks\n\nChange-Id: I52744382a7e3d2c6c11a43e027d87bf43ec4e62b\n" }, { "commit": "e7fd3e3a8e7f10048b7ea558cc525331c97bbefa", "tree": "a5d1a942460fe34c82f3dce7846d004b90ebd08d", "parents": [ "606a81aab3b9289d37d828375793020b93718c6a", "cd6dffedf1bd8e6dfb3fb0c933551f9a90f7de3f" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Jan 20 12:28:09 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jan 20 12:28:11 2015 +0000" }, "message": "Merge \"Add implicit null checks for the optimizing compiler\"" }, { "commit": "3747b48f7b09a9bc836397ceaacb9de0940db6fd", "tree": "8d8d5a096504344ab2d336641ed272517dcbc42c", "parents": [ "e210661a68e933cc6982368c24cca165eb61962f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jan 19 17:17:16 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jan 19 17:17:16 2015 +0000" }, "message": "Address review comments.\n\nComments were from:\nhttps://android-review.googlesource.com/#/c/121992.\n\nChange-Id: I8c59b30a356d606f12c50d0c8db916295a5c9e13\n" }, { "commit": "a8eef82f394f31272610d7ed80328ee465fa1a0f", "tree": "363103fcf07b2b4e6c944b02984d3f345b2949f1", "parents": [ "c2c7a33a25169cdf19a0dcf45ddb3747055c7296" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 16 11:14:27 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jan 19 09:10:12 2015 +0000" }, "message": "Do not use STMP, it conflicts with the calling convention.\n\nHard-float calling convention uses S14 and D7 for argument passing,\nso we cannot use them.\n\nChange-Id: I77a2d8c875677640204baebc24355051aa4175fd\n" }, { "commit": "cd6dffedf1bd8e6dfb3fb0c933551f9a90f7de3f", "tree": "0d83e9fdf65bded684d6e836078f253e63b7e11f", "parents": [ "12c03ac7575db242a6f35739bb459e8277115da4" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Jan 08 17:35:35 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Jan 16 17:27:03 2015 +0000" }, "message": "Add implicit null checks for the optimizing compiler\n\n- for backends: arm, arm64, x86, x86_64\n- fixed parameter passing for CodeGenerator\n- 003-omnibus-opcodes test verifies that NullPointerExceptions work as\nexpected\n\nChange-Id: I1b302acd353342504716c9169a80706cf3aba2c8\n" }, { "commit": "42d1f5f006c8bdbcbf855c53036cd50f9c69753e", "tree": "fb885c3df20797b55f19e5ceccf72dac1c13017b", "parents": [ "36740379b9b1c81b7eb06ea9c9df411d0a9a765e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 16 09:14:18 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 16 11:22:08 2015 +0000" }, "message": "Do not use register pair in a parallel move.\n\nThe ParallelMoveResolver does not work with pairs. Instead,\ndecompose the pair into two individual moves.\n\nChange-Id: Ie9d3f0b078cef8dc20640c98b20bb20cc4971a7f\n" }, { "commit": "71fb52fee246b7d511f520febbd73dc7a9bbca79", "tree": "444d91e910433aaf887bbdada28dfaa3160bebc2", "parents": [ "420457e6040184a6e1639a4c84fcc8e237bd8a3d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Dec 29 17:43:08 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jan 15 10:21:11 2015 -0800" }, "message": "ART: Optimizing compiler intrinsics\n\nAdd intrinsics infrastructure to the optimizing compiler.\n\nAdd almost all intrinsics supported by Quick to the x86-64 backend.\nFurther intrinsics require more assembler support.\n\nChange-Id: I48de9b44c82886bb298d16e74e12a9506b8e8807\n" }, { "commit": "c208b8776eac5ab2d656eda1c5ede90d2cc795a2", "tree": "a2359060c57423bb35da15408af2fa7e628714bf", "parents": [ "c40a4350daac81ddbfc5f6ceab934f2180dc4ec6", "53f1262773516a247e7bfad50de3cd94a4dcf4df" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 14 10:31:28 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jan 14 10:31:29 2015 +0000" }, "message": "Merge \"Implement ParallelMoveResolver::Swap for doubles on arm.\"" }, { "commit": "53f1262773516a247e7bfad50de3cd94a4dcf4df", "tree": "acf2c3095a0af9457a42a82c0fbdf43bcc2cd3e7", "parents": [ "8fccea249b1a6f1469eeea42c2b2cca06ce1c70d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jan 13 18:04:41 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 14 10:30:21 2015 +0000" }, "message": "Implement ParallelMoveResolver::Swap for doubles on arm.\n\nCurrently reserve a global register DTMP for these operations.\n\nChange-Id: Ie88b4696af51834492fd062082335bc2e1137be2\n" }, { "commit": "af2c65c38449dfeb21b572887110c5c9a0008ca1", "tree": "fe90654338f6768cfc6475c3ee2d87c01ec1f703", "parents": [ "7774edf4c19734922669fa888923e8c7d7385ea3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 14 09:40:32 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 14 09:40:32 2015 +0000" }, "message": "Remove whitespace.\n\nChange-Id: I82f51cff87765a3aeeb861d2ae64978f2e762c73\n" }, { "commit": "69c15d340e7e76821bbc5d4494d4cef383774dee", "tree": "afea69c321ffa55e0af63a83be62eedd2b378d2f", "parents": [ "603104b5b5c3759b0bc2733bda2f972686a775a3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jan 13 11:42:13 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jan 13 18:11:24 2015 +0000" }, "message": "Skip r1 on arm if first parameter is a long.\n\nChange-Id: I16d927ee0a0b55031ade4c92c0095fd74e18ed5b\n" }, { "commit": "425f239c291d435f519a1cf4bdd9ccc9a2c0c070", "tree": "6c4ec2cef8fd0caf45712191bcbc5d72ed0d318b", "parents": [ "11adb76fbc2dc3d8cbb6665945ff5d6733e2a8e6" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 08 14:52:29 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jan 12 14:08:55 2015 +0000" }, "message": "Fix handling of long argument spanning register/memory.\n\nComment in arm_lir.h says:\n * If a 64-bit argument would span the register/memory argument\n * boundary, it will instead be fully passed in the frame.\n\nThis change implements such logic for all platforms. We still need\nto pass the low part in register as well because I haven\u0027t ported\nthe jni compilers (x86 and mips) to it.\n\nOnce the jni compilers are updated, we can remove the register\nassignment.\n\nNote that this greatly simplifies optimizing\u0027s register allocator\nby not having to understand a long spanning register and memory.\n\nChange-Id: I59706ca5d47269fc46e5489ac99bd6576e87e7f3\n" }, { "commit": "bdcedd301a0a417ca538b7bf7e684c60cb1dbda3", "tree": "fe557008730c8eb19d27ccf7895899e098f4dd8e", "parents": [ "c9025c185462c9b8d61725a7399ccf2d8a433a6d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 09 08:48:29 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 09 08:48:29 2015 +0000" }, "message": "Don\u0027t overwrite a register input.\n\n`addr` is a register input, which can survive the current instruction,\ntherefore we can\u0027t overwrite it.\n\nChange-Id: I6eaa60e5f91c2b7b9b31673457d2a0d63474e587\n" }, { "commit": "840e5461a85f8908f51e7f6cd562a9129ff0e7ce", "tree": "ea8b4cbc5a0e3dea96fefcd9247e6c06b17ac518", "parents": [ "893e8881e31180721512c1b9e5ffacb03aad2e45" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 07 16:01:24 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 08 13:57:51 2015 +0000" }, "message": "Implement double and float support for arm in register allocator.\n\nThe basic approach is:\n- An instruction that needs two registers gets two intervals.\n- When allocating the low part, we also allocate the high part.\n- When splitting a low (or high) interval, we also split the high\n (or low) equivalent.\n- Allocation follows the (S/D register) requirement that low\n registers are always even and the high equivalent is low + 1.\n\nChange-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797\n" }, { "commit": "0eb8e5db064188f09ebec78ea8ac8b4a7596c12c", "tree": "76f9812b6ea74ed8ac072cdd27629682611f3f7a", "parents": [ "1e862370ff2c3207afd1b2fc6f77f7ca345643b2", "3416601a9e9be81bb7494864287fd3602d18ef13" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Jan 06 12:10:48 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jan 06 12:10:49 2015 +0000" }, "message": "Merge \"Look at instruction set features when generating volatiles code\"" }, { "commit": "3416601a9e9be81bb7494864287fd3602d18ef13", "tree": "dd228519bfb9733aa7627b9cea81ecb28974a1ab", "parents": [ "8558375377946aabbbda6ab584e13f754590bd89" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Dec 19 17:22:29 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Jan 05 16:25:59 2015 +0000" }, "message": "Look at instruction set features when generating volatiles code\n\nChange-Id: Ia882405719fdd60b63e4102af7e085f7cbe0bb2a\n" }, { "commit": "1cc7dbabd03e0a6c09d68161417a21bd6f9df371", "tree": "8557bdff971e366909351af95a7c8ead82792986", "parents": [ "5e0a9849d4e353c3726095b65ab07cefce40a636" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Dec 17 18:43:01 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Dec 29 10:52:02 2014 -0800" }, "message": "ART: Reorder entrypoint argument order\n\nShuffle the ArtMethod* referrer backwards for easier removal.\n\nClean up ARM \u0026 MIPS assembly code.\n\nChange some macros to make future changes easier.\n\nChange-Id: Ie2862b68bd6e519438e83eecd9e1611df51d7945\n" }, { "commit": "52c489645b6e9ae33623f1ec24143cde5444906e", "tree": "a39667aa354645bd42a7a061d08ca82df3004143", "parents": [ "193c7a94822f765b0b6b0cecd54c9f08dfd26425" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Dec 16 17:02:57 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Dec 19 09:58:27 2014 +0000" }, "message": "[optimizing compiler] Add support for volatile\n\n- for backends: arm, x86, x86_64\n- added necessary instructions to assemblies\n- clean up code gen for field set/get\n- fixed InstructionDataEquals for some instructions\n- fixed comments in compiler_enums\n\n* 003-opcode test verifies basic volatile functionality\n\nChange-Id: I144393efa312dfb2c332cb84056b00edffee338a\n" }, { "commit": "6048838af46f41c08c4132ba242040dc49bd5f23", "tree": "5124300bf9a7106d534e126b1926cc9d787ae2dc", "parents": [ "ca747ea9951188dbc6f5217d49aca34aeadcc2a6", "5b4b898ed8725242ee6b7229b94467c3ea3054c8" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 17:46:12 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Dec 18 17:46:13 2014 +0000" }, "message": "Merge \"Revert \"Don\u0027t block quick callee saved registers for optimizing.\"\"" }, { "commit": "5b4b898ed8725242ee6b7229b94467c3ea3054c8", "tree": "46f6df76e49f9a42dae89a6b9cf8336eae1da519", "parents": [ "6004796d6c630696127df2494dcd4f30d1367a34" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 17:45:56 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 17:45:56 2014 +0000" }, "message": "Revert \"Don\u0027t block quick callee saved registers for optimizing.\"\n\nX64 has one libcore test failing, and codegen_test on\narm is failing.\n\nThis reverts commit 6004796d6c630696127df2494dcd4f30d1367a34.\n\nChange-Id: I20e00431fa18e11ce4c0cb6fffa91977fa8e9b4f\n" }, { "commit": "e408f8c6ac0ee80543ee1a695695e8917e45eaf3", "tree": "8637636ea603b134b410cf535281fb56249f9d55", "parents": [ "452a8bec86e7795c99f774e81c02f12f1b1e502f", "6004796d6c630696127df2494dcd4f30d1367a34" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 15:49:52 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Dec 18 15:49:53 2014 +0000" }, "message": "Merge \"Don\u0027t block quick callee saved registers for optimizing.\"" }, { "commit": "6004796d6c630696127df2494dcd4f30d1367a34", "tree": "850f3e82a47061200c4e34e2c7e7a934f4769a97", "parents": [ "407d77f344cfbdbbfb50531c5f0766bc0892e2fe" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 15 00:01:18 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 14:59:50 2014 +0000" }, "message": "Don\u0027t block quick callee saved registers for optimizing.\n\nThis change builds on:\nhttps://android-review.googlesource.com/#/c/118983/\n\n- Also fix x86_64 assembler bug triggered by this change.\n- Fix (and improve) x86\u0027s backend byte register usage.\n- Fix a bug in baseline register allocator: a fixed\n out register must prevent inputs from allocating it.\n\nChange-Id: I4883862e29b4e4b6470f1823cf7eab7e7863d8ad\n" }, { "commit": "4e44c829e282b3979a73bfcba92510e64fbec209", "tree": "42375a128b28bb886955214336f63391dfc41d5c", "parents": [ "390f59f9bec64fd81b05e796dfaeb03ab6d4cc81" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Dec 17 12:25:12 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Dec 17 12:25:12 2014 +0000" }, "message": "Revert \"Small optimization for recursive calls: avoid dex cache.\"\n\nFails on target.\n\nThis reverts commit 390f59f9bec64fd81b05e796dfaeb03ab6d4cc81.\n\nChange-Id: Ic3865b8897068ba20df0fbc2bcf561faf6c290c1\n" }, { "commit": "390f59f9bec64fd81b05e796dfaeb03ab6d4cc81", "tree": "d418b4a488390d718144bf5a5a180d965d1d762e", "parents": [ "240016da1d6615b26c8342bdeb4bae381570ac47" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Dec 12 19:22:03 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Dec 17 11:53:33 2014 +0000" }, "message": "Small optimization for recursive calls: avoid dex cache.\n\nChange-Id: Ic4054b6c38f0a2a530ba6ef747647f86cee0b1b8\n" }, { "commit": "e53798a7e3267305f696bf658e418c92e63e0834", "tree": "8979bbed96b107a5a6bbae9285ff4e0c362dad95", "parents": [ "e6c0cdd11097dd72275ac24f1e98217c299d973e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 01 10:31:54 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 15 22:52:27 2014 +0000" }, "message": "Inlining support in optimizing.\n\nCurrently only inlines simple things that don\u0027t require an\nenvironment, such as:\n- Returning a constant.\n- Returning a parameter.\n- Returning an arithmetic operation.\n\nChange-Id: Ie844950cb44f69e104774a3cf7a8dea66bc85661\n" }, { "commit": "d2ec87d84057174d4884ee16f652cbcfd31362e9", "tree": "9456c5851f157566380c37895407dfce4749bb4d", "parents": [ "f551efff34c20e2f0cf962c3fc267204d5e7611f" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Dec 08 14:24:46 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Dec 08 17:02:11 2014 +0000" }, "message": "[optimizing compiler] Add REM_FLOAT and REM_DOUBLE\n\n- for arm, x86, x86_64 backends\n- reinstated fmod quick entry points for x86. This is a partial revert\nof bd3682eada753de52975ae2b4a712bd87dc139a6 which added inline assembly\nfor floting point rem on x86. Note that Quick still uses the inline\nversion.\n- fix rem tests for longs\n\nChange-Id: I73be19a9f2f2bcf3f718d9ca636e67bdd72b5440\n" }, { "commit": "4c0b61f506644bb6b647be05d02c5fb45b9ceb48", "tree": "26ff4e14af3cae5f9b30f65177be258d8259ecee", "parents": [ "7c8ce29e97fb7873160ab8895d847e9643a1f8f6" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Dec 05 12:06:01 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Dec 05 12:06:01 2014 +0000" }, "message": "Add support for double-to-int \u0026 double-to-long in optimizing.\n\n- Add support for the double-to-int and double-to-long Dex\n instructions in the optimizing compiler.\n- Add S1 to the list of ARM FPU parameter registers so that\n a double value can be passed as parameter during a call\n to the runtime through D0.\n- Have art::x86_64::X86_64Assembler::cvttsd2si work with\n 64-bit operands.\n- Generate x86, x86-64 and ARM (but not ARM64) code for\n double to int and double to long HTypeConversion nodes.\n- Add related tests to test/422-type-conversion.\n\nChange-Id: Ic93b9ec6630c26e940f7966a3346ad3fd5a2ab3a\n" }, { "commit": "8964e2b689d80fe546604ac8c724078645095cf1", "tree": "9909dfb2f891d12cc9ad6aabebfba9f535014609", "parents": [ "833e903b7a9063f37bea3c505cf134fc4a4e2084" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Dec 04 12:10:50 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Dec 04 12:10:50 2014 +0000" }, "message": "Add support for float-to-double \u0026 double-to-float in optimizing.\n\nChange-Id: I41b0fee5a28c83757697c8d000b7e224cf5a4534\n" }, { "commit": "624279f3c70f9904cbaf428078981b05d3b324c0", "tree": "a81f8d8facfc28cac479a68a1042edc74c36d25b", "parents": [ "9a64a46e8edfa89402598d8650b8ebb337ba3d52" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Dec 04 11:54:28 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Dec 04 11:54:28 2014 +0000" }, "message": "Add support for float-to-long in the optimizing compiler.\n\n- Add support for the float-to-long Dex instruction in the\n optimizing compiler.\n- Add a Dex PC field to art::HTypeConversion to allow the\n x86 and ARM code generators to produce runtime calls.\n- Instruct art::CodeGenerator::RecordPcInfo not to record\n PC information for HTypeConversion instructions.\n- Add S0 to the list of ARM FPU parameter registers.\n- Have art::x86_64::X86_64Assembler::cvttss2si work with\n 64-bit operands.\n- Generate x86, x86-64 and ARM (but not ARM64) code for\n float to long HTypeConversion nodes.\n- Add related tests to test/422-type-conversion.\n\nChange-Id: I954214f0d537187883f83f7a83a1bb2dd8a21fd4\n" }, { "commit": "3f8f936aff35f29d86183d31c20597ea17e9789d", "tree": "3abc4e5f99cf7de74dbc65cafb6c045074e25381", "parents": [ "fc600dccd7797a9a10cdd457034ea8e148ccd631" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Dec 02 17:45:01 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Dec 03 12:09:28 2014 +0000" }, "message": "Add support for float-to-int in the optimizing compiler.\n\n- Add support for the float-to-int Dex instruction in the\n optimizing compiler.\n- Factor type conversion related lines in\n compiler/optimizing/builder.cc.\n- Generate x86, x86-64 and ARM (but not ARM64) code for\n float to int HTypeConversion nodes.\n- Add related tests to test/422-type-conversion.\n\nChange-Id: I2382dfc04bf394ed75f675148cfcf98216d65bc6\n" }, { "commit": "01fcc9ee556f98d0163cc9b524e989760826926f", "tree": "db932611fcfb1390c761ae589a99dee5e956c271", "parents": [ "dff1069220465f93dc2e3636a0acd7522a5ba639" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 01 14:16:20 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 01 14:38:56 2014 +0000" }, "message": "Remove type conversion nodes converting to the same type.\n\nWhen optimizing, we ensure these conversions do not reach the\ncode generators. When not optimizing, we cannot get such situations.\n\nChange-Id: I717247c957667675dc261183019c88efa3a38452\n" }, { "commit": "3bcc8ea079d867f26622defd0611d134a3b4ae49", "tree": "a1f3f3ad3ec1284d199eee6e57889b8c1e90b619", "parents": [ "eea79dd779ba199658ada7264f8f96d776e53f19" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Nov 28 15:00:02 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Nov 28 16:03:28 2014 +0000" }, "message": "Don\u0027t use CanHoldArm in the code generator.\n\nCanHoldArm was ARM32 specific. Instead use a virtual\nAssembler::ShifterOperandCanHold that both thumb2 and arm32\nimplement.\n\nChange-Id: I33794a93caf02ee5d78d32a8471d9fd6fe4f0a00\n" }, { "commit": "6d0e483dd2e0b63e952de060738c10e2abd12ff7", "tree": "b396377926d2645f0df982f0b03c41149632a3de", "parents": [ "7c97e855ceb9b45a1cc738fb144bd3312c4e09a8" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 27 18:31:21 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 27 18:36:14 2014 +0000" }, "message": "Add support for long-to-float in the optimizing compiler.\n\n- Add support for the long-to-float Dex instruction in the\n optimizing compiler.\n- Have art::x86_64::X86_64Assembler::cvtsi2ss work with\n 64-bit operands.\n- Generate x86, x86-64 and ARM (but not ARM64) code for\n long to float HTypeConversion nodes.\n- Add related tests to test/422-type-conversion.\n\nChange-Id: Ic983cbeb1ae2051add40bc519a8f00a6196166c9\n" }, { "commit": "199f336af1fc8212646fda67675df0361ece33d6", "tree": "e8709a668b285246ab7d7f4c3f8f2553fd5f39e2", "parents": [ "924632d2626b17b903bf7b851099f6d575ac534b" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 27 17:15:16 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 27 17:15:16 2014 +0000" }, "message": "Wrap long lines in the optimizing compiler.\n\nChange-Id: I5dee0c65e6652de574ae952b1f1dfc7355859e45\n" }, { "commit": "924632d2626b17b903bf7b851099f6d575ac534b", "tree": "e9f06a7a23aa6a8882aeb8c27671e78178b71c12", "parents": [ "e936f68824c441d07bd3a4d5dce4b9b18794a41f", "271ab9c916980209fbc6b26e5545d76e58471569" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 27 15:42:08 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Nov 27 15:42:08 2014 +0000" }, "message": "Merge \"Ensure opt. compiler doesn\u0027t get core \u0026 FP registers mixed up.\"" }, { "commit": "32b2a52aa3d6dc25c18422514c7f88757f87d33c", "tree": "b819d171a509bde557fe1ffefc838d8573854f53", "parents": [ "d7fa3a7d26105dd112acf955a0c7a880a6027180" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Nov 27 14:54:18 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Nov 27 15:35:24 2014 +0000" }, "message": "Fix Move64 by using ParallelMoves.\n\nDestination and source might overlap in a Move64, so we have to\nuse a parallel move resolver.\n\nChange-Id: Ica6c72d91ab8e2e2ee4661b211ac1ee8f054b9ef\n" }, { "commit": "271ab9c916980209fbc6b26e5545d76e58471569", "tree": "fc07a28f5fd4b7a086ae90dd94778c16efd6dae3", "parents": [ "5368c219a462defc90c4b896b34eb7506ba5c142" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 27 15:23:57 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 27 15:23:57 2014 +0000" }, "message": "Ensure opt. compiler doesn\u0027t get core \u0026 FP registers mixed up.\n\nReplace Location::As\u003cT\u003e() with two method methods\n(Location::AsRegister\u003cT\u003e() and Location::AsFpuRegister\u003cT\u003e())\nchecking the kind of the location (register).\n\nChange-Id: I22b4abee1a124b684becd2dc1caf33652b911070\n" }, { "commit": "d7fa3a7d26105dd112acf955a0c7a880a6027180", "tree": "2230bd8ef1ab17e79b786c906f571222a76e9d67", "parents": [ "a9159b2e6b11ec92a1c20a6f3cfe0072f12bd389", "ddb7df25af45d7cd19ed1138e537973735cc78a5" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Nov 27 13:13:34 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Nov 27 13:13:35 2014 +0000" }, "message": "Merge \"[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}\"" }, { "commit": "ddb7df25af45d7cd19ed1138e537973735cc78a5", "tree": "c428e9482c7d9137c0965eed586969ae108b173f", "parents": [ "35ecc8ca8fba713728b8fc60e9e2a275da2028aa" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Nov 25 20:56:51 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Nov 27 12:30:27 2014 +0000" }, "message": "[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}\n\nAdds:\n- float comparison for arm, x86, x86_64 backends.\n- ucomis{s,d} assembly to x86 and x86_64.\n- vmstat assebmly for thumb2\n- new assembly tests\n\nChange-Id: Ie3e19d0c08b3b875cd0a4be4ee4e9c8a4a076290\n" }, { "commit": "647b9ed41cdb7cf302fd356627a3ba372419b78c", "tree": "f1ca054aa20ae4c489f208982e7a6cba5d5ee21e", "parents": [ "35ecc8ca8fba713728b8fc60e9e2a275da2028aa" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 27 12:06:00 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 27 12:06:00 2014 +0000" }, "message": "Add support for long-to-double in the optimizing compiler.\n\n- Add support for the long-to-double Dex instruction in the\n optimizing compiler.\n- Enable requests of temporary FPU (double) registers during\n code generation.\n- Fix art::x86::X86Assembler::LoadLongConstant and extend\n it to int64_t values.\n- Have art::x86_64::X86_64Assembler::cvtsi2sd work with\n 64-bit operands.\n- Generate x86, x86-64 and ARM (but not ARM64) code for\n long to double HTypeConversion nodes.\n- Add related tests to test/422-type-conversion.\n\nChange-Id: Ie73d9e5e25bd2e15f585c371e8fc2dcb83438ccd\n" }, { "commit": "91debbc3da3e3376416e4394155d9f9e355255cb", "tree": "fd2181a2d4b8e7e8d26101a9a87b4f0c34fa990f", "parents": [ "fd861249f31ab360c12dd1ffb131d50f02b0bfc6" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Nov 26 19:01:09 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Nov 26 19:01:09 2014 +0000" }, "message": "Revert \"[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}\"\n\nFails on arm due to missing vmrs op after vcmp. I revert this instead of pushing the fix because I don\u0027t understand yet why it compiles with run-test but not with dex2oat.\n\nThis reverts commit fd861249f31ab360c12dd1ffb131d50f02b0bfc6.\n\nChange-Id: Idc2d30f6a0f39ddd3596aa18a532ae90f8aaf62f\n" }, { "commit": "fd861249f31ab360c12dd1ffb131d50f02b0bfc6", "tree": "1765db2b26337f8e96616ebfb769c95d7b421ad2", "parents": [ "fef1680241e85532919ecfaf42855d31ddb69361" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Nov 25 20:56:51 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Nov 26 16:49:23 2014 +0000" }, "message": "[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}\n\n- adds float comparison for arm, x86, x86_64 backends.\n- adds ucomis{s,d} assembly to x86 and x86_64.\n\nChange-Id: I232d2b6e9ecf373beb5cc63698dd97a658ff9c83\n" }, { "commit": "fef1680241e85532919ecfaf42855d31ddb69361", "tree": "fd2181a2d4b8e7e8d26101a9a87b4f0c34fa990f", "parents": [ "141d92c6abcc5057a4e586bfae801011bc4fefba", "799f506b8d48bcceef5e6cf50f3f5eb6bcea05e1" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 26 14:46:09 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Nov 26 14:46:10 2014 +0000" }, "message": "Merge \"Revert \"[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}\"\"" }, { "commit": "799f506b8d48bcceef5e6cf50f3f5eb6bcea05e1", "tree": "078cd0518627673566727494b003fa671c027dc8", "parents": [ "cea28ec4b9e94ec942899acf1dbf20f8999b36b4" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 26 14:45:52 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 26 14:45:52 2014 +0000" }, "message": "Revert \"[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}\"\n\nFails on x86_64 and target.\n\nThis reverts commit cea28ec4b9e94ec942899acf1dbf20f8999b36b4.\n\nChange-Id: I30c1d188c7ecfe765f137a307022ede84f15482c\n" }, { "commit": "141d92c6abcc5057a4e586bfae801011bc4fefba", "tree": "e0ca3be39ba519c3cf0fa39be9617b2228474a98", "parents": [ "94572c51dfbc1d48785ee340e602f0f8092afecf", "cea28ec4b9e94ec942899acf1dbf20f8999b36b4" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Nov 26 12:04:39 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Nov 26 12:04:40 2014 +0000" }, "message": "Merge \"[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}\"" }, { "commit": "cea28ec4b9e94ec942899acf1dbf20f8999b36b4", "tree": "893c062f6792688671519989a78065ecc7e79de9", "parents": [ "f0c001465371279355eeb7633b67ffcc6f6738e5" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Nov 25 20:56:51 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Nov 26 10:59:15 2014 +0000" }, "message": "[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}\n\n- adds float comparison for arm, x86, x86_64 backends.\n- adds ucomis{s,d} assembly to x86 and x86_64.\n\nChange-Id: Ie91e04bfb402025073054f3803a3a569e4705caa\n" }, { "commit": "eace45873190a27302b3644c32ec82854b59d299", "tree": "73fbf327839263b6847bdc4359ac1dbea2b897e3", "parents": [ "8ac8d5556fae9c728bcebcc9036a1bbf40087c76" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Mon Nov 24 18:29:54 2014 -0800" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Tue Nov 25 16:02:04 2014 -0800" }, "message": "Move dexCacheStrings from ArtMethod to Class\n\nAdds one load for const strings which are not direct.\n\nSaves \u003e\u003d 60KB of memory avg per app.\nImage size: -350KB.\n\nBug: 17643507\nChange-Id: I2d1a3253d9de09682be9bc6b420a29513d592cc8\n\n(cherry picked from commit f521f423b66e952f746885dd9f6cf8ef2788955d)\n" }, { "commit": "9aec02fc5df5518c16f1e5a9b6cb198a192db973", "tree": "fe924b37f395af1bb50f55ee6c87c66b727f00af", "parents": [ "20032e512c003a8f42735c4e1eca19c1472bb95e" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Nov 18 23:06:35 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Nov 24 16:06:55 2014 +0000" }, "message": "[optimizing compiler] Add shifts\n\nAdded SHL, SHR, USHR for arm, x86, x86_64.\n\nChange-Id: I971f594e270179457e6958acf1401ff7630df07e\n" }, { "commit": "86a8d7afc7f00ff0f5ea7b8aaf4d50514250a4e6", "tree": "3db61320369973e463f67927a8983d7eb0d9f860", "parents": [ "255a5bde2f0014dc86a564555106a4291c0867b4" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 19 08:47:18 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 19 08:47:18 2014 +0000" }, "message": "Consistently use k{InstructionSet}WordSize.\n\nThese constants were defined prior to k{InstructionSet}PointerSize. So\nuse them consistently in optimizing as a first step. We can discuss\nwhether we should remove them in a second step.\n\nChange-Id: If129de1a3bb8b65f8d9c816a8ad466815fb202e6\n" }, { "commit": "2d7210188805292e463be4bcf7a133b654d7e0ea", "tree": "7705a3bf841ae44b2396728fa22ed0b5dcb44dbf", "parents": [ "e0491682d101c69bf88c3c24a965312129cbfa38" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Mon Nov 10 11:08:06 2014 -0800" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Tue Nov 18 12:27:37 2014 -0800" }, "message": "Change 64 bit ArtMethod fields to be pointer sized\n\nChanged the 64 bit entrypoint and gc map fields in ArtMethod to be\npointer sized. This saves a large amount of memory on 32 bit systems.\nReduces ArtMethod size by 16 bytes on 32 bit.\n\nTotal number of ArtMethod on low memory mako: 169957\nImage size: 49203 methods -\u003e 787248 image size reduction.\nZygote space size: 1070 methods -\u003e 17120 size reduction.\nApp methods: ~120k -\u003e 2 MB savings.\n\nSavings per app on low memory mako: 125K+ per app\n(less active apps -\u003e more image methods per app).\n\nSavings depend on how often the shared methods are on dirty pages vs\nshared.\n\nTODO in another CL, delete gc map field from ArtMethod since we\nshould be able to get it from the Oat method header.\n\nBug: 17643507\n\nChange-Id: Ie9508f05907a9f693882d4d32a564460bf273ee8\n\n(cherry picked from commit e832e64a7e82d7f72aedbd7d798fb929d458ee8f)\n" }, { "commit": "67555f7e9a05a9d436e034f67ae683bbf02d072d", "tree": "9a01b7c69032b08b3c55c18076f68c1e397d8a35", "parents": [ "bf75c5cf32a47eecadcc5e4a324237c1f1d09cde" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Tue Nov 18 10:55:16 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Nov 18 15:36:36 2014 +0000" }, "message": "Opt compiler: Add support for more IRs on arm64.\n\nChange-Id: I4b6425135d1af74912a206411288081d2516f8bf\n" }, { "commit": "cff137481eda0eb8dbdf9d2a303ae2bdac2c7322", "tree": "577692649599d8c5ffd9b235d18af22c2621f7fe", "parents": [ "7bfb3f8b1748b5bf7e217a1337176ad488dca66a" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Nov 17 14:32:17 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Nov 17 16:40:49 2014 +0000" }, "message": "Add support for int-to-float \u0026 int-to-double in optimizing.\n\n- Add support for the int-to-float and int-to-double Dex\n instructions in the optimizing compiler.\n- Generate x86, x86-64 and ARM (but not ARM64) code for\n byte to float, short to float, int to float, char to\n float, byte to double, short to double, int to double and\n char to double HTypeConversion nodes.\n- Add related tests to test/422-type-conversion.\n\nChange-Id: I963f9d0184a5d3721af2d8f593f133d5af7aa6a3\n" }, { "commit": "1c18d5d0141ffa76b0838fb99615186dcbefc50e", "tree": "3789d51fabf7fa297575d6ce485a03e16faa1903", "parents": [ "610b21cc7f62c61fcb7d88c1ffcc74bfa9ca5ef8", "bacfec30ee9f2f6fdfd190f11b105b609938efca" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Nov 17 11:55:59 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Nov 17 11:55:59 2014 +0000" }, "message": "Merge \"[optimizing compiler] Add REM_INT, REM_LONG\"" }, { "commit": "bacfec30ee9f2f6fdfd190f11b105b609938efca", "tree": "1fb08fa38b27627ab59a54895ef098b43bb70ce1", "parents": [ "ff5298ff1640b730ee62c90ca78fc96b7ee82ec4" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Nov 14 15:54:36 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Nov 17 11:19:35 2014 +0000" }, "message": "[optimizing compiler] Add REM_INT, REM_LONG\n\n- for arm, x86, x86_64\n- minor cleanup/fix in div tests\n\nChange-Id: I240874010206a5a9b3aaffbc81a885b94c248f93\n" }, { "commit": "610b21cc7f62c61fcb7d88c1ffcc74bfa9ca5ef8", "tree": "85314ec6521fd5e8be6b4f75f1dab3ecc16e5a02", "parents": [ "1ad824c1e2b91196fa5d6a4827322923c3046833", "01a8d7135c59b4a664d1e0c0e4d8db343d4118ef" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Nov 17 10:24:03 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Nov 17 10:24:03 2014 +0000" }, "message": "Merge \"Add support for int-to-short in the optimizing compiler.\"" }, { "commit": "c1d4ec95c9dc69a7373e2eca0e69965e54d9cf03", "tree": "7ded15095ee62d471fe1455ec915c1d68fb202f6", "parents": [ "44e6d985fddb3d921f054ff64c319c86005118e9", "af07bc121121d7bd7e8329c55dfe24782207b561" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Nov 17 09:42:23 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Nov 17 09:42:25 2014 +0000" }, "message": "Merge \"Minor object store optimizations.\"" }, { "commit": "01a8d7135c59b4a664d1e0c0e4d8db343d4118ef", "tree": "2a7470f7320f015e67da880e3cf51fd9d616c17d", "parents": [ "ff5298ff1640b730ee62c90ca78fc96b7ee82ec4" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Nov 14 16:27:39 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Nov 14 16:27:39 2014 +0000" }, "message": "Add support for int-to-short in the optimizing compiler.\n\n- Add support for the int-to-short Dex instruction in the\n optimizing compiler.\n- Generate x86, x86-64 and ARM (but not ARM64) code for\n byte to short, int to short and char to short\n HTypeConversion nodes.\n- Add related tests to test/422-type-conversion.\n\nChange-Id: If1829549708d9c3473efaa641f7f0bcfa6080ae9\n" }, { "commit": "af07bc121121d7bd7e8329c55dfe24782207b561", "tree": "51e93225aa77c3949a63104f8d48e4b6f6fb2b5b", "parents": [ "d0d805bad888857fe974142cbf3292b9747daae3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 12 18:08:09 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Nov 14 13:45:02 2014 +0000" }, "message": "Minor object store optimizations.\n\n- Avoid emitting write barrier when the value is null.\n- Do not do a typecheck on an arraystore when storing something that\n was loaded from the same array.\n\nChange-Id: I902492928692e4553b5af0fc99cce3c2186c442a\n" }, { "commit": "981e45424f52735b1c61ae0eac7e299ed313f8db", "tree": "b52598c87d7e1cd030e570da2a59ee26199ae481", "parents": [ "4594ad627a48e249ee1680e954558dea15f0d133" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Nov 14 11:47:14 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Nov 14 11:51:41 2014 +0000" }, "message": "Add support for int-to-char in the optimizing compiler.\n\n- Add support for the int-to-char Dex instruction in the\n optimizing compiler.\n- Implement the ARM and Thumb-2 UBFX instructions and add\n tests for them.\n- Generate x86, x86-64 and ARM (but not ARM64) code for\n byte to char, short to char, int to char (and char to\n char!) HTypeConversion nodes.\n- Add related tests to test/422-type-conversion.\n\nChange-Id: I5cd4c6d86f0f6a966c059715b98db35cc8f9de76\n" }, { "commit": "7bdabab1b6a37248bcc0e16893e43f91b4218d29", "tree": "5087b4d6062deba3e105d1fd49f17bc0ea73db4c", "parents": [ "346bcbde27e4620ed1e7bce91728f22069a371f0", "51d3fc40637fc73d4156ad617cd451b844cbb75e" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 13 18:44:19 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Nov 13 18:44:20 2014 +0000" }, "message": "Merge \"Add support for int-to-byte in the optimizing compiler.\"" }, { "commit": "51d3fc40637fc73d4156ad617cd451b844cbb75e", "tree": "21669a66124a23dfc78a8c3f1d8b89415bfb0271", "parents": [ "d94a0a1d2868baaab49f4d2835bca086d98cf763" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 13 14:11:42 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 13 17:30:06 2014 +0000" }, "message": "Add support for int-to-byte in the optimizing compiler.\n\n- Add support for the int-to-byte Dex instruction in the\n optimizing compiler.\n- Implement the ARM and Thumb-2 SBFX instructions.\n- Generate x86, x86-64 and ARM (but not ARM64) code for\n char to byte, short to byte and int to byte\n HTypeConversion nodes.\n- Add related tests to test/422-type-conversion.\n\nChange-Id: Ic8b8911b90d4b5281fad15bcee96bc3ee85dc577\n" } ], "next": "dc87c1dd1d7a7192b03e87ffd07eec80e8c2ae24" }