)]}'
{
  "log": [
    {
      "commit": "dbbac8f812a866b1b53f3007721f66038d208549",
      "tree": "05cecd927afccd33fc1c14b39ada47e86873f560",
      "parents": [
        "2406bf17998e15bd40677a907beb3e9c41facce4"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Sep 01 13:06:08 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Sep 21 10:20:55 2017 -0700"
      },
      "message": "Implement Sum-of-Abs-Differences idiom recognition.\n\nRationale:\nCurrently just on ARM64 (x86 lacks proper support),\nusing the SAD idiom yields great speedup on loops\nthat compute the sum-of-abs-difference operation.\nAlso includes some refinements around type conversions.\n\nSpeedup ExoPlayerAudio (golem run):\n1.3x on ARM64\n1.1x on x86\n\nTest: test-art-host test-art-target\n\nBug: 64091002\n\nChange-Id: Ia2b711d2bc23609a2ed50493dfe6719eedfe0130\n"
    },
    {
      "commit": "5e3afa950f05bca470ef6b92460940f37831c27f",
      "tree": "3656fb1d9153a87b55b56c71a93833da49c112d4",
      "parents": [
        "b407afe983f8b106a5007d07aa2523ffc6525018"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Sep 20 14:11:11 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Sep 20 14:11:11 2017 -0700"
      },
      "message": "Ensure extract is seen as having scalar result.\n\nRationale:\nExtracting from a vector yields a scalar, yet\nour parallel mover and one DCHECK did not account\nfor that fact (note that moving towards a vector\ntype system will prevent such errors).\n\nRegression test for this is part of the SAD CL.\n\nTest: test-art-host test-art-target\n\nBug: 64091002\nChange-Id: Id154edd1a069c54e7d8da069c368dea0a8f973f4\n"
    },
    {
      "commit": "0148de41a5c77c2f61252c219f1a02413c7c4a32",
      "tree": "91736a82a7e98721a44879b6597b5aea386e8e3b",
      "parents": [
        "c101222c854a0c476f5b6ae64e20adbd38126a3c"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Sep 05 09:25:01 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Sep 05 10:20:09 2017 -0700"
      },
      "message": "Basic SIMD reduction support.\n\nRationale:\nEnables vectorization of x +\u003d .... for very basic (simple, same-type)\nconstructs. Paves the way for more complex (narrower and/or mixed-type)\nconstructs, which will be handled by the next CL.\n\nThis is  a revert   of Icb5d6c805516db0a1d911c3ede9a246ccef89a22\nand thus a revert^2 of I2454778dd0ef1da915c178c7274e1cf33e271d0f\nand thus a revert^3 of I1c1c87b6323e01442e8fbd94869ddc9e760ea1fc\nand thus a revert^4 of I7880c135aee3ed0a39da9ae5b468cbf80e613766\n\nPS1-2 shows what needed to change\n\nTest: test-art-host test-art-target\n\nBug: 64091002\nChange-Id: I647889e0da0959ca405b70081b79c7d3c9bcb2e9\n"
    },
    {
      "commit": "982334cef17d47ef2477d88a97203a9587a4b86f",
      "tree": "7e65d03a4533f21286cf68e66696bd0a7a54ef54",
      "parents": [
        "cfa59b49cde265dc5329a7e6956445f9f7a75f15"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Sat Sep 02 12:54:16 2017 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Sat Sep 02 12:54:16 2017 +0000"
      },
      "message": "Revert \"Basic SIMD reduction support.\"\n\nFails 530-checker-lse on arm64.\n\nBug: 64091002, 65212948\n\nThis reverts commit cfa59b49cde265dc5329a7e6956445f9f7a75f15.\n\nChange-Id: Icb5d6c805516db0a1d911c3ede9a246ccef89a22\n"
    },
    {
      "commit": "cfa59b49cde265dc5329a7e6956445f9f7a75f15",
      "tree": "eed953f62e796f7e64252520a40d7e77d1f117af",
      "parents": [
        "82a63734d3067ea0c96f8ba15bc40caaf798c625"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Aug 31 09:08:13 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Sep 01 10:32:50 2017 -0700"
      },
      "message": "Basic SIMD reduction support.\n\nRationale:\nEnables vectorization of x +\u003d .... for very basic (simple, same-type)\nconstructs. Paves the way for more complex (narrower and/or mixed-type)\nconstructs, which will be handled by the next CL.\n\nThis is a revert^2 of I7880c135aee3ed0a39da9ae5b468cbf80e613766\nand thus a revert  of I1c1c87b6323e01442e8fbd94869ddc9e760ea1fc\n\nPS1-2 shows what needed to change, with regression tests\n\nTest: test-art-host test-art-target\n\nBug: 64091002, 65212948\nChange-Id: I2454778dd0ef1da915c178c7274e1cf33e271d0f\n"
    },
    {
      "commit": "a57b4ee7b15ce6abfb5fa88c8dc8a516fe40e0d9",
      "tree": "c7ed7e8cb7439a8e689e399e34559aa46a97cdbd",
      "parents": [
        "9879d0eac8fe2aae19ca6a4a2a83222d6383afc2"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Aug 30 21:21:41 2017 +0000"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Aug 30 21:21:41 2017 +0000"
      },
      "message": "Revert \"Basic SIMD reduction support.\"\n\nThis reverts commit 9879d0eac8fe2aae19ca6a4a2a83222d6383afc2.\n\nGetting these type check failures in some builds. Need time to look at this better, so reverting for now :-(\n\n\ndex2oatd F 08-30 21:14:29 210122 226218 \ncode_generator.cc:115] Check failed: CheckType(instruction-\u003eGetType(), locations-\u003eInAt(0)) PrimDouble C\n\nChange-Id: I1c1c87b6323e01442e8fbd94869ddc9e760ea1fc\n"
    },
    {
      "commit": "9879d0eac8fe2aae19ca6a4a2a83222d6383afc2",
      "tree": "c75ab69be15630f86824bb202577eaa1ff91c4ee",
      "parents": [
        "60f734443d54d48fad86dce6d80d8cef22a134d0"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Aug 15 10:51:25 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Aug 30 09:10:40 2017 -0700"
      },
      "message": "Basic SIMD reduction support.\n\nRationale:\nEnables vectorization of x +\u003d .... for very basic (simple, same-type)\nconstructs. Paves the way for more complex (narrower and/or mixed-type)\nconstructs, which will be handled by the next CL.\n\nTest: test-art-host test-art-target\n\nBug: 64091002\n\nChange-Id: I7880c135aee3ed0a39da9ae5b468cbf80e613766\n"
    },
    {
      "commit": "b79f4ac55c0bb177f541937d0678f2aa777e1c9a",
      "tree": "7c331aa30d3c38b4448070527ac02fdbd848f284",
      "parents": [
        "51e74b47f240187d336d9e688f5d7538366f2edf"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Jul 10 10:10:37 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Jul 13 16:50:03 2017 -0700"
      },
      "message": "Added GVN related attributes to vector nodes.\n\nRationale: enables better GVNing of vector operations,\nalso pays off some technical debt by adding unit tests\nfor vector nodes.\n\nThis is a revert^2 of a79f0b5deb932aa44e227c94c4ad09082b3ab4c7\n(failed some of the existing checker test due to\nmoving scalar replication; fix was setting can-be-moved\nattribute correctly on that node).\n\nBug: 63538372\n\nTest: test-art-host, test-art-target\n\nChange-Id: I2f29c317354b5e4bf520829232aef17931305ea6\n"
    },
    {
      "commit": "9858bf70c9af425f5f712caca7b51b49c806b271",
      "tree": "e70e88c83c8260fbea01b258d3d221cc31d38d8d",
      "parents": [
        "a79f0b5deb932aa44e227c94c4ad09082b3ab4c7"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Sat Jul 08 12:34:55 2017 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Sat Jul 08 12:34:55 2017 +0000"
      },
      "message": "Revert \"Added GVN related attributes to vector nodes.\"\n\nFails armv8 checker tests.\n\nThis reverts commit a79f0b5deb932aa44e227c94c4ad09082b3ab4c7.\n\nChange-Id: I8913743f241febbbb24c0662af76397e87e59cd1\n"
    },
    {
      "commit": "a79f0b5deb932aa44e227c94c4ad09082b3ab4c7",
      "tree": "2d16c2876f6ccbc8ca1b9f6bf7fe43523a4132e3",
      "parents": [
        "4c4d9df7c79747978d2f927994a7b3c11a079075"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Jul 05 17:19:41 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Jul 06 11:58:20 2017 -0700"
      },
      "message": "Added GVN related attributes to vector nodes.\n\nRationale: enables better GVNing of vector operations,\nalso pays off some technical debt by adding unit tests\nfor vector nodes.\n\nTest: test-art-host, test-art-target\n\nChange-Id: I2aa886b894bb6a0961823ae309cf8cf44984cf4a\n"
    },
    {
      "commit": "a1633a7077781d9c64a77b27deb1707d1a56906d",
      "tree": "505f2560cfd247b2e1aab86d3ab96e5c399cb05d",
      "parents": [
        "a774575ae3af3d46955f941ddd08a79caf2aaa94",
        "c8e93c736c149ce41be073dd24324fb08afb9ae4"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue May 16 15:56:01 2017 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Tue May 16 15:56:04 2017 +0000"
      },
      "message": "Merge \"Min/max SIMDization support.\""
    },
    {
      "commit": "c8e93c736c149ce41be073dd24324fb08afb9ae4",
      "tree": "8e7154cf1bbcee8f5837ee9cb930174e2516ac03",
      "parents": [
        "92f4672f811a4eccdc596f7c2235804abd196fde"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@ajcbik2.mtv.corp.google.com",
        "time": "Wed May 10 10:49:22 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon May 15 11:44:58 2017 -0700"
      },
      "message": "Min/max SIMDization support.\n\nRationale:\nThe more vectorized, the better!\n\nTest: test-art-target, test-art-host\n\nChange-Id: I758becca5beaa5b97fab2ab70f2e00cb53458703\n"
    },
    {
      "commit": "e1811ed6b57a54dc8ebd327e4bd2c4422092a3a0",
      "tree": "e3ce48e66190c11a8b5342f4ec0d1046ba28d788",
      "parents": [
        "7113885fcd983b33ee1e350865d21517d6297843"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu Apr 27 16:50:47 2017 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu May 11 10:06:04 2017 +0100"
      },
      "message": "ARM64: Share address computation across SIMD LDRs/STRs.\n\nFor array accesses the element address has the following structure:\nAddress \u003d CONST_OFFSET + base_addr + index \u003c\u003c ELEM_SHIFT\n\nTaking into account ARM64 LDR/STR addressing modes address part\n(CONST_OFFSET + index \u003c\u003c ELEM_SHIFT) can be shared across array\naccess with the same data type and index.\n\nFor example, for the following loop 5 accesses can share address\ncomputation:\n\nvoid foo(int[] a, int[] b, int[] c) {\n  for (i...) {\n    a[i] \u003d a[i] + 5;\n    b[i] \u003d b[i] + c[i];\n  }\n}\n\nTest: test-art-host, test-art-target\n\nChange-Id: I46af3b4e4a55004336672cdba3296b7622d815ca\n"
    },
    {
      "commit": "d58bc3212a968fe5a2e1fba51df9a7efedcf1b60",
      "tree": "62d442542629674b503d7005977e73c99b3d5d37",
      "parents": [
        "18df7714111bdd3c5737f1ef2fa587d9957f8a2f"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon May 01 14:49:18 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon May 01 15:14:27 2017 -0700"
      },
      "message": "Allow same-length integral type mixing in SIMD.\n\nRationale:\nJust like the incoming sequential code, the SIMD\ncode allows for some type matching, as long as\nit is integral and same length.\n\nBug: 37764324\nTest: test-art-target, test-art-host\nChange-Id: Ide1c5403e0f3b8c5372e8ac6dd282d8211ca8f1b\n"
    },
    {
      "commit": "db14fcf45effb7dd4b3febd697ff5f0541119835",
      "tree": "4197a7be031e7206b1c4f55a51821e9b273b1b36",
      "parents": [
        "06660db82d6b3d59080584431addf3797a468a70"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Apr 25 15:53:58 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Tue Apr 25 16:13:55 2017 -0700"
      },
      "message": "Pack booleans in the already existing bit field.\n\nAlso adds is_string_char_at boolean in preparation of\n[un]compressed string vectorization support.\n\nTest: test-art-target, test-art-host\nChange-Id: Ia99b28564727bf91b3d5cfc49f6d40a4dd1ffd3b\n"
    },
    {
      "commit": "8de5916666ab5d146ac1bdac7d7748e197ae347e",
      "tree": "87a7cfda1a91ef4335f78a59edf2d5fcca6e8e46",
      "parents": [
        "f99f62f8e04aecbbe1615e242a19ac475f66e565"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Apr 21 09:42:01 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Apr 21 11:00:26 2017 -0700"
      },
      "message": "Factor vector unary/binary shared code out into superclass.\n\nTest: test-art-target, test-art-host\nChange-Id: I42770d9a9142f2e53d3b5bd60bd25593b2154a7c\n"
    },
    {
      "commit": "f34dd206d0073fb3949be872224420a8488f551f",
      "tree": "b24b451af6efdd9f67c4cbd5c37ebb4ec6a4aaad",
      "parents": [
        "1f56cb5c594f5757085820b1042988d10f02bb0b"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Mon Apr 10 17:41:46 2017 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu Apr 20 00:21:29 2017 +0100"
      },
      "message": "ARM64: Support MultiplyAccumulate for SIMD.\n\nTest: test-art-host, test-art-target.\n\nChange-Id: I06af8415e15352d09d176cae828163cbe99ae7a7\n"
    },
    {
      "commit": "f3e61ee363fe7f82ef56704f06d753e2034a67dd",
      "tree": "a00f1fce4a2e284b0a03f941f530afc5b5c56b59",
      "parents": [
        "741a81af441cbcb7255229bf250bc009d2894e92"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Apr 12 17:09:20 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Apr 19 10:30:57 2017 -0700"
      },
      "message": "Implement halving add idiom (with checker tests).\n\nRationale:\nFirst of several idioms that map to very efficient SIMD instructions.\nNote that the is-zero-ext and is-sign-ext are general-purpose utilities\nthat will be widely used in the vectorizer to detect low precision\nidioms, so expect that code to be shared with many CLs to come.\n\nTest: test-art-host, test-art-target\nChange-Id: If7dc2926c72a2e4b5cea15c44ef68cf5503e9be9\n"
    },
    {
      "commit": "6daebeba6ceab4e7dff5a3d65929eeac9a334004",
      "tree": "6aa2948896c6a731531451840a9a8bb26854cdd8",
      "parents": [
        "7cd18fb5a7ce83d98b1bbc3c55583fc5f93dc16f"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Apr 03 14:35:41 2017 -0700"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Apr 05 09:24:01 2017 -0700"
      },
      "message": "Implemented ABS vectorization.\n\nRationale:\nThis CL adds the concept of vectorizing intrinsics\nto the ART vectorizer. More can follow (MIN, MAX, etc).\n\nTest: test-art-host, test-art-target (angler)\nChange-Id: Ieed8aa83ec64c1250ac0578570249cce338b5d36\n"
    },
    {
      "commit": "f8f5a16ed7bad1e18179e38453e59c96a944de10",
      "tree": "53369083a97103563467cc5910a439a1864dd0b1",
      "parents": [
        "7298b1ae3e9af5fdb46d168302a26cfbf5d475f5"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Mon Feb 06 15:35:29 2017 -0800"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Mar 31 10:58:11 2017 -0700"
      },
      "message": "ART vectorizer.\n\nRationale:\nMake SIMD great again with a retargetable and easily extendable vectorizer.\n\nProvides a full x86/x86_64 and a proof-of-concept ARM implementation. Sample\nimprovement (without any perf tuning yet) for Linpack on x86 is about 20% to 50%.\n\nTest: test-art-host, test-art-target (angler)\nBug: 34083438, 30933338\n\nChange-Id: Ifb77a0f25f690a87cd65bf3d5e9f6be7ea71d6c1\n"
    }
  ]
}