)]}' { "log": [ { "commit": "692be80cb2278ae585a776a163bc4b3ef60cae88", "tree": "7ddadb6753024b2b6b864a192e56c4a4047354ee", "parents": [ "9a4f003f9a6da8e4c6ee279bd2a13aac37648183" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Aug 29 15:52:59 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri Aug 31 14:46:26 2012 -0700" }, "message": "Quick compiler: reuse llvm context \u0026 ir builder\n\nWith this CL, we avoid setting up an llvm context, module and intrinsic\ndefinitions for each method, and considerably speed up compilation time.\nThis does not represent a final form - we\u0027ll be reworking the compiler driver\nto support Quick \u0026 Portable via the command line, and this code will likely\nchange at that time.\n\nChange-Id: I19e298a011141c3bc35c4f28175b2b20653fd5e4\n" }, { "commit": "9a4f003f9a6da8e4c6ee279bd2a13aac37648183", "tree": "ce78afe7c842c8ff99d52c0a09bfe758d67d037f", "parents": [ "cfb21d92796087963c092b69110a2e7ff7a03a55" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Aug 30 16:17:40 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Fri Aug 31 10:49:06 2012 -0700" }, "message": "Remove the THROW_VERIFICATION_ERROR op and supporting code.\n\nChange-Id: Idc40a2c379048c7e3d74f50b2bd765a507a417ce\n" }, { "commit": "08f753d5859936f8d3524e9e4faa6cee353873ea", "tree": "5679a9ad8be6827e2a10de282cd28e3d000917de", "parents": [ "b0b2be7688109cff548d2ddc8f02eecbad49ecd2" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Aug 24 14:35:25 2012 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Aug 28 11:34:56 2012 -0700" }, "message": "Avoid compile time rewriting of dex code by verifier.\n\nCompile time rewriting of dex code leads to dead code that is causing\nissues with the LLVM compiler. Make instantiation and incompatible class\nchange errors be detected in slow path field and invoke logic so its\nsafe for the compile time verification just to softly fail the effected\nclasses.\n\nThis change places incompatible class change logic into the class\nlinkers ResolveMethod and consequently changes a number of APIs.\n\nChange-Id: Ifb25f09accea348d15180f6ff041e38dfe0d536e\n" }, { "commit": "7fbee0731b14b5bf392a4254f5cd84685ab517da", "tree": "b24cf6d9eed7935e3b26d63cf2292fd8c008005b", "parents": [ "f3a26411e0e8b56b64d184d3e946e72f9c31e4c7" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Fri Aug 24 17:56:54 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Mon Aug 27 11:33:05 2012 -0700" }, "message": "Preliminary changes to allow mips target to build.\n\nIt compiles, but it doesn\u0027t work yet.\n\nChange-Id: I2973a03bd956d8d398b9cfd1047e66fbf3ff439c\n" }, { "commit": "ca7a5e484ac02927247cc77ad40f291bf6613ed5", "tree": "5dd6f55984fe8eb0dd2cf80bd3b2aff5f514afa2", "parents": [ "b18e77abdb06a443744fbb6589e0932fa89f6073" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon Aug 20 11:12:18 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Thu Aug 23 15:22:25 2012 -0700" }, "message": "Quick compiler: restore optimizations\n\nThis CL re-enables optizations on the Quick compile path.\nNotes:\n\n o Although all optimization are enabled, several are now useless\n because of llvm and bitcode constraints:\n - Large method de-optimization (i.e. - skipping expensive dataflow\n analysis) can\u0027t be done because we have to do the analysis to\n produce a CFG that makes the bitcode verifier happy.\n - Small method pattern matching isn\u0027t applicable w/ bitcode (though\n I can probably do something similar in the Quick backend, but\n looking for bitcode instead of dex patterns).\n - Branch fusing doesn\u0027t translate to bitcode.\n - Bitcode generation has de-optimized code layout. We\u0027ll try to\n repair the damage in a subsequent CL.\n\n o There is an ugly workaround related to the way we\u0027re loading and\n unloading the compiler .so containing llvm. [See comment in compiler.cc]\n\n o We\u0027re still running single-threaded - need to add the magic to allow\n multi-threaded use of llvm.\n\n o With the CL, the phone boots, all target tests pass and all cts VM\n tests pass (except those being dealt with via a verifier change).\n\n o Compile time is pretty bad - when flashing it\u0027s best to follow\n with an adb sync to avoid on-device compilation of system apps.\n\nChange-Id: I1c98f9e64aefbcbd24b957c71544c28450eb2023\n" }, { "commit": "c9f40dd0a3dba696fc694d51fb82b61dcff19066", "tree": "c4c44c15500e53b78e9988983301823c11d18c76", "parents": [ "3d71d80626fdc0fe1f61c84bb52e9f7d96c95060" ], "author": { "name": "Bill Buzbee", "email": "buzbee@google.com", "time": "Wed Aug 15 11:35:25 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Aug 15 13:21:36 2012 -0700" }, "message": "Restore \"CFG rework for explicit exception edges\"\n\nRestores, with fix, I9fa359c912e25ca6a75e2f69d0975126d0687c33\n\nHere\u0027s the original commit message:\n\nPreviously, basic blocks were terminated by any Dalvik opcode\nwhich might throw, and the exception edges were represented\nas a list of successor basic blocks. This resulted in a\nSSA renaming bug: any Dalvik register definition caused by\na throwing instruction (such as IGET) would incorrectly be considered\nto be visible across the exception edges. For the Art compiler (and JIT)\nthis was a benign bug. But for llvm, it means an invalid CFG.\n\nThe other problem this CL is addressing is the llvm bitcode requirement\nthat all exception edges be explicit. Because we can\u0027t use\nthe llvm bitcode \"invoke\" (it doesn\u0027t match our exception handling),\nall exception edges must be represented as explicit branches in the\nbitcode (further contributing to the llvm bitcode bloat).\n\nWe split all potentially throwing instructions into two parts: a\ncheck prologue followed by the body. If there are any catch blocks\nassociated with the potentially throwing instruction, we make a call\nto the intrinisc dex_lang_catch_targets(). Though it should never\nexpand into actual code, this intrinsic returns a switch key that\nfeeds into an immediately-following switch statement. That switch\nstatement will include edges to all necessary catch blocks, with the\ndefault target referencing the block conaining the \"work\" portion of\nthe pair.\n\nIncluded in this CL are also fixes for .dot file generation\n(previously there was an issue with non-unique block names), and an\nenhancement to include the block number on Phi incoming arcs.\n\nAlso reworked dissasembly to use StringPrintf.\n\nNote: the insertion of new basic blocks following computation of\ndepth-first-search order badly degrades code layout. DFS order\ncomputation can be expensive, so I\u0027ll be looking for a workaround\nin a future CL to avoid a full dfs order regeneration.\n\nWith this CL, the device boots, all target tests pass, all methods\nare converted to Greenland Bitcode and all well-formed converted methods\npass llvm\u0027s function validation pass without error or warning.\n\nWe still have some cts failures related to the verifier\u0027s\ninstruction rewriting to THROW_VERIFICATION_ERROR. In those cases\nwe can have a malformed graph - but we still must be able to convert\nit to legal llvm bitcode. If executed, it will throw.\n\nWe\u0027ll detect that situation and bitcast these mismatches away in a\nsubsequent CL.\n\n[Update: since this original CL, we\u0027ve determined that the\nTHROW_VERIFICATION_ERROR problem is best solved by changes in the\nverifier to avoid the problem of malformed code. Structural\nverification failures will be treated as hard.]\n\nThis reverts commit 937b73eea7a473395f3572e0db1fdc9c6a094db5\n\nChange-Id: I8ba7fe080d8720c14bf74a342403077c150e4a71\n" }, { "commit": "00f7d0eaa6bd93d33bf0c1429bf4ba0b3f28abac", "tree": "6a2172ece15c4699e6c2a67ce76f019db0a9a21d", "parents": [ "634ea28f78c4a138e6a1de54eae8696095422415" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Jul 19 15:28:27 2012 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Aug 14 10:45:52 2012 -0700" }, "message": "Global lock levels.\n\nIntroduce the notion of the mutators/GC being a shared-exclusive (aka\nreader-writer) lock. Introduce globally ordered locks, analysable by\nannotalysis, statically at compile time. Add locking attributes to\nmethods.\n\nMore subtly, remove the heap_lock_ and split between various locks that\nare held for smaller periods (where work doesn\u0027t get blocked). Remove\nbuggy Dalvik style thread transitions. Make GC use CMS in all cases when\nconcurrent is enabled. Fix bug where suspend counts rather than debug\nsuspend counts were sent to JDWP. Move the PathClassLoader to\nWellKnownClasses. In debugger refactor calls to send request and\npossibly suspend. Break apart different VmWait thread states. Move\nidentity hash code to a shared method.\n\nChange-Id: Icdbfc3ce3fcccd14341860ac7305d8e97b51f5c6\n" }, { "commit": "634ea28f78c4a138e6a1de54eae8696095422415", "tree": "9852d454d5168462f3d75c5497d6582cfb1e950f", "parents": [ "86e4671975752b112b2e8969ac6652c72c8e86c7" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Fri Aug 10 13:04:01 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Fri Aug 10 13:04:01 2012 -0700" }, "message": "Implemented inline of String charAton x86.\n\nChange-Id: I5899d5169096adf9b2563a7160c60d05e2ab3e9d\n" }, { "commit": "86e4671975752b112b2e8969ac6652c72c8e86c7", "tree": "44be48718a716ce58a7c087c33ddd264c7943450", "parents": [ "46a23638436afdf17330870ef150f5b8eb66410c" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Wed Aug 08 17:30:59 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Fri Aug 10 09:52:15 2012 -0700" }, "message": "Implemented inline of String indexOf and compareTo on x86.\n\nChange-Id: Ia141d4900e9ab9dd563e718af0d10dcd445794cb\n" }, { "commit": "77ae36b35d47393335bf5399cab9c91ccf08e88f", "tree": "736bfd865e7bfd7caf6c8bc282fa9d04d16232f7", "parents": [ "e37543ed52379bcf08f57ebb3510846294a7102c" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Tue Aug 07 14:18:16 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Tue Aug 07 16:24:08 2012 -0700" }, "message": "Fix and enable inlining of some intrinsics on x86.\n\nInlined min/max int, String isEmpty/length, and abs int/long.\n\nChange-Id: I24aa1b403ee5c8437d63c58dbe1504494ce106ef\n" }, { "commit": "0e3ac14885bb646b187cda5ff8dab08cf6c99b43", "tree": "31433c0319dd9a18cf8e260fd1585433f888ab2f", "parents": [ "1dc7e3eaf922b79f08dafde5656ad6a9928106b2" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Fri Aug 03 18:24:38 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Fri Aug 03 18:24:38 2012 -0700" }, "message": "Fix fused branches, so vm-tests work again.\n\nChange-Id: Ia6f4dce1a86f63cdf20a9ccb9df518f4ac590efa\n" }, { "commit": "626aaa987b171c0addab75d7d300a91c24f9a5cc", "tree": "020411da9658eae76036851f49c74515f8c6f481", "parents": [ "dcf8d7283bd51714f3faa55b631ae4103dc98b51", "63ebbb68631caaf1de0588ece186af4018c33cfd" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri Aug 03 14:44:06 2012 -0700" }, "committer": { "name": "Android Git Automerger", "email": "android-git-automerger@android.com", "time": "Fri Aug 03 14:44:06 2012 -0700" }, "message": "am 63ebbb68: Quick compiler: fix NOT_LONG codegen\n\n* commit \u002763ebbb68631caaf1de0588ece186af4018c33cfd\u0027:\n Quick compiler: fix NOT_LONG codegen\n" }, { "commit": "63ebbb68631caaf1de0588ece186af4018c33cfd", "tree": "5898dceb78e4753e2d2bb411204b5f3c7f47173d", "parents": [ "8b503db0432981c6b0b2271723f9bcf9448a554a" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri Aug 03 14:05:41 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri Aug 03 14:05:41 2012 -0700" }, "message": "Quick compiler: fix NOT_LONG codegen\n\nThe llvm ir-builder converts Not operands into xor w/ -1. Detect\nand restore original operation on the GBC to LIR path.\n\nChange-Id: I219bcdc6b2e3ee8bb6cfea4c0b159deb10207359\n" }, { "commit": "babda950caf2d577aa57102c3281f0f3c36f3d6d", "tree": "469a16ecb709ab0bad151f01bb15253be0d9512e", "parents": [ "8302576126efae240eb21c7545cda7982437bd26" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Aug 02 15:55:30 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Aug 02 15:57:46 2012 -0700" }, "message": "Populate call info and inline float/double conversions on x86.\n\nAlso cleaned up neg-float/neg-double implementation.\n\nChange-Id: I8e7fe76e36d3c31bae0a82a956691202c09b8e0c\n" }, { "commit": "8302576126efae240eb21c7545cda7982437bd26", "tree": "c49a698c034951cc6f3799472dabefb5ccdaaf7f", "parents": [ "937b73eea7a473395f3572e0db1fdc9c6a094db5" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Aug 02 11:08:56 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Aug 02 11:08:56 2012 -0700" }, "message": "Added thin-lock fast path for monitor-enter/exit on x86.\n\nChange-Id: Iba187ae1acde6e341ae510d4b47f59e6984fc354\n" }, { "commit": "937b73eea7a473395f3572e0db1fdc9c6a094db5", "tree": "73c6d5d2f44ac27b6750b5377b272dfd19618b02", "parents": [ "034f76b91225bea769d6185d7dad5e243af4ffa0" ], "author": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Wed Aug 01 16:09:16 2012 -0700" }, "committer": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Wed Aug 01 16:09:16 2012 -0700" }, "message": "Revert \"CFG rework for explicit exception edges\"\n\nThis reverts commit 8b503db0432981c6b0b2271723f9bcf9448a554a.\n\nChange-Id: I21d5255d827c63de6a229ef419f372fbcf4d16ed\n" }, { "commit": "f2ba9cbe81b0762a7c8c659cdb86ba79b2dbbc40", "tree": "3a7944e695c65fb25ebdcd27bc640b84e6f4fd38", "parents": [ "573b42936ba7fbf296452875cdcadedc619418ef", "8b503db0432981c6b0b2271723f9bcf9448a554a" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Aug 01 10:01:59 2012 -0700" }, "committer": { "name": "Android Git Automerger", "email": "android-git-automerger@android.com", "time": "Wed Aug 01 10:01:59 2012 -0700" }, "message": "am 8b503db0: CFG rework for explicit exception edges\n\n* commit \u00278b503db0432981c6b0b2271723f9bcf9448a554a\u0027:\n CFG rework for explicit exception edges\n" }, { "commit": "8b503db0432981c6b0b2271723f9bcf9448a554a", "tree": "fb729e6813484499ad983a08ddff844d6b576846", "parents": [ "9a2487f94efeb88016a695af823bf26799ef0f06" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri Jul 20 15:36:47 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Aug 01 09:52:02 2012 -0700" }, "message": "CFG rework for explicit exception edges\n\nPreviously, basic blocks were terminated by any Dalvik opcode\nwhich might throw, and the exception edges were represented\nas a list of successor basic blocks. This resulted in a\nSSA renaming bug: any Dalvik register definition caused by\na throwing instruction (such as IGET) would incorrectly be considered\nto be visible across the exception edges. For the Art compiler (and JIT)\nthis was a benign bug. But for llvm, it means an invalid CFG.\n\nThe other problem this CL is addressing is the llvm bitcode requirement\nthat all exception edges be explicit. Because we can\u0027t use\nthe llvm bitcode \"invoke\" (it doesn\u0027t match our exception handling),\nall exception edges must be represented as explicit branches in the\nbitcode (further contributing to the llvm bitcode bloat).\n\nWe split all potentially throwing instructions into two parts: a\ncheck prologue followed by the body. If there are any catch blocks\nassociated with the potentially throwing instruction, we make a call\nto the intrinisc dex_lang_catch_targets(). Though it should never\nexpand into actual code, this intrinsic returns a switch key that\nfeeds into an immediately-following switch statement. That switch\nstatement will include edges to all necessary catch blocks, with the\ndefault target referencing the block conaining the \"work\" portion of\nthe pair.\n\nIncluded in this CL are also fixes for .dot file generation\n(previously there was an issue with non-unique block names), and an\nenhancement to include the block number on Phi incoming arcs.\n\nAlso reworked dissasembly to use StringPrintf.\n\nNote: the insertion of new basic blocks following computation of\ndepth-first-search order badly degrades code layout. DFS order\ncomputation can be expensive, so I\u0027ll be looking for a workaround\nin a future CL to avoid a full dfs order regeneration.\n\nWith this CL, the device boots, all target tests pass, all methods\nare converted to Greenland Bitcode and all well-formed converted methods\npass llvm\u0027s function validation pass without error or warning.\n\nWe still have some cts failures related to the verifier\u0027s\ninstruction rewriting to THROW_VERIFICATION_ERROR. In those cases\nwe can have a malformed graph - but we still must be able to convert\nit to legal llvm bitcode. If executed, it will throw.\n\nWe\u0027ll detect that situation and bitcast these mismatches away in a\nsubsequent CL.\n\nChange-Id: I9fa359c912e25ca6a75e2f69d0975126d0687c33\n" }, { "commit": "573b42936ba7fbf296452875cdcadedc619418ef", "tree": "8d0edb778bd3b5e598fedb1aa9fdc45f9f6ac585", "parents": [ "bb5f32837926bde201bf5744778dcf2573ea0c68" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Mon Jul 30 16:37:41 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Mon Jul 30 16:37:41 2012 -0700" }, "message": "Enable load store elimination on x86.\n\nIncludes a fix to prevent stores from being sunk between cmp and jcc\nops. Also fixes neg-float/double when the source and destination are the\nsame register. All optis are enabled by default on x86 now.\n\nChange-Id: Ie6f1a3a5ba94fd1b5298df87779d70d9868e8baa\n" }, { "commit": "4b771a09fe1d947dee7265e3c018d7f1dd89a5d3", "tree": "cfb02aaca1f8d389c73c5f6996775734859c7e5f", "parents": [ "8772f7d8b066887340e39bcb99a0009dd168b4d2" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Wed Jul 25 15:07:21 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Mon Jul 30 09:56:41 2012 -0700" }, "message": "Implemented fused branches for long and fp on x86.\n\nAlso marked mips fused branches as unimplemented.\n\nChange-Id: I2d845874d73b03dfadcaf5a56d1d315bb1e63763\n" }, { "commit": "8772f7d8b066887340e39bcb99a0009dd168b4d2", "tree": "10c43fd229bd9d74ee624ee219c874454253544c", "parents": [ "f1ea6b072b8b473eabf91d1d582fb5966ffea4ba", "9a2487f94efeb88016a695af823bf26799ef0f06" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri Jul 27 06:46:50 2012 -0700" }, "committer": { "name": "Android Git Automerger", "email": "android-git-automerger@android.com", "time": "Fri Jul 27 06:46:50 2012 -0700" }, "message": "am 9a2487f9: Quick compiler - NOT_LONG and verification fixes\n\n* commit \u00279a2487f94efeb88016a695af823bf26799ef0f06\u0027:\n Quick compiler - NOT_LONG and verification fixes\n" }, { "commit": "9a2487f94efeb88016a695af823bf26799ef0f06", "tree": "19525acc9c56763a35a12afc2e900fa346c3444d", "parents": [ "854029c13351fd3a8f7794eb6c2c73af0fde8ac8" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Thu Jul 26 14:01:13 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Thu Jul 26 14:01:13 2012 -0700" }, "message": "Quick compiler - NOT_LONG and verification fixes\n\nWe continue to have issues when the verifier rewrites Dalvik\nbyte codes. This is a workaround to fix the GBC -\u003e LIR\nconversion, but I suspect I\u0027m going to have to add a dead code\nelimination pass to get things working properly for llvm. The\nbasic problem is that if the re-written instruction defined a\nDalvik virtual register, then we lose the definition. The\nMIR to GBC converter doesn\u0027t handle uses without definitions\nvery well.\n\nChange-Id: Ia235c299b686ce080755f9bb4c05c719c16c0d77\n" }, { "commit": "f1ea6b072b8b473eabf91d1d582fb5966ffea4ba", "tree": "7b964348bca02512e1d1591269127147c2952047", "parents": [ "08836618c4505544c2a134ee317543829c07a5e9", "854029c13351fd3a8f7794eb6c2c73af0fde8ac8" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Wed Jul 25 10:06:17 2012 -0700" }, "committer": { "name": "Android Git Automerger", "email": "android-git-automerger@android.com", "time": "Wed Jul 25 10:06:17 2012 -0700" }, "message": "am 854029c1: Fixes to x86 register promotion and load hoisting.\n\n* commit \u0027854029c13351fd3a8f7794eb6c2c73af0fde8ac8\u0027:\n Fixes to x86 register promotion and load hoisting.\n" }, { "commit": "854029c13351fd3a8f7794eb6c2c73af0fde8ac8", "tree": "3f2968be0023fa1d22303e74a989a1961ea402c9", "parents": [ "22fc28eb95191a1957025b219452c09c7fbb6bd0" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Mon Jul 23 17:31:30 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Tue Jul 24 16:33:07 2012 -0700" }, "message": "Fixes to x86 register promotion and load hoisting.\n\nFixed a check to ensure that the mvzxb source register can be byte\naccessed, not the destination reg.\n\nDisabled branch fusion for x86 since code generation for that is\nunimplemented.\n\nChanged regId mask for x86 to allow proper masking of double registers.\n\nAlso added more output to the disassembler.\n\nChange-Id: Idc0a949755ec9ae7b6d5dba38caa5ac01fcc5713\n" }, { "commit": "1eb16c161c1c49153a0da60c5eea19e2543b49d6", "tree": "08ecb7f7bc1520e69c2356269d351195811e2e4a", "parents": [ "467ef4c9031f78129ca4658054d4057f8b9b5f2a", "703f2cd1f4d1eb5ab5c9792ca2de9ffb39378203" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Mon Jul 23 23:01:44 2012 -0700" }, "committer": { "name": "Android Git Automerger", "email": "android-git-automerger@android.com", "time": "Mon Jul 23 23:01:44 2012 -0700" }, "message": "am 703f2cd1: Numerous fixes to enable PromoteRegs, though it\\\u0027s still broken.\n\n* commit \u0027703f2cd1f4d1eb5ab5c9792ca2de9ffb39378203\u0027:\n Numerous fixes to enable PromoteRegs, though it\u0027s still broken.\n" }, { "commit": "703f2cd1f4d1eb5ab5c9792ca2de9ffb39378203", "tree": "652ceef30d52a13854c14bb0a6f586e96421f625", "parents": [ "e6e0651c7f0480e18d648200f8958c3463e82a2f" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Fri Jul 13 17:25:52 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Fri Jul 20 17:21:18 2012 -0700" }, "message": "Numerous fixes to enable PromoteRegs, though it\u0027s still broken.\n\n- Fixed ThrowNullPointerFromCode launchpad to load the array length\n directly into the necessary arg reg without clobbering the array\n pointer, since that value may be live afterwards.\n\n- genArrayPut use a temporary reg for bytes if the source reg is \u003e\u003d 4,\n since x86 can\u0027t express this.\n\n- Fixed the order that core regs are spilled and unspilled.\n\n- Correctly emit instructions when base \u003d\u003d rBP and disp \u003d\u003d 0.\n\n- Added checks to the compiler to ensure that byte opcodes aren\u0027t used\n on registers that can\u0027t be byte accessed.\n\n- Fixed generation of a number of ops which use byte opcodes, including\n floating point comparison, int-to-byte, and and-int/lit16.\n\n- Added rBP, rSI, and rDI to spill registers for the x86 jni compiler.\n\n- Various fixes and additions to the x86 disassembler.\n\nChange-Id: I365fe7dec5cc64d181248fd58e90789f100b45e7\n" }, { "commit": "462ef2008ccb79197f8210f0580bcdc61ffc3898", "tree": "035dc964b5d4df9a6b8572497337a7a1df923627", "parents": [ "0104594fb6aa2f03b45fdd37e05a75f60eadf826" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Thu Jul 19 09:27:50 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Thu Jul 19 09:27:50 2012 -0700" }, "message": "Quick compiler - delete unreferenced local\n\nChange-Id: Ic021e36c5d3a509eb5981555be504a99019b69a8\n" }, { "commit": "85eee02c456cd54f9e4110e90ebed6b55906e1bf", "tree": "07a8b4f12618eeec2d0f41dd484b7c1a0d7d01fa", "parents": [ "ea905deb5e2b84ad7acbccfd03bbbf2e759bbf45" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon Jul 16 22:12:38 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Tue Jul 17 15:42:22 2012 -0700" }, "message": "Quick compiler: various bug fixes\n\no Use appropriate size immediate for placeholder Values.\no Turn unexpected MOVE_RESULT into a warning for x86 (still need to\n implement this)\no Use the correct iput value to determine value type.\no I\u0027ve identified a bug with SSA renaming that shows up in three methods\n while doing a full build. Disable bitcode conversion for them until\n the fix is in place.\n\nChange-Id: I2762c913d83ef53b8b68dcde51fbe8463f209591\n" }, { "commit": "2a83e8f06031948741ae3dda3633433ddd669693", "tree": "8f189b330f9593746b6e4ab379bbf09b75e30020", "parents": [ "7c7679cd76e76b44c75a3e32a8727148d3ab9ada" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri Jul 13 16:42:30 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon Jul 16 14:20:36 2012 -0700" }, "message": "Quick compiler, fix wide bug\n\nIn Dalvik, 64-bit data items are represented as a pair of 32-bit\nregisters. The Art compiler maintained this notation, while llvm\nexpects properly typed data. During the conversion to bitcode, we\nmust drop the high word of pairs, while correctly typing the low.\n\nThis CL fixes several bugs related to this. \"Placeholder\" llvm\nValues are created only for the low word of pairs, and we now skip\nPhi node generation for high words. Doing this required a bit\nof tightening up of the size \u0026 type inference code (which previously\nwas able to get away with ignoring high words).\n\nAlso, I\u0027ve moved shift operations into intrinics because Dalvik\nand llvm have different ideas about what a shift means.\n\nBitcode generation is only supported for the Arm target at the\nmoment. With this CL, all target tests pass and the phone boots.\nSome caveats:\n\n o Performance data is not yet meaningful, either compile or\n run times.\n o When configured for Quick, we run single-threaded.\n o In a small percentage of methods, we generate invalid llvm\n bitcode (missing exception edges). As-checked-in, llvm\n function generation is turned off to avoid missing edge\n complaints (to enable testing of the Quick backend).\n\nChange-Id: I66932ffb44d299fcaf0a112e0d1c217c49341ccf\n" }, { "commit": "7c7679cd76e76b44c75a3e32a8727148d3ab9ada", "tree": "1d82f306be7eb0cd187170c0e7e17d9a0d6034da", "parents": [ "eb6f3a4f25c3c84ce9b7ea3d608347d159d3998c", "4be777b5efccbffddd6227d30ab1f658403e18cf" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri Jul 13 09:05:27 2012 -0700" }, "committer": { "name": "Android (Google) Code Review", "email": "android-gerrit@google.com", "time": "Fri Jul 13 09:05:27 2012 -0700" }, "message": "Merge \"Quick compiler: fix for missing defs\" into ics-mr1-plus-art" }, { "commit": "4be777b5efccbffddd6227d30ab1f658403e18cf", "tree": "a901c7f58cbe1cb1034a91acfdc78f4fddcaf463", "parents": [ "ca314c6a1be1b4cc11f4d284da90af7dc8a4ce25" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Thu Jul 12 14:38:18 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Thu Jul 12 21:20:33 2012 -0700" }, "message": "Quick compiler: fix for missing defs\n\nWhen the verifier replaces a Dex instruction, it may cause us\nto lose a definition, making the SSA graph invalid. This CL\ndeals with this situation by introducing dummy definitions.\n\nWith this CL, run-tests 042 and 075 pass. The only remaining\nrun-test failures are related to missing exception edges in the CFG.\nThe old compiler could infer some of them, while llvm requires all\nto be explicit.\n\nChange-Id: I471fa515d8717aa102713a05b0e4115bf656b78e\n" }, { "commit": "eb6f3a4f25c3c84ce9b7ea3d608347d159d3998c", "tree": "694b2c07db5301b438efd676822738aa0fc0fbeb", "parents": [ "654d3a217faf46310895a1825354d610c2f3d6c2", "fdffdf898f12d91765c7dbe7bcb1ccbbcd2b72d1" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Jul 12 17:37:55 2012 -0700" }, "committer": { "name": "Android (Google) Code Review", "email": "android-gerrit@google.com", "time": "Thu Jul 12 17:37:55 2012 -0700" }, "message": "Merge \"Fixes to enable TrackLiveTemps optimization on x86.\" into ics-mr1-plus-art" }, { "commit": "fdffdf898f12d91765c7dbe7bcb1ccbbcd2b72d1", "tree": "87a7c98d46415dce49aea9a9c73a1351a5d64626", "parents": [ "f1f863695b28f630abb772f50170fefaddc2fb91" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Wed Jul 11 16:08:43 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Jul 12 14:32:54 2012 -0700" }, "message": "Fixes to enable TrackLiveTemps optimization on x86.\n\n- Created new kRegRegStore instruction class for Movdrx, where the\n source is first, and the destination is second.\n\n- Reverted neg_float and neg_double implementation to prevent confusion\n of register types when optimizations are performed.\n\n- Swapped order of loads for wide values to prevent base pointer from\n being clobbered when the base pointer equals the low destination reg.\n\n- Implemented opRegCopyWide for general purpose reg source to floating\n point reg destination and vice versa.\n\n- Added more opcode coverage to x86 disassembler.\n\nChange-Id: I4e58eec91742cc51333003fa5a678ba5b23eb575\n" }, { "commit": "d5018897273f3b889f025a79ef28199ad2a640bf", "tree": "63477c7788be3ddaeea49a06b97bdc1293f65334", "parents": [ "f1f863695b28f630abb772f50170fefaddc2fb91" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Jul 11 14:23:40 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Jul 11 14:23:40 2012 -0700" }, "message": "Quick compiler - run-test bug fixes\n\nMiscellaneous bug fixes, largely dealing with making llvm happy\nwith consistent types. This CL causes the quick compiler to\nadditionally pass run-tests 004, 036, 044, 64, 068, 072, 074, 085.\nStill failing: 042, 053, 075.\n\nChange-Id: Ic3c9aa981e641ac68179d42d03b4c9b84cac9b85\n" }, { "commit": "f1f863695b28f630abb772f50170fefaddc2fb91", "tree": "9a5bdda08897530e998484a2a400ac34ff7962f4", "parents": [ "dcfdd2b03af29dcaf234d062a79acb919f130435" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Tue Jul 10 15:18:31 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Tue Jul 10 19:19:27 2012 -0700" }, "message": "Quick compiler - fix run-test 019\n\nTwo problems:\n 1. Was treating an array object store as a regular array store\n 2. Codegen bug that (somewhat disturbingly) existed in the\n non-quick code. I\u0027m a little surprised that it hadn\u0027t\n shown up before now, but it would tend to be masked if\n the array base register in question was promoted.\n\nChange-Id: I62bcb866174538ceedcc1309edcf22261237840a\n" }, { "commit": "a1da8a553681d1f7aec305610c8848c26373e0f0", "tree": "0e4f86f208c67a2a761d052a49a94b3bc9c659fa", "parents": [ "44a25bbc4626119d24d2cb7378212b6fd0093c19" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon Jul 09 14:00:21 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon Jul 09 14:00:21 2012 -0700" }, "message": "Quick compiler: complete switch support\n\nWith this CL, all Dex opcodes are handled. We pass 79 run-tests,\nand fail 12. Temporarily going single-threaded for the Quick\ncompiler (llvm\u0027s ir-builder dies otherwise - will figure out what I\nneed to do for multi-threaded operation in a later CL).\n\nChange-Id: I389e94d9a831096d4e7493460729933fb45e649e\n" }, { "commit": "f58c12c79cf11e6d6e3dd7db8f676d1edaf5d68b", "tree": "c18cf8229a9ba7e36b92934a6fb35aaf0e2259b6", "parents": [ "4f4dfc7ce0d309448d6fc47737c1f3c0a9eda7e5" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Tue Jul 03 15:06:29 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Tue Jul 03 15:27:27 2012 -0700" }, "message": "Quick compiler - packed switch support\n\nAdd support for PACKED_SWITCH. Uses the stock llvm switch operator\nplus additional metadata for the Quick path that the portable path\nmay freely ignore.\n\nChange-Id: I3f7cbf9d441d4cc53bf188beeb94d4178fef3e07\n" }, { "commit": "4f4dfc7ce0d309448d6fc47737c1f3c0a9eda7e5", "tree": "c5f92133bd4d3672483b045f7b192599b19f5bf9", "parents": [ "fbfc9a480fb5b31b0ca52449b0ce5a45c8cd377d" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon Jul 02 14:54:44 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon Jul 02 15:47:26 2012 -0700" }, "message": "Quick compiler - various bug fixes\n\nContinuing clean-up of the MIR-\u003eLLVMIR-\u003eLIR path. With this CL,\nall of run-test 003 passes except for tests which need switch\nsupport (unimplemented) and one of the Throw tests (I\u0027m apparently not\nfully describing all of the exception-related edges in the CFG).\n\nChange-Id: I2075357bc7c5419c873bb62d44c34fdb73424e29\n" }, { "commit": "76592633b491e294d78db2c4dbc44ca679004b71", "tree": "e836e4fb045e400b09326bd3228e7e6f8f416a6e", "parents": [ "101305f7ca3da8c665e3c5f7cdf9e1f22f009567" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri Jun 29 15:18:35 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri Jun 29 15:18:35 2012 -0700" }, "message": "Quick compiler: conversions, bug fixes\n\nAdded support for the remaining conversions, misc. bugs fixed. Still\nleft is switch support, rework of type handling and lots of bug\nfixes.\n\nChange-Id: Ib370a4176555d628f222e35776e0b3f0be8de0c4\n" }, { "commit": "101305f7ca3da8c665e3c5f7cdf9e1f22f009567", "tree": "7a71558261ec9fb6833e7cea4f7a9952b06cbe1f", "parents": [ "026b14660723c2b25a4f3ef6394f43a4fe64ba92" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Thu Jun 28 18:00:56 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri Jun 29 09:50:46 2012 -0700" }, "message": "Continued fleshout out of Quick compiler\n\nConversion support for IGET/IPUT, more array stuff, some conversions\nand miscellaneous bug fixes. Note that I\u0027m adding what I hope are\nintend to be temporary intrinsics to speed development.\n\nWith this CL, most of run-test 027 passes.\n\nChange-Id: Ib74233fba0aab3194c383be6f7330921c04a3a62\n" }, { "commit": "e296248a124ed8287b38a9225463696c18d84cd6", "tree": "ffa3305cfb89082b39982d5d617f408c13cf3e66", "parents": [ "837210218c82a4f8e69304e58f8d018dbeb313b8" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Jun 28 11:29:57 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Jun 28 11:39:22 2012 -0700" }, "message": "Fixes for x86 compiler optimizations.\n\nx86 works with all but a few optimizations turned on, and the broken\nones are still disabled for now. This change includes:\n\n- Flagging of opcodes to incidate register use and def. Also, made\n flagging more complete for loads/stores and set/use ccodes.\n\n- Fixes to load store elimination, though it still doesn\u0027t work yet.\n\n- Prevent double values that are loaded or stored from losing their\n FP_DOUBLE flag. Later optimizations use this sizing.\n\n- Renumbering of DOUBLE registers so they alias with FP regs when\n masked.\n\n- Add support in the disassembler to recognize shifts.\n\nChange-Id: I758cdce418409fdd84206ce295005d5c9ab635f8\n" }, { "commit": "8fa0fda8e1b6aa0a759990b3d32b78bb08065e0f", "tree": "4e87b99f5afdc564ee27eb3902e48d52c8795720", "parents": [ "6613de3585d726a246b5ee2597ddaef8b3c3a621" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Jun 27 15:44:52 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Jun 27 15:44:52 2012 -0700" }, "message": "Quick compiler: support for arrays, misc.\n\nContinuing to flesh out support in the Quick compiler. Mostly\narray-related. Also, added runtest 028-array-write to the set of\npassing tests.\n\nChange-Id: I3c8eaf4bb14e9327e4f5fc48de73c85a5d3efb54\n" }, { "commit": "6613de3585d726a246b5ee2597ddaef8b3c3a621", "tree": "cb2f55860eaea7b87daa28f8832ded3b4c6d2efd", "parents": [ "50b69e30ef69e72a48b1789622caaab4de203cfb", "32412961b1c912faba30cdecd3560ab05e463807" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Jun 27 09:05:14 2012 -0700" }, "committer": { "name": "Android (Google) Code Review", "email": "android-gerrit@google.com", "time": "Wed Jun 27 09:05:14 2012 -0700" }, "message": "Merge \"Quick compiler exception support\" into ics-mr1-plus-art" }, { "commit": "32412961b1c912faba30cdecd3560ab05e463807", "tree": "8d7656dfd7394865442d0374dc7f3fcd5cd4972f", "parents": [ "4f1181fe061d3529f72e1237e7662bf9bc73c6e2" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Tue Jun 26 16:27:56 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Tue Jun 26 19:15:57 2012 -0700" }, "message": "Quick compiler exception support\n\nHandle MOVE_RESULT, THROW and THROW_VERIFICATION_ERROR. Enable\nruntests 007 and 014 to pass. Minor munging of the tests to make\nthem easier to selectively compile with the Quick compiler.\n\nChange-Id: I756def54d81771b144e8ebc213cd90077e23758b\n" }, { "commit": "271769a39b900a5f9f752cea318980e96367b55b", "tree": "87ef6f89813b8b660881f9f178bb534d0c4e1fc5", "parents": [ "4f1181fe061d3529f72e1237e7662bf9bc73c6e2", "365c10235438607541fa2259a5fec48061b90bd8" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Jun 26 15:22:43 2012 -0700" }, "committer": { "name": "Android (Google) Code Review", "email": "android-gerrit@google.com", "time": "Tue Jun 26 15:22:43 2012 -0700" }, "message": "Merge \"Increase use of ScopedJniThreadState.\" into ics-mr1-plus-art" }, { "commit": "365c10235438607541fa2259a5fec48061b90bd8", "tree": "26516a4985a8bbef4c8da36b99bf1e54af3ad24d", "parents": [ "147440427984816b6ed5235a9b1fb2cbf99496d0" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Jun 22 15:05:28 2012 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Jun 26 15:21:01 2012 -0700" }, "message": "Increase use of ScopedJniThreadState.\n\nMove the routines for changing Object* to jobject and vice-versa\n(AddLocalReference and Decode) to ScopedJniThreadState to enforce use of\nObject*s in the Runnable thread state. In the Runnable thread state\nsuspension is necessary before GC can take place.\n\nReduce use of const ClassLoader* as the code bottoms out in FindClass\nand with a field assignment where the const is cast away (ie if we\u0027re\nnot going to enforce the const-ness we shouldn\u0027t pretend it is).\n\nRefactor the Thread::Attach API so that we\u0027re not handling raw Objects on\nunattached threads.\n\nRemove some unreachable code.\n\nChange-Id: I0fa969f49ee6a8f10752af74a6b0e04d46b4cd97\n" }, { "commit": "4f1181fe061d3529f72e1237e7662bf9bc73c6e2", "tree": "ea4044920632370d170a8b1c37ec4729ceb859f4", "parents": [ "147440427984816b6ed5235a9b1fb2cbf99496d0" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri Jun 22 13:52:12 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Tue Jun 26 11:27:36 2012 -0700" }, "message": "Quick compiler: support for 006, 012, 013, 017\n\nContinued fleshing out of the Quick compiler. With this CL,\nwe\u0027re passing run-tests 006, 012, 013 and 017. Note minor\nchanges to the tests to allow for easy identification of methods\nwe want to run through the Quick path. Also, set up by default\nnow to dump bitcode file to /sdcard/Bitcode/\n\nChange-Id: I77ec73a87a21064273567802ddb44c4fdf71f9fd\n" }, { "commit": "4f2935ef077529cc41aa0b590262fa91acbf6558", "tree": "55e846dfa27b5eb92e68ae0b10f6819fb11e1900", "parents": [ "008fa5114f356861f74f086f0b0c50fe42ef2891" ], "author": { "name": "TDYa127", "email": "tdy@google.com", "time": "Fri Jun 22 06:25:03 2012 -0700" }, "committer": { "name": "Shih-wei Liao", "email": "sliao@google.com", "time": "Fri Jun 22 09:45:27 2012 -0700" }, "message": "Fix missed suspend check.\n\nChange-Id: Id926b6290f2ace12a1e2d36f59303591a896763b\n" }, { "commit": "0399dde18753aa9bd2bd0d7cf60beef154d164a4", "tree": "ea88327c01ca321074aaa59b97e4c54348802937", "parents": [ "de5705dcf4ab5f92d48e144bcd7b59f7bcd18e16" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Jun 06 17:09:28 2012 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Jun 21 22:11:24 2012 -0700" }, "message": "Remove Frame, merge shadow and quick representations.\n\nChange-Id: I5ae03a5e52111792d2df7e83cbd89ab25777844b\n" }, { "commit": "5937e047bd15b3ce48c95e0457e501ab6feb7234", "tree": "73dbd27330a1720bff179210fff6d260465071f6", "parents": [ "713b00e106f6f27142a3273acf496865729c936f", "748474146da0c6484fa3dca0a700f612d47550c3" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Thu Jun 21 09:15:02 2012 -0700" }, "committer": { "name": "Android (Google) Code Review", "email": "android-gerrit@google.com", "time": "Thu Jun 21 09:15:02 2012 -0700" }, "message": "Merge \"Fix a bunch of lint.\" into ics-mr1-plus-art" }, { "commit": "748474146da0c6484fa3dca0a700f612d47550c3", "tree": "58837d0fa82d4099eb4b82b2fd3d2bbf4294e4aa", "parents": [ "92e3134cd84c134f167175288671a1e6838c908f" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Wed Jun 20 18:10:21 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Thu Jun 21 09:14:27 2012 -0700" }, "message": "Fix a bunch of lint.\n\nThere are still about 1800 lint warnings, so don\u0027t get too excited...\n\nChange-Id: I2394bd6e750b94060231378b3a7a88b87f70c757\n" }, { "commit": "e33c92b3b9c75b7a5c685639d289d6381b2694a9", "tree": "0b0d108988fa893131780539ba28ad5c6f2a9166", "parents": [ "83475c208287fe671f12a1c59f914194b2caf1db" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Jun 20 17:45:00 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Jun 20 17:45:00 2012 -0700" }, "message": "Fix string.compareTo regression\n\nThe recent restructuring that fused invokes and their subsequent\nmove-results caused a performance regression in the compareto\nmicrobenchmarks. The restructuring CL was being a little over conservative\nand disabled detection of special inlined functions when encountering\none who\u0027s subsequent move-result was missing. The string.compareto\nmicrobenchmarks do a bunch of compareto\u0027s and ignore the result.\n\nIt\u0027s perfectly legal to ignore the return value, and the generaated\ncode handles this case just fine by defaulting back to the special\nreturn registers if not move-result is found. Remove the check.\n\nChange-Id: Idca9d10404ced4d6b11be6ea00d62ed429345e85\n" }, { "commit": "83475c208287fe671f12a1c59f914194b2caf1db", "tree": "65d1f065aae991d42d10e055c89de4992652db92", "parents": [ "4d999fe696d43de5872f7be293e8a749cb69beaf", "ad8f15e0b13383b2eaa2486b230debeae7a55661" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Jun 20 15:14:24 2012 -0700" }, "committer": { "name": "Android (Google) Code Review", "email": "android-gerrit@google.com", "time": "Wed Jun 20 15:14:24 2012 -0700" }, "message": "Merge \"Milestone: close Quick side channel communication\" into ics-mr1-plus-art" }, { "commit": "ad8f15e0b13383b2eaa2486b230debeae7a55661", "tree": "0939aa6dee5f24dc4ae21dd2c06db0265d4682ca", "parents": [ "83c26f9c7ee42b0037d2679f6f37dd28a3f13af7" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon Jun 18 14:49:45 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Jun 20 15:12:44 2012 -0700" }, "message": "Milestone: close Quick side channel communication\n\nThis CL elminates side-channel communication between the Quick\nCompiler\u0027s Dex-\u003eMIR-\u003eLLVM-IR and LLVM-IR-\u003eLIR lowering stages by clearing\nkey data structures between the two stages.\n\nThe purpose if to flush out any hidden information transfer, and thus\nensure that the GreenlandIR representation of the program is sufficient.\n\nNote that as of this change, we\u0027ve lost all register promotion info\nso the Quick compiler will generate non-promoted code. A near-future\nCL will restore that info from the MethodInfo intrinsic.\n\nChange-Id: I797845f1fc029bc03aac3ec20f8cd81f917817ca\n" }, { "commit": "44335e189951a863607049a33571932fb6a2a841", "tree": "0d8bfb84cd0830523cc7ec5fd0eabed0770ae6de", "parents": [ "83c26f9c7ee42b0037d2679f6f37dd28a3f13af7" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Mon Jun 18 13:48:25 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Mon Jun 18 14:38:46 2012 -0700" }, "message": "Fix arguments to throw of ArrayIndexOutOfBounds exception.\n\nThe handler expects the array length in the second arg, but x86 was\npassing the array pointer.\n\nChange-Id: I0439b93f70569f3e1aa5ef34b9dfa75062935170\n" }, { "commit": "6969d50c820bd63043940b0e0f0ddc6e6ac763b0", "tree": "e6e02ddea49c4ad6706931a62172bce9a921d8d0", "parents": [ "e5f01223ae03b89767dc7881d75dca061121ee36" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri Jun 15 16:40:31 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Sat Jun 16 14:56:03 2012 -0700" }, "message": "Invoke support for Quick Compiler\n\nFleshed out invoke and const-string support. Fixed a bug in Phi node\ninsertion.\n\nWith this CL, the \"Recursive Fibonacci\" and \"HelloWorld\" milestones are\nmet.\n\nAdded are a set of \"HL\" (for High-Level) invoke intrinsics. Until we\ncomplete the merging of the Quick \u0026 Iceland runtime models the invoke\ncode sequences are slightly different. Thus, the Greenland IR needs\nto represent invokes at a somewhat higher level than Iceland. The\ntest for fast/slow path needs to happen during the lowering of the\nHLInvokeXXX intrinsics in both the Quick and Portable paths.\n\nThis will generally be the case in the short term - push fast/slow\npath determination below the Greenland IR level. As unification\nproceeds, we\u0027ll pull as much as makes sense into the common front end.\n\nChange-Id: I0a18edf1be18583c0afdc3f7e10a3e4691968e77\n" }, { "commit": "e5f01223ae03b89767dc7881d75dca061121ee36", "tree": "67be365994561e90a2adc8e871989a706f070a1d", "parents": [ "dc07f948e2b5e2355a9e26f7e0fd582c3d4cb182" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Thu Jun 14 15:19:35 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri Jun 15 11:24:22 2012 -0700" }, "message": "Fixes for invoke/move-result fusing, recursion bug\n\nFix for the Arm move-result fusing - NEW_FILLED_ARRAY wasn\u0027t\nbeing handled properly. Still keeping x86 disabled. Replaced\nthe recursive dfs order computation with an iterative version. Could\nbe improved, but I\u0027ll wait to see if it shows up as an issue during\ncompile-time profiling.\n\nKeeping the old recursive version code in place for a little while until\nwe\u0027re sure the new mechanism computes the exact same orderings.\n\nWith this CL we stop running out of thread stack memory on the 003\nruntest.\n\nChange-Id: Iab80f42135b081a3f49e1ee26a29220e602ae7e8\n" }, { "commit": "1395b1e06c1d0ff5155b0c5d113ad3bd6f163c07", "tree": "65e1aa9f24ac5d4d3469832756b4f92981d40176", "parents": [ "1c678be1960b48a8df82ec2d1f9a0bd4c8f0ea95" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Wed Jun 13 18:05:13 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Jun 14 15:01:01 2012 -0700" }, "message": "Patches to x86 compilation to fix vm tests on emulator.\n\nnot-int and not-long were unimplemented previously.\n\ncmp-long would return the wrong value with Long.MIN_VALUE.\n\nrem-double and rem-float now use a c helper. This is because fprem may\nnot fully compute the result on the first invocation and would need to\nbe looped to completion.\n\nChange-Id: Idf5f6349a63b19d395a3d89434b5b35c430ae3d3\n" }, { "commit": "45623b86ad048aa2c51c5ffdba0535654bc447c7", "tree": "b5c0cf210c8ab8c345c30226a5e69d5912fad49f", "parents": [ "f96a92f795bcfc492bd28cffb7784325d28eba45" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Thu Jun 14 11:15:00 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Thu Jun 14 11:21:45 2012 -0700" }, "message": "Disable move-result fusing\n\nWork around bug in invoke/move-result fusing. With this, runtests 003, 004,\n010 and 044 work again.\n\nChange-Id: Iecf8467434b32a1441635532c02b28756c057c83\n" }, { "commit": "52ed776c9b71abbdee7c24119859371549bd3172", "tree": "99702bcfcd56063a56f15faa0383912096ef2d9f", "parents": [ "3b3dbddcbc7a7bee505a608061304f9b26a91750" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Jun 13 23:43:14 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Jun 13 23:43:14 2012 -0700" }, "message": "FP breakage workaround\n\nThis should get the x86 runtests passing again until I track down\nthe root cause. The bug is related to the invoke/move_result fusing,\nbut the problem remained after fixing the issue with x86 using a\ndifferent return register for floats. This CL disables the fusing for\nx86.\n\nChange-Id: Id2b2ebc5ebd4089fe3053d8f077dcadba3466de0\n" }, { "commit": "3b3dbddcbc7a7bee505a608061304f9b26a91750", "tree": "a8973c0ce937e6f11136804dabdcd14ee2e2e509", "parents": [ "1a5e1e7b3b2340a6ac08c53220900d4044ac3e4c" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Jun 13 13:39:34 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Jun 13 13:51:40 2012 -0700" }, "message": "More Quick compiler mir/bb cleanup\n\nRemoved the references to MIR and BasicBlock from the generator\nfor NEW_ARRAY and the compare/branch. The previously-introduced\nInvokeInfo structure was sufficient for handling the NEW_ARRAY call,\nso renamed it to cover both.\n\nThis CL should end this round of restructuring.\n\nChange-Id: I9bec6a820589a562eb58f0c9688d27fabe98c064\n" }, { "commit": "15bf9804820b73765899e4b3e0d8a1fa15e0dbd3", "tree": "bcc0a0e3c0037e86041d769c1bde4b9cb9330048", "parents": [ "a168c83a1d247094e9efb1244b0f73a5f1e1ed97" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Tue Jun 12 17:49:27 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Jun 13 10:44:04 2012 -0700" }, "message": "More Quick compiler restructuring\n\nYet another round of compiler restructuring to remove references to\nMIR and BasicBlock structures in the lower levels of code generation.\nEliminating these will make it easer to share code with the\nLLVM-IR -\u003e LIR lowering pass.\n\nThis time I\u0027m focusing on the Invokes and special-cased inlined\nintrinsics. Note that this CL includes a somewhat subtle difference\nin handling MOVE_RETURNs following an INVOKE. Previously, we fused\nINVOKEs and MOVE_RETURNs for inlined intrinsics. To simplify the\nworld, we\u0027re now fusing all INVOKE/MOVE_RETURN pairs (though it shouldn\u0027t\nimpact the codegen non-inlined invokes.\n\nChanges in latest patch set: Two of the old intrinsic generators\ndid not fuse the following MOVE_RESULT, so the results were dropped\non the floor. Also, allowed match of MOVE_RESULT_OBJECT (which\npreviously had not been matched because no inline intrisic used it\nas a return value).\n\nChange-Id: I93fec0cd557398ad7b04bdcc0393f27d3644913d\n" }, { "commit": "a168c83a1d247094e9efb1244b0f73a5f1e1ed97", "tree": "d0fb5a91a00227eda6b430fd64f2a1bff5271723", "parents": [ "289be85116aaf7c48413858b5d0448868b4e61f3" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Tue Jun 12 15:34:20 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Tue Jun 12 15:34:20 2012 -0700" }, "message": "Convince tsan that the card table isn\u0027t a problem.\n\nAlso move the #include \u003csys/mman.h\u003e into \"mem_map.h\", since it\u0027s\ncurrently not possible to make any use of the latter without the\nformer. If we care about the pollution, we should offer our own\nconstants as part of our API.\n\nChange-Id: I01ec451d23c1d8afb8cb8a6660af8d9723faf5f5\n" }, { "commit": "b03f487219e446b0480aabd534fac139513502a4", "tree": "701f18e7dd88648f9006be87dea072adbfdcc945", "parents": [ "622a6988351d77da0008142f4ce1ea447d838556" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon Jun 11 15:22:11 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon Jun 11 15:28:13 2012 -0700" }, "message": "Shadow frame support for MIR-\u003eLLVM-IR conversion\n\nAdded basic shadow stack support. Minimally tested.\n[Removed some stray debugging LOGs]\n\nChange-Id: Ia27f8383548a5ca8a6fe0aa6543310575c2523ac\n" }, { "commit": "4abb1a9000b525a0636763a97528e24468f16d10", "tree": "c48ab3f5599ad81caa026bbbce380d9df7a3f149", "parents": [ "741c9fab3531a0157e1f51e3fc22466145ba15fa" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Fri Jun 08 17:02:08 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Fri Jun 08 17:02:08 2012 -0700" }, "message": "Fixes for x86 compilation with floats.\n\nCorrected compilation of neg-float and neg-double, as well as other\nfloat and double operations. There was an issue of the destination\noverwriting the second source if they were the same virtual register.\n\nChange-Id: If75e5f74b5609323c7068b68be1b72510a6ac5b1\n" }, { "commit": "2cfc639fc803bf67e3d2a961f2b637220c86d5f7", "tree": "dfb184dc35b3a534fcd54a420378f29f30011f3a", "parents": [ "a9719eb4167b544438268d46692389761652fc5d" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon May 07 14:51:40 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Thu Jun 07 16:29:03 2012 -0700" }, "message": "Foundation for Quick LLVM compiler\n\nReady for review - probably better get this cleaned up and\nchecked in even though much work remains.\n\nBasic conversion from MIR to GreenlandIR and from GreenlandIR\nback to LIR. Support sufficient to run Fibonacci test.\n\nNote some structural changes in MIR to support this work:\n o retaining incoming label for phi nodes\n o constant propagation\n o include object reference detection in type inference pass\n\nChange-Id: I8ba63c73e76d071aa40cae0f744e598b96f68699\n" }, { "commit": "408ad16bf7c460bf34ca55ff6351b79841a6fcd5", "tree": "7336813d0fc92aa3ddd9b372cb1d260dd2386b9f", "parents": [ "95b2619ca83752eb041020276e57af01052d0f94" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Jun 06 16:45:18 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Jun 06 16:45:18 2012 -0700" }, "message": "Restructure to reduce MIR references\n\nThis CL eliminates most of the MIR references in the lower-level\ncode generator. This allows a higher level of code sharing with\nthe MIR-\u003eLIR and GreenlandIR-\u003eLIR lowering passes.\n\nThe invoke, launchpads and new array support will need some more\nextensive refactoring (future CL).\n\nChange-Id: I75f249268c8ac18da1dd9180ff855d5176d6c4fe\n" }, { "commit": "60234563a621362c6ffe753fe5368afcd6682bcb", "tree": "dc17bb4872b6badd6860d9ce029568bcba3afc43", "parents": [ "9ad4f22cd9a94a3bd3439e1bc9d67fdc3e9bc67f" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Fri Jun 01 12:25:59 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Fri Jun 01 12:25:59 2012 -0700" }, "message": "Various missing hunks.\n\nThese are hunks of changes that seem to have been lost between\nics-mr1-plus-art and dalvik-dev. Maybe bad merge resolutions?\n\nChange-Id: I822c64651dc693df38efa8bc290edb959ce3398c\n" }, { "commit": "fd2ec5473d9c63b15dbc28c8a5996c83120cb8ae", "tree": "afaf2523cbb7a82548de599075d216c8eaa66624", "parents": [ "526643e38c344701d96068f351548a393c67b6be" ], "author": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Wed May 02 15:08:57 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Fri Jun 01 10:28:42 2012 -0700" }, "message": "Fix compilation issues with new gcc\n\n(cherry picked from commit efad79fa4121e20ab613e31bde44cc3120f23832)\n\nConflicts:\n\n\tsrc/compiler/codegen/mips/Mips32/Factory.cc\n\tsrc/compiler/codegen/x86/X86/Factory.cc\n\nChange-Id: I5e0e9dc48ba76092cccc70b25668978a08a5449b\n" }, { "commit": "abe64aa66cbe974508c04692f21f061c51ac6d6d", "tree": "5256fad4f489d2ec4b321908dbfa40a1d05cacb0", "parents": [ "29dbef28a9fa99d337265de1f054ba418f6bf127" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Wed May 30 17:34:45 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Wed May 30 17:34:45 2012 -0700" }, "message": "Remove a dangerous default from oatNew and fix the bug it hid.\n\nFunnily enough, no-one was using the default on purpose anyway.\n\nChange-Id: Id7b576565c1929087c05834078147dbbc8e635b3\n" }, { "commit": "21e127119e2de7246dab3f29068c4eadbd1b6f37", "tree": "f3181bc4ea8919d35ac9d785b3b300475164d7f1", "parents": [ "633703ffb2d25b0cc30404eb057d18eb2f81f07c" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Fri May 25 19:06:18 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Fri May 25 19:06:18 2012 -0700" }, "message": "Fix x86 aget-wide compilation to use loadBaseIndexedDisp.\n\nloadPair doesn\u0027t work properly when the result register is floating\npoint. Using loadBaseIndexedDisp fixes the run-tests again.\n\nChange-Id: I06cc455abe230068eea862846b91c09681139c55\n" }, { "commit": "3f9ace8d90bfc48c8d7bf35af66de8ce8238de7f", "tree": "d903b13a436fff00ec48393bf00df8b37ee875a4", "parents": [ "b2eb5c18d628dc84bdc424b5e5a491382d867e36" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Fri May 25 11:25:36 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Fri May 25 11:25:36 2012 -0700" }, "message": "Fix x86 compilation of aget-wide when src and dest regs are the same.\n\nThe base register was being overwritten by half of the result, so now a\ntemp is allocated to hold the address that is loaded from.\n\nChange-Id: I5efd45f06538f6b7d691c942c9e602b321a090ba\n" }, { "commit": "5772babbe824494ef9fe90a1b07a926d124bb7c7", "tree": "49daf01f5589f33af0c880ef9ecf1e77a59fc265", "parents": [ "6523cf6eccc0730a3ed58565ee9f1d4bc2f69ed8" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Fri May 18 11:51:26 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Fri May 18 11:58:56 2012 -0700" }, "message": "Fixed x86 compilation of filled-new-array/range.\n\nImplemented loadBaseIndexed and found a way to implemented\nfilled-new-array/range using only 4 temps instead of 5 by regenerating\nthe target pointer value after the loop.\n\nChange-Id: Ibb694600e6852ba3c4939c5878625655809c60fd\n" }, { "commit": "292188d514c9826971308a18fcc5a66261729f3b", "tree": "40417b04b3599c5bdef8fbbc7387f371d2b1601d", "parents": [ "84a5bb4556d8974d3aa1c436af36e48d622b4045" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu May 17 15:45:04 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Fri May 18 10:34:48 2012 -0700" }, "message": "More x86 fixes for floating point operations.\n\n- Fixed encoding for cvtss2sd and cvtsd2ss (they were swapped).\n\n- Implemented neg-float and neg-double in assembly.\n\n- Fixed float-to-int and double-to-int to return 0 if given NaN.\n\n- Created helpers for rem-float and rem-double.\n\nChange-Id: I456fcc1252a63dbb96c8280562e601f4efa3a5df\n" }, { "commit": "41005ddb5576b8630a1084fbb3979ffa602c0599", "tree": "af8d74573cc3a98c959566233d12bdb15251910c", "parents": [ "c3f8fa57268740f95a3c25e605bcab638b18d7b9" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Wed May 09 17:58:52 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Tue May 15 15:44:18 2012 -0700" }, "message": "Fix x86 type conversions. test-art-host-oat passes.\n\n- test-art-host-oat enabled in test builds.\n\n- Created inline versions of float-to-int and double-to-int.\n\n- Fixed calls to helper functions for long-to-float/double and\n float/double-to-long.\n\n- Removed storePair and replaced its use with storeBaseDispWide (fixes\n iput-wide and aput-wide with doubles).\n\n- Renamed helper functions to have art_ prefix.\n\n- Fixed move-exception to store the result back.\n\n- Fixed floating point comparison when the destination reg is the same as\n a source. The typing would get confused since the source is floating\n point, but the result is int, and a clobber is needed to overwrite the\n expected result type. A similar thing happens in float/double-to-int.\n\nChange-Id: I0a876072254411aa42d6acadb8723be030727219\n" }, { "commit": "5121e0b9699c8cd5e89ee323e30074b984b7b436", "tree": "1f90b4280860a5a07d72266e7e23feb577269001", "parents": [ "af0cdef6a3ea06a4ae3fb012e4f7a9c56d661508" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Tue May 08 18:23:38 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Tue May 08 18:23:38 2012 -0700" }, "message": "Fix x86 long right shifting and int-to-float/double.\n\nRight shifting a long by 32 bits or more now works correctly.\n\nAlso, uses a normal register for the src of int-to-float and\nint-to-double instead of an fp reg.\n\nChange-Id: Idaf8a398f50314eb4fc302acfbaeddfce25380b1\n" }, { "commit": "6a4a7e1d7130f5a3bf4b56a5bf5e897c4fc22713", "tree": "9a92bcda1ccb84db74a1b19236daa8f8ebc15c30", "parents": [ "644d5310d7759f6d531a2c4220b1e2cc8f3b72d3" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Mon May 07 13:28:15 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Mon May 07 13:28:15 2012 -0700" }, "message": "Fix x86 compilation of const-wide.\n\nThe psllq op was missing a prefix of 0x66, and it ended up shifting an\nmm register instead of the intended xmm register. Now IntMath works.\n\nChange-Id: Ie5244d77bced338f1d34c7079e19ff68cff7952a\n" }, { "commit": "644d5310d7759f6d531a2c4220b1e2cc8f3b72d3", "tree": "0fe8476932cb8b9aa87a7adc60ebf9bc03e2b4ff", "parents": [ "145d491d1a30b291eb3ea608507a04451237f327" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu May 03 19:04:49 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Mon May 07 10:48:00 2012 -0700" }, "message": "Fixes to x86 compilation.\n\n- div-long and rem-long were calling the wrong helper methods.\n- genCmpFP was grabbing new src and destination registers instead of\n using the ones it was passed. Also, it wasn\u0027t writing its result back.\n- gave mul-long its own assembly helper method to help it marshall its\n sources properly.\n- fixed assembly of shifts for longs.\n- updated IntMath\u0027s testFloatCompare to exit on the first error.\n\nChange-Id: Iacecf07d3c7135d865728c18551c7989e7e0276b\n" }, { "commit": "bff2465abb4b0c097623c82f18a1307ea890bff1", "tree": "aee1448eec34b9e5bf8c41fc9f83559ca5f49fd7", "parents": [ "d0379748bd05b949a8e2193b44ddf4950f9569a8" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Sun May 06 16:22:05 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Sun May 06 16:30:57 2012 -0700" }, "message": "[Compiler] Add object ref discovery\n\nPreviously, the compiler ran a type inference pass to identify floating\npoint uses for register allocation. The grand plan involves moving\nall type inference into the Art compiler driver (using the results from\nverification). As a short-term workaround, this CL adds object reference\ndiscovery to the type inference pass. This is needed for LLVM-IR generation.\n\nChange-Id: I655806264181bfd26ab9340582a02c657cd3f678\n" }, { "commit": "a114add0300b95eeaae7465493f39144e07324e8", "tree": "19b119195c00bd4688bb085eadbe142851f75e0e", "parents": [ "1ecce9487a1b3aac6b656f5704cf86a961ab0481" ], "author": { "name": "Bill Buzbee", "email": "buzbee@google.com", "time": "Thu May 03 15:00:40 2012 -0700" }, "committer": { "name": "Bill Buzbee", "email": "buzbee@google.com", "time": "Thu May 03 18:57:47 2012 -0700" }, "message": "[Compiler] use Art indentation standard\n\nFirst of several CLs to bring code closer to alignment with Art and LLVM\nstandards. Move to 2-space indenting. Sticking with 80-col line\nlength (which LLVM apparently also wants). LLVM also prefers camel\ncase names, so keeping Dalvik convention there as well (for now).\n\nChange-Id: I351ab234e640678d97747377cccdd6df0a770f4a\n" }, { "commit": "4467908da159039dccc37e3fb9dd0e35442c8d11", "tree": "067c0c50034b37bd27f3034693dda1a889e9abdf", "parents": [ "8803c0c07feb0fb5f50337cf191dae7cb034c061" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Wed Apr 25 16:22:59 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Wed Apr 25 16:22:59 2012 -0700" }, "message": "Fix immediate size for IMUL32RRI, IMUL32RMI, and IMUL32RAI.\n\nThe size of the immediate should be 4 bytes, not 2.\n\nChange-Id: I0affbab9f11584331238388823a62504da32abae\n" }, { "commit": "7b9d996e4cd7d154bb1a244d67139aff0c363cf2", "tree": "a9dabe8f910b4b8bf29c2f4285d860995e25f58d", "parents": [ "934100aea5a0f498c17e2c4a1fd0193af1557b42" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Fri Apr 20 18:48:18 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Fri Apr 20 18:57:19 2012 -0700" }, "message": "Tidy up some C-isms.\n\nChange-Id: I53b457cab9067369320457549071fc3e4c23c81b\n" }, { "commit": "174651dea03956e160a2cff0d842954823c49134", "tree": "cee1f154612afe918a0640ee8aa33644b604c039", "parents": [ "640529bdc78deaeb8d1f3e95da90f9eb5ce9806d" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Apr 19 15:27:22 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Thu Apr 19 16:01:28 2012 -0700" }, "message": "Fixed x86 division and modulus and merged their entry points.\n\nAlso enabled compilation of fill-array-data instructions in x86\n(untested), and improved x86 disassembly.\n\nChange-Id: Ia3d8d0766080d01f1c228f9283085024cadd528b\n" }, { "commit": "36ecb789775eb5bd284ce5dd35d2e31e42354f24", "tree": "5265dd2a4cf859a2e5cee4b59197dfc3f4099e33", "parents": [ "2acf36d8cfeb5ddb293904148aa70f25ef6d8845" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Tue Apr 17 16:55:45 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Tue Apr 17 16:55:45 2012 -0700" }, "message": "Fix stack overflow handling.\n\nChange-Id: I829001fdf52d33fdeac599ba9225e9f8a40b7881\n" }, { "commit": "225ae523d1b757d0579e02976446288d0a666a8d", "tree": "bc3edb9e6b9dbf639f0fa7e4b02949989d6c8ec0", "parents": [ "54a3e919ef3c8788e39a21696944d00826c25af3" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Apr 16 20:21:45 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Apr 16 20:21:45 2012 -0700" }, "message": "Implement RRI and RRI8 variants of IMUL.\n\nAlso make a few UNIMPLEMENTEDs slightly more revealing.\n\nChange-Id: I4471e7ffb84523146611bbd4c7527fb7e183e894\n" }, { "commit": "5450e0ef824b71d9cccc4b322048cabc96f141e6", "tree": "249515b6ff82563f74d6b721bc2810e783e99936", "parents": [ "776ac1fa61237db645adb4370a4aab888530caf4" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Apr 16 16:05:57 2012 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Apr 16 16:05:57 2012 -0700" }, "message": "Fix psllq encoding bug.\n\nChange-Id: I786ba9d610ec68c01064c3b3ce731f42b7864e2b\n" }, { "commit": "a0e180632411f7fe0edf454e571c42209ee7b540", "tree": "97dc85e76c5449ec1a901226c44e0f68fec89870", "parents": [ "e5eb1914de86129d78e965fb9f2e1bfb2aa68640" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Fri Apr 13 15:59:59 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Sat Apr 14 11:44:21 2012 -0700" }, "message": "Add a SafeMap equivalent to std::map but without the error-prone operator[].\n\nChange-Id: Iae5ba2091c55a34dbd1005cf3d25fce2a8d5c1f9\n" }, { "commit": "f3aac973bb944885a1a4779ba04a97faa88b7ed0", "tree": "fea6d65da9770addbff35ae610ee6c1d0c397644", "parents": [ "933abf8ce64e522b1c45b191b796bf2208a760d9" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Apr 11 16:33:36 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Apr 11 16:33:36 2012 -0700" }, "message": "Special case division by small constants\n\nDo the standard reciprocal multiply trick for small division\nby small constants.\n\nChange-Id: Iad1060ccdc6ffeb7b47d45c29ba741683ad01ab9\n" }, { "commit": "cd4935fcfe1ebc60cc727fe5e537cf201dcb0ede", "tree": "d0c9973dfdb9bdb6a1855c22b0800e6a0feb84e5", "parents": [ "b92bcabcbb28f69fe99e1c2f2e5559ab2c47aa60" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Tue Apr 10 16:15:59 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Tue Apr 10 16:15:59 2012 -0700" }, "message": "Use a shorter x86 CMP encoding for suspend count tests.\n\nChange-Id: Ic765c0517cccb22030efa42271ede650f64284e4\n" }, { "commit": "d36c52ea6bc22883ef381f6da1ac05ef7524f63a", "tree": "cc184142b857a666d4aca5d049852f123fa80dae", "parents": [ "82914b6164fd0109531391975389e4f0ff6832c8" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Apr 09 16:29:25 2012 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Apr 09 19:45:49 2012 -0700" }, "message": "Check for null array assignments inline. Tidy asm macros.\n\nTidy/fix array object stores to not pass incremented register to card\nmark. Fix x86 register allocator clobbers. Clean runtime support\nassembler macros to be more macrotized. Extra X86 shift assert.\nAdd X86 thread suspension down call.\n\nChange-Id: Ida765dcba32404519fe7eb478f5628d46caf41f7\n" }, { "commit": "141d62275f207bf68c55f583fb206fe586d857cf", "tree": "6263e12c9194e966d452658f54612fc7b3b7e410", "parents": [ "f3388e6ef460384a87c85bff72c961ebcd11ce0a" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Apr 05 12:23:06 2012 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Apr 05 18:11:20 2012 -0700" }, "message": "More X86 fixes.\n\nFix bugs in a few long entrypoints and with object validation being\nenabled.\n\nChange-Id: I18884fbbe6829b584b9fc92e338549577f925f14\n" }, { "commit": "55bd45f4ea40b9a0af323f813d07f23d7a8ed397", "tree": "f315fc79924662e612c6825b6d9b20ba2178853e", "parents": [ "5e284224e5525ee0a8494a73d84c8ef86e022a0a" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Apr 04 17:31:20 2012 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Apr 04 18:23:36 2012 -0700" }, "message": "More X86 fixes.\n\nSupport for long divides and sparse switches.\n\nChange-Id: I07cdf6a9a2e4c6156cc70a429bf58f22e0e45ef1\n" }, { "commit": "fc700ed5af8d7c9ac044698b078a12a92a360ba7", "tree": "67aa8f384d7c22f0dae9425527d0a27de3ef1487", "parents": [ "7caad77632ae121c9f64c488e3f8f710e2c4813d" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Apr 04 11:21:26 2012 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Apr 04 11:21:26 2012 -0700" }, "message": "Fix x86 long math.\n\nChange-Id: I5ffe82dc4476f4b7e6f7ee16329031f26994b517\n" }, { "commit": "7caad77632ae121c9f64c488e3f8f710e2c4813d", "tree": "6b12ff6e0c27529f5434c5655b3306a1f79bd379", "parents": [ "4855cd516d97c9728fa58312acdf6c4b8b81397a" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Mar 30 01:07:54 2012 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Apr 04 09:56:48 2012 -0700" }, "message": "Implement various missing parts of the X86 compiler\n\nChange-Id: I76f08580600befe268328f8cf7102c6146460c5e\n" }, { "commit": "e52e49b32f5cf862a414da63e5dbd2eb04ad758e", "tree": "582296bc89fcb3ca475260abba8e9b3d6fc2f39d", "parents": [ "2d62a0e4ae6b528648c585aa804569aaefc4c517" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Apr 02 16:05:44 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Mon Apr 02 16:05:44 2012 -0700" }, "message": "Fix the mutex diagnostics, and other targets of opportunity.\n\nThree changes for the price of one:\n\n1. Fix the mutex diagnostics so they work right during startup and shutdown.\n\n2. Fix a memory leak in common_test.\n\n3. Fix memory corruption in the compiler; we were calling memset(3) on a struct\nwith non-POD members.\n\nThanks, as usual, to valgrind(1) for the latter two (and several bugs in\nearlier attempts at the former).\n\nChange-Id: I15e1ffb01e73e4c56a5bbdcaa7233a4b5221e08a\n" }, { "commit": "cf7d3a3b813b8bf08e127abeab67a425c9752f63", "tree": "d6faf1ad1ae70d09455593135663a967534c0722", "parents": [ "16796a1a0a4f7898ec1daaac8fc3a9e10d8f3007", "0f3c55331439970e01af67f80ac117c473bc04cf" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Fri Mar 30 15:11:51 2012 -0700" }, "committer": { "name": "Android (Google) Code Review", "email": "android-gerrit@google.com", "time": "Fri Mar 30 15:11:51 2012 -0700" }, "message": "Merge \"Kill constants.h and fix some copyright headers.\" into ics-mr1-plus-art" }, { "commit": "0f3c55331439970e01af67f80ac117c473bc04cf", "tree": "cfa28ad2a58af1ffddb0a2ce90443ad4606743c3", "parents": [ "273cf36d199cf73de3cf61a559ad27c9d23f9825" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Fri Mar 30 14:51:51 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Fri Mar 30 14:51:51 2012 -0700" }, "message": "Kill constants.h and fix some copyright headers.\n\nChange-Id: I51c04d731d6de035328781d8ac134ad6fcf49897\n" }, { "commit": "fead293106bf15bd97c126b81479cb06668de9c8", "tree": "bddc8ea3a26eafe7e5421eaafeb56904ee150f69", "parents": [ "ba7a3ecc0c7342a19951f076474c41d43168f68e" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri Mar 30 14:02:01 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri Mar 30 14:02:01 2012 -0700" }, "message": "Minor suspend check tweak\n\nRearrange the suspend check branch for unconditional backwards\nbranches. Now, the conditional branch on rSUSPEND will go directly\nto the target in the common case, and fallthrough to an\nunconditional branch to the suspend launchpad in the uncommon case.\n\nChange-Id: Ie1a2b2fe720efde6e131a8d5274b7487fb644881\n" }, { "commit": "a2e39d9c54a1e35e3f67ee3543bf7039f112d39c", "tree": "f3c6b31484ca6c119e371935127a8ec3b59c4015", "parents": [ "e103141a78d705f2009b7f98c9a9df201dda63a7" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri Mar 30 09:11:45 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri Mar 30 09:34:31 2012 -0700" }, "message": "Enable the rest of branch fusing\n\nI mistakenly left most of the branch fusing cases disabled in\nthe previous CL. This CL turns them all on, along with a fix\nfor the bug I was chasing while disabling them in the first\nplace.\n\nChange-Id: Ia60f7fe5394a5da08ed75bbff39b47ae9497a61c\n" }, { "commit": "84fd693103dddd50b6a18522bfb5eaab0e51b6ec", "tree": "47e3e167fe7b42561b1eafeda2c53329fbad4f58", "parents": [ "7cea03edf5f9615cb65af864183f0e8b4d13a79e" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Thu Mar 29 16:44:16 2012 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Thu Mar 29 16:44:16 2012 -0700" }, "message": "Branch fusing\n\nA belated birthday gift for irogers. Fuse cmp-long/if-XXz,\ncmp[lg]-[float|double]/if-XXz.\n\nChange-Id: I8fa87f620fcf4e6bcf291bbc7a0ea6c8f5535467\n" } ], "next": "57b86d47b66322693a070185fadfb43cb9c12eab" }