)]}' { "log": [ { "commit": "5d6e27d136756216c945d3fc5eb2ecc1537bfe7a", "tree": "6c558348ad01c748894902ac9b0adc6cc032384f", "parents": [ "bae13af2fc2fa89985d0466cedf155cb96767910" ], "author": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Mon Jul 18 13:38:44 2016 -0700" }, "committer": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Tue Jul 19 14:18:30 2016 -0700" }, "message": "Refactor SSA deconstruction into its own class\n\nTest: m test-art-host\n\nChange-Id: Ie82c2802f76f27512ef922ba583caeccf5675063\n" }, { "commit": "0c67ddaff8fac3e4b3bd8e91cedd5f3a0498f3cd", "tree": "9f37ec492a4831bbdec7503a24e929dbcddb985d", "parents": [ "64a73d790d983c3dc3b42b044eca687b54442977", "e9288851eb6b62ece28f510d978d3793723b9a51" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Mon Jul 18 19:35:11 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jul 18 19:35:11 2016 +0000" }, "message": "Merge \"Rename current register allocator implementation\"" }, { "commit": "4c489f48ef432126b8e7a84b61c1c13a7514c085", "tree": "d3f22711eac67a0a00cecfdbd0f1a522d1c7e7e2", "parents": [ "11502fb83b1cac020d9ac8e5c36cf229b82a4a1e", "ab922503cee2b105dfd9dbdde9fb60c26a35d2df" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jul 18 15:40:34 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jul 18 15:40:34 2016 +0000" }, "message": "Merge \"MIPS64: Highest/Lowest Bit Intrinsic Support\"" }, { "commit": "71280fcc8c7edc244b8236cd67b32b87365b069f", "tree": "7f1576978ca0b6d660eced5a67f32d713c4700bf", "parents": [ "5668e58daf0f54d6cc8a6919033acc3506fc86ee" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jul 18 16:03:05 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jul 18 16:03:05 2016 +0100" }, "message": "Fix the build with respect to new VIXL.\n\nTest: Build ART for ARM64.\nChange-Id: I2a9ebf145c61db9f8ceec6616963bac3ad5a7eb9\n" }, { "commit": "5668e58daf0f54d6cc8a6919033acc3506fc86ee", "tree": "de19460ff3c2f940ce5b0f7036a4bf756b59ed4e", "parents": [ "24670a7aac24c7a9b661220ab76b36c75f1494c5", "97c72b76cf776228196c6abd33973ef751de61ad" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jul 18 14:28:05 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jul 18 14:28:06 2016 +0000" }, "message": "Merge \"Fixes to build against new VIXL interface.\"" }, { "commit": "24670a7aac24c7a9b661220ab76b36c75f1494c5", "tree": "0a6388616c4c8c6527b5b45c69a31c51459714b0", "parents": [ "471c2270aa8606ba62d06b0d2eef8c8fd3ec5f9f", "dac9b19b822e6cc6f1d7f40e27780515d1fddf22" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jul 18 12:16:46 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jul 18 12:16:46 2016 +0000" }, "message": "Merge \"Add a new control flow simplifier.\"" }, { "commit": "68bd9b9b165ffca1a49b80bb437ce9f87b738264", "tree": "671bb60203157fdb34dd2e9cdf851cb79eb02a0e", "parents": [ "173f435e56acfd0501fc460747572a4796dcffe0" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Jul 15 17:41:13 2016 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Mon Jul 18 11:25:19 2016 +0100" }, "message": "ARM64: Improve code generated to spill/restore for slow paths.\n\nAligning the accesses allows generating better code.\n\nBefore:\n\n add x16, sp, #0x44 (68)\n stp x0, x1, [x16, #-16]\n\nAfter:\n\n stp x0, x1, [sp, #56]\n\nChange-Id: I3e20ad3fa59d00aee4b4d14ea9d59c7cd546509e\n" }, { "commit": "dac9b19b822e6cc6f1d7f40e27780515d1fddf22", "tree": "de163a82ef5f13394c4b467897e558571ed284b9", "parents": [ "173f435e56acfd0501fc460747572a4796dcffe0" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jul 15 10:46:17 2016 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jul 18 11:22:51 2016 +0100" }, "message": "Add a new control flow simplifier.\n\nRun it in the dead code elimination phase, as it relates to\ncreating dead branches.\n\nFrom 0.04 to 0.07% less code size framework/gms/docs/fb (70K saved on fb)\n3%-5% runtime performance improvements on Richards/DeltaBlue/Ritz.\nCompile-time is mixed, so in the noise (from 2% slower to 1% faster).\n\ntest:611-checker-simplify-if\n\nChange-Id: Ife8b7882d57b5481f5ca9dc163beba655d7e78bf\n" }, { "commit": "e9288851eb6b62ece28f510d978d3793723b9a51", "tree": "3d422c4dfa7437b4891504ee452bf50b4852a9c5", "parents": [ "161c866ca742049f5c916696e1503c697be30e87" ], "author": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Thu Jul 14 14:08:16 2016 -0700" }, "committer": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Fri Jul 15 18:09:46 2016 -0700" }, "message": "Rename current register allocator implementation\n\nThis will allow a cleaner commit in an upcoming\nrefactoring of register allocation.\n\nTest: m test-art-host\n\nChange-Id: If420c97b088b3c934411ff83373e024003120746\n" }, { "commit": "97c72b76cf776228196c6abd33973ef751de61ad", "tree": "7a78a2b19b0847281f8cf69af735b30b15732fa8", "parents": [ "1fd347303275a424d114c9833f954e8e27812554" ], "author": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Fri Jun 24 16:19:36 2016 +0100" }, "committer": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Fri Jul 15 09:48:07 2016 +0100" }, "message": "Fixes to build against new VIXL interface.\n\n- Fix namespace usage and use of deprecated functions.\n- Link all dependants to new libvixl-arm64 target for now.\n\nChange-Id: Iee6f299784fd663fc2a759f3ee816fdbc511e509\n" }, { "commit": "05d9a647a66d67b9ef444ba1627f019735cb72d8", "tree": "5b3d9e17d6ec22bc8637512e7881aa6577dc4c12", "parents": [ "f18f3cb337161b2cb651cd38642d6f9c06266728", "dc00f184b57086263587f1a1c1991336c07a8e4a" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Jul 14 21:09:55 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 14 21:09:56 2016 +0000" }, "message": "Merge \"Revert \"Revert \"Dump more dex file data in oatdump\"\"\"" }, { "commit": "dc00f184b57086263587f1a1c1991336c07a8e4a", "tree": "3e4ad30844658b9ccc48f80def1b8de66e2e2622", "parents": [ "2c30a373428b8d19bf97866d5d323c4ca2fbca72" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Thu Jul 14 10:10:44 2016 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Thu Jul 14 13:09:51 2016 -0700" }, "message": "Revert \"Revert \"Dump more dex file data in oatdump\"\"\n\nDelete runtime to fix leak before callin exit.\n\nBug: 29462018\n\nThis reverts commit 9c05578dd2306231437bd290c0f70abc2bb3b6d8.\n\nChange-Id: Ica23ba0f2d07496d0e4a3288329945f612ac3b20\n" }, { "commit": "f18f3cb337161b2cb651cd38642d6f9c06266728", "tree": "0e80bb81a9c36a32f5c3cf83b70e2e64ae876689", "parents": [ "2fce5cf079924c20da8c35e2fd0271715091d97b", "f1073c81a88bd545a45639865c38c43c83f89419" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Jul 14 19:44:38 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 14 19:44:39 2016 +0000" }, "message": "Merge \"Integer.bitCount and Long.bitCount intrinsics for ARM\"" }, { "commit": "f1073c81a88bd545a45639865c38c43c83f89419", "tree": "e25adf623c8a56552400ae6ad3f52c85c509c3a4", "parents": [ "2e7acaffda05db1df6e0631468f10726e898a20a" ], "author": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Tue Jul 05 15:28:19 2016 +0100" }, "committer": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Thu Jul 14 16:32:50 2016 +0100" }, "message": "Integer.bitCount and Long.bitCount intrinsics for ARM\n\nChange-Id: I4ed3e779415be026c7d090b61a3e356b37c418e5\n" }, { "commit": "2c30a373428b8d19bf97866d5d323c4ca2fbca72", "tree": "8927430b0ae7185b0583615e8dbd7481ac13c6c7", "parents": [ "7598736db0647eb963e77fafc22af6c0a5747d20", "02b75806a80f8b75c3d6ba2ff97c995117630f36" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jul 14 09:32:34 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 14 09:32:34 2016 +0000" }, "message": "Merge \"Introduce more compact ReadBarrierMark slow-paths.\"" }, { "commit": "7598736db0647eb963e77fafc22af6c0a5747d20", "tree": "19b18b2bf954b537e4dade3e7e11e28229ccefc9", "parents": [ "09d77fac678d6c4d743218ffb6b77dea002b073e", "9c05578dd2306231437bd290c0f70abc2bb3b6d8" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jul 14 09:24:45 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 14 09:24:45 2016 +0000" }, "message": "Merge \"Revert \"Dump more dex file data in oatdump\"\"" }, { "commit": "9c05578dd2306231437bd290c0f70abc2bb3b6d8", "tree": "0f9983cabba29de867051ea990221603f0ff765a", "parents": [ "8e2c56252aa9527bd9a82bdd147fdc46cf5deb9c" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jul 14 09:24:30 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jul 14 09:24:30 2016 +0000" }, "message": "Revert \"Dump more dex file data in oatdump\"\n\nBreaks valgrind.\n\nBug: 29462018\n\nThis reverts commit 8e2c56252aa9527bd9a82bdd147fdc46cf5deb9c.\n\nChange-Id: If58cedcee75dd0eda8571e90d63e080a4709d773\n" }, { "commit": "09d77fac678d6c4d743218ffb6b77dea002b073e", "tree": "e9c527aa279e3c1eb400e0d2c539521d899875eb", "parents": [ "d2c44723e6fac5dd4aafffe61cbed3214340883c", "ff484b95b25a5181a6a8a191cbd11da501c97651" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jul 14 07:56:16 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jul 14 07:56:17 2016 +0000" }, "message": "Merge \"Fix a bug in ClassTableGet code generation for IMTs.\"" }, { "commit": "8e2c56252aa9527bd9a82bdd147fdc46cf5deb9c", "tree": "4b300a176d73caae6c63768e951976a4fde993ef", "parents": [ "633c22de95fe6f80c0dd3176e15de4de3ee4bc79" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Tue Jun 21 15:14:20 2016 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed Jul 13 13:20:55 2016 -0700" }, "message": "Dump more dex file data in oatdump\n\nDump some statistics for each dex file along side with strings loaded\nfrom code and dex code bytes.\n\nSample output:\nCumulative dex file data\nNum string ids: 202809\nNum method ids: 320464\nNum field ids: 162822\nNum type ids: 68151\nNum class defs: 48061\nUnique strings loaded from dex code: 51049\nTotal strings loaded from dex code: 106651\nNumber of unique dex code items: 247929\nTotal number of dex code bytes: 11090574\n\nAdded content testing to oat dump test. No significant slowdown.\n\nTEST: test-art-host\nBug: 29462018\n\nChange-Id: I60effd3087d8c427eda4ee26431d5d77165b3939\n" }, { "commit": "633c22de95fe6f80c0dd3176e15de4de3ee4bc79", "tree": "0f9983cabba29de867051ea990221603f0ff765a", "parents": [ "bcdc888a393d226a970f4611b649cd9a3de815b9", "f64a6ab5f69446303faadbf6a0ede00af435e25c" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Wed Jul 13 18:07:04 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jul 13 18:07:04 2016 +0000" }, "message": "Merge \"Improve search for available spill slots in RA\"" }, { "commit": "a70835569128786877caa64c4e1978e734ff0768", "tree": "e7ca7ee9517983ede563a338c0372f3aad9476b6", "parents": [ "c8cbda659671b111e309fe123cb2d4887e4edd10", "ee8d971b14edfc1e0af9436fd223277df966e4c2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jul 13 16:37:34 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jul 13 16:37:34 2016 +0000" }, "message": "Merge \"X86: Use memory to do array range checks\"" }, { "commit": "ff484b95b25a5181a6a8a191cbd11da501c97651", "tree": "a14875e1a28afd1c5f7bd6a0a80414674253e593", "parents": [ "1fd347303275a424d114c9833f954e8e27812554" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 13 14:13:48 2016 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 13 16:13:03 2016 +0100" }, "message": "Fix a bug in ClassTableGet code generation for IMTs.\n\nIntroduced by:\n https://android-review.googlesource.com/#/c/244980/\n\ntest:566-polymorphic-inling for fixing x86 crash. Also\nfixes a performance regression.\nbug:29188168\n\nChange-Id: Id90cb819c88e7ba3db1cb3c50c517a112ab7d784\n" }, { "commit": "ee8d971b14edfc1e0af9436fd223277df966e4c2", "tree": "2dc16ca40980cc716aba24d793eaa8731846a180", "parents": [ "dedde3f10d7801ad862d1ca1de89135decff6a60" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Jul 12 11:13:15 2016 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Jul 13 10:40:45 2016 -0400" }, "message": "X86: Use memory to do array range checks\n\nCurrently, an HBoundsCheck is fed by an HArrayLength, causing a load of\nthe array length, followed by a register compare.\n\nAvoid the load when we can by comparing directly with the array length\nin memory. Implement this by marking the HArrayLength as \u0027emitted at\nuse site\u0027, and then generating the code in the HBoundsCheck.\n\nOnly do this replacement when we are the only user of the ArrayLength\nand it isn\u0027t visible to the environment.\n\nHandle the special case where the array is \u0027null\u0027 and where an implicit\nnull check can\u0027t be eliminated.\n\nThis code moves the load of the length to the slow code for the failed\ncheck, which is what we want.\n\nTest: 609-checker-x86-bounds-check\n\nChange-Id: I9cdb183301e048234bb0ffeda940eedcf4a655bd\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "02b75806a80f8b75c3d6ba2ff97c995117630f36", "tree": "ecdb1852c3e33f120110091cc2d07a9737fbd3b5", "parents": [ "5f485719b166ceb8e591329d40e76c5e50988022" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jul 13 11:54:35 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jul 13 11:54:35 2016 +0100" }, "message": "Introduce more compact ReadBarrierMark slow-paths.\n\nReplace entry point ReadBarrierMark with 32\nReadBarrierMarkRegX entry points, using register\nnumber X as input and output (instead of the standard\nruntime calling convention) to save two moves in Baker\u0027s\nread barrier mark slow-path code.\n\nTest: ART host and target (ARM, ARM64) tests.\nBug: 29506760\nBug: 12687968\nChange-Id: I73cfb82831cf040b8b018e984163c865cc44ed87\n" }, { "commit": "f64a6ab5f69446303faadbf6a0ede00af435e25c", "tree": "a445bbe8fa31ad699b91eee3386e0ac2864f561a", "parents": [ "dedde3f10d7801ad862d1ca1de89135decff6a60" ], "author": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Mon Jul 11 14:45:01 2016 -0700" }, "committer": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Tue Jul 12 10:20:55 2016 -0700" }, "message": "Improve search for available spill slots in RA\n\nPreviously we always searched for two adjacent spill slots, even if\nwe only needed one. This small change fixes that.\n\nTest: m test-art-host\n\nChange-Id: I021d355e6602ffee687c8537a959232b1504dcf1\n" }, { "commit": "058d934b429513380218b029fc2ee562c7f47696", "tree": "0966acbb887bdb072d793f8bbbd6837367b9f912", "parents": [ "2f378bf675e0fa99cf20ee4c7c5d6b2c0325cf51", "877a0335d3d86ee7e63e25af3f0ed82c89468d51" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 12 15:02:31 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jul 12 15:02:31 2016 +0000" }, "message": "Merge \"ARM64: Shorter fast-path for read barrier field load.\"" }, { "commit": "2f378bf675e0fa99cf20ee4c7c5d6b2c0325cf51", "tree": "85ab6711ea27a977f54bb58fdd3764e38225d710", "parents": [ "5f4f6cfe4603133b4b746d9e4e061575bbf880e0", "d3278bd288aaecd525f931a54f5f2a392f627fd3" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 12 14:14:26 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jul 12 14:14:26 2016 +0000" }, "message": "Merge \"Two more patterns for instruction simplifier\"" }, { "commit": "877a0335d3d86ee7e63e25af3f0ed82c89468d51", "tree": "d14daa76937d926481b6a3a5ac987a24cb2f3800", "parents": [ "dedde3f10d7801ad862d1ca1de89135decff6a60" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jul 11 19:30:56 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 12 14:50:34 2016 +0100" }, "message": "ARM64: Shorter fast-path for read barrier field load.\n\nReduces the aosp_flounder-userdebug 64-bit boot.oat by\n~4.2MiB, i.e. ~3.5%, in the ART_USE_READ_BARRIER\u003dtrue\nconfiguration.\n\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue on Nexus 9.\nBug: 29966877\nBug: 12687968\nChange-Id: Ic9853ec82747a1702e4091fcf9cbf06674fcd5f6\n" }, { "commit": "5f4f6cfe4603133b4b746d9e4e061575bbf880e0", "tree": "f991ca0a84e65ef27dae8d2ea3f4decc5961771d", "parents": [ "d8f5f56f2dd90e2bcb6d41cb48403320b9eb04b9", "194bcfea4a29db2c529de333c6a00b32608dd4e5" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 12 12:03:02 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jul 12 12:03:03 2016 +0000" }, "message": "Merge \"ARM: Shorter fast-path for read barrier field load.\"" }, { "commit": "d3278bd288aaecd525f931a54f5f2a392f627fd3", "tree": "20a795e7de9ace6fa695e123fcf7beaf4e9ccbb9", "parents": [ "d8f5f56f2dd90e2bcb6d41cb48403320b9eb04b9" ], "author": { "name": "Maxim Kazantsev", "email": "maxim.kazantsev@intel.com", "time": "Tue Jul 12 15:55:33 2016 +0600" }, "committer": { "name": "Maxim Kazantsev", "email": "maxim.kazantsev@intel.com", "time": "Tue Jul 12 11:14:02 2016 +0000" }, "message": "Two more patterns for instruction simplifier\n\nThis patch allows the instruction simplifier to cover\ntwo more cases:\n\n x \u003d a + b and x \u003d a - b\n y \u003d x - b y \u003d x + b\n\nIn both cases y can be replaced with a, if the types\nof arguments are integral.\n\nChange-Id: I4735737f471e31057f1df76ddace5d4d1c79cde6\nTest: New tests in 458-checker-instruction-simplification.\nSigned-off-by: Max Kazantsev \u003cmaxim.kazantsev@intel.com\u003e\n" }, { "commit": "d8f5f56f2dd90e2bcb6d41cb48403320b9eb04b9", "tree": "6c0c43f98f6c50c799c45449a4a45fa121ab1ba3", "parents": [ "6caea66f9d73b9fe4693090e3b3ceb1cf0b248d1", "54ff482710910929900f8348a19c5b875e519237" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Jul 12 11:07:50 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jul 12 11:07:50 2016 +0000" }, "message": "Merge \"Rename kCall to kCallOnMainOnly\"" }, { "commit": "194bcfea4a29db2c529de333c6a00b32608dd4e5", "tree": "83c8c87448730de7d8a0a4ac51414806ae0b9090", "parents": [ "dedde3f10d7801ad862d1ca1de89135decff6a60" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jul 11 15:52:00 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jul 12 12:04:19 2016 +0100" }, "message": "ARM: Shorter fast-path for read barrier field load.\n\nReduces the aosp_hammerhead-userdebug boot.oat by 2.2MiB,\ni.e. ~2.2%, in the ART_USE_READ_BARRIER\u003dtrue configuration.\n\nTest: Tested with ART_USE_READ_BARRIER\u003dtrue on Nexus 5.\nBug: 29966877\nBug: 12687968\nChange-Id: I4454150003e12a1aa7f0cf451627dc1ee9a495ae\n" }, { "commit": "54ff482710910929900f8348a19c5b875e519237", "tree": "82667795ef43a33a87a585f9bc841c88ff3460f1", "parents": [ "2e7acaffda05db1df6e0631468f10726e898a20a" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Thu Jul 07 18:03:19 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Jul 11 17:59:29 2016 +0000" }, "message": "Rename kCall to kCallOnMainOnly\n\nThis patch renames kCall to kCallOnMainOnly in preparation for\nthe next patch in this series which will be adding kCallOnMainAndSlowPath.\n\nNote: With this patch there will be places where we use kCallOnMainOnly\neven though we call on the slow path too. The next patch in this series\nwill fix that.\n\nTest: ART host tests.\nChange-Id: Iabfdb0901990d163be5d780f3bdd2fab6fa17b32\n" }, { "commit": "83e4903f9f966b52d758b52ac1d522e13fd43e60", "tree": "966df75b9d69f43bb18ece89b1ef16db6c546e45", "parents": [ "dadc075149eb322bf28ba35a75a70157147c1c30", "a62cb9bb6cb2278cb41ab0664191623e178c6a4f" ], "author": { "name": "Jeff Hao", "email": "jeffhao@google.com", "time": "Fri Jul 08 20:06:58 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jul 08 20:06:58 2016 +0000" }, "message": "Merge \"Revert \"Revert \"Optimize IMT\"\"\"" }, { "commit": "ab922503cee2b105dfd9dbdde9fb60c26a35d2df", "tree": "238d5d01ee93aac328f13797096ec8596a140718", "parents": [ "dadc075149eb322bf28ba35a75a70157147c1c30" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Fri Apr 15 10:00:56 2016 -0700" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Fri Jul 08 10:56:06 2016 -0700" }, "message": "MIPS64: Highest/Lowest Bit Intrinsic Support\n\n- int java.lang.Integer.highestOneBit(int)\n- long java.lang.Long.highestOneBit(long)\n- int java.lang.Integer.lowestOneBit(int)\n- long java.lang.Long.lowestOneBit(long)\n\nChange-Id: I0db7858542130d759ee7d17ecb1eadb7ec3dc04c\n" }, { "commit": "b136c87854820aa4b5d47d725793770342b45ca1", "tree": "1b2115a79e47a059a7fb345f16736124599aeb3f", "parents": [ "a548c081fe1967e89b6973aa0715a83419f93ef7", "7adaab070bbe9783130e78eea163c459303c980b" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Jul 08 17:26:30 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jul 08 17:26:30 2016 +0000" }, "message": "Merge \"MIPS64: java.lang.Math.round\"" }, { "commit": "a548c081fe1967e89b6973aa0715a83419f93ef7", "tree": "a6df98cb61f3badf4e7a5d45e3f533f9aef2e3f6", "parents": [ "4a7a7d267987928a20af65b07563ad719cb2bb61", "d1e153c4101d52a3f916a15b57b7ef4394106e11" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jul 08 16:28:23 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jul 08 16:28:23 2016 +0000" }, "message": "Merge \"Math Round Intrinsic Implementations For Java8.\"" }, { "commit": "4a7a7d267987928a20af65b07563ad719cb2bb61", "tree": "290e087c967a5a0dcf0d40d94519e0743fca81b3", "parents": [ "5f485719b166ceb8e591329d40e76c5e50988022", "8c5d310b8ac3bdce41cdc680fcad791c321eaec2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jul 08 15:43:25 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jul 08 15:43:25 2016 +0000" }, "message": "Merge \"ARM: Remove unnecessary VMOV from float/double-to-int.\"" }, { "commit": "d1e153c4101d52a3f916a15b57b7ef4394106e11", "tree": "ae18fde2ce2d59b29ed0d06eaed4c07e53803dee", "parents": [ "2e7acaffda05db1df6e0631468f10726e898a20a" ], "author": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Fri May 27 18:56:13 2016 +0100" }, "committer": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Fri Jul 08 14:51:05 2016 +0100" }, "message": "Math Round Intrinsic Implementations For Java8.\n\nAccording to Java 8 API definition Math.round() performs:\nReturn the closest long or int to the argument,\nwith ties rounding to positive infinity.\n\nBefore this patch, the Math.round intrinsics were disabled,\nbecause they followed the old definition of Math.round: floor(input+0.5).\n\nThis patch reimplement Math.round intrinsic to follow the new definition.\n\nChange-Id: I453c01a9857a3d461b230e4d4e98c2d7bdf7a3c7\n" }, { "commit": "fea1abd660cc89b31d121c8700fae8d804178391", "tree": "e7139b23b923d89c239619746bd4684e2f3e363d", "parents": [ "9fa78522de3eef6277631284598781479f289b0c" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 06 12:09:12 2016 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jul 07 16:23:46 2016 +0100" }, "message": "Implement System.arraycopy intrinsic on x86.\n\nAlso remove wrong comments when doing the raw copying.\n\ntest:run-test, 537-checker-arraycopy, 610-arraycopy\n\nChange-Id: I2495bc03cde8ccad03c93f7722dd29bf85138525\n" }, { "commit": "8c5d310b8ac3bdce41cdc680fcad791c321eaec2", "tree": "fb3e2055fb8afd580ab740e29d73b1eb3be6f8d8", "parents": [ "74c0d1bb67f9c6ee8306f0318ab7251d56dc99d6" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 07 12:07:44 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 07 14:01:26 2016 +0100" }, "message": "ARM: Remove unnecessary VMOV from float/double-to-int.\n\nTest: Run standard ART test suite on Nexus 5.\nChange-Id: I780fd0cca68f89401d2a114e1022bed498d02979\n" }, { "commit": "9f65db89353c46f6b189656f7f55a99054e5cfce", "tree": "8644957a017c9954372ef73d7bcc457789d294eb", "parents": [ "f731706af1ce91e9d77f85c36b4dcacce17b7f9b" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jul 07 12:07:42 2016 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jul 07 13:35:51 2016 +0100" }, "message": "Fix System.arraycopy when doing same array copying.\n\nAt compile time, if constant source \u003c constant destination, and we don\u0027t\nknow if the arrays are the same, then we must emit code that checks\nif the two arrays are the same. If so, we jump to the slow path.\n\ntest:610-arraycopy\n\nChange-Id: Ida67993d472b0ba4056d9c21c68f6e5239421f7d\n" }, { "commit": "a62cb9bb6cb2278cb41ab0664191623e178c6a4f", "tree": "62263dac644e2d80a34a04f2649e4741a1bed6f4", "parents": [ "bb8d501c9bb882a8927c6ceda07bf9577e06c3e1" ], "author": { "name": "Artem Udovichenko", "email": "artem.u@samsung.com", "time": "Thu Jun 30 09:18:25 2016 +0000" }, "committer": { "name": "Artem Udovichenko", "email": "artem.u@samsung.com", "time": "Thu Jul 07 10:01:04 2016 +0000" }, "message": "Revert \"Revert \"Optimize IMT\"\"\n\nThis reverts commit 88f288e3564d79d87c0cd8bb831ec5a791ba4861.\n\nChange-Id: I49605d53692cbec1e2622e23ff2893fc51ed4115\n" }, { "commit": "5bf7bacc0993a2efd9b0765813928ff72ea4bb9f", "tree": "c8d6df8d62ea03664199420d2866cb66c3fdf945", "parents": [ "a5f0a1ab3f632f1e9c0bc048604aa0c0e98a4a93" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 06 14:18:23 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 06 15:50:18 2016 +0100" }, "message": "Revert \"Revert \"Inline and optimize interface calls.\"\"\n\nThis reverts commit 19dc255bf94a4229de8627a2079ee6f0e9005e2d.\n\nChange-Id: Ifc3a92280878d4db1b460d486137497b3456beae\n" }, { "commit": "19dc255bf94a4229de8627a2079ee6f0e9005e2d", "tree": "38ce4ec6ab0ae5ed99f16c695441135fd36d26dd", "parents": [ "d9faceaa8da92f4a56c2907de949081bd42faf79" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 06 14:01:50 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 06 14:01:50 2016 +0000" }, "message": "Revert \"Inline and optimize interface calls.\"\n\nWent ahead too quickly.\n\nThis reverts commit d9faceaa8da92f4a56c2907de949081bd42faf79.\n\nChange-Id: I1610deaf89b38037cf2786d135a59c48b10ced0c\n" }, { "commit": "d9faceaa8da92f4a56c2907de949081bd42faf79", "tree": "2efc00cfe8d5211e420174db81e732f8e92cbb33", "parents": [ "74c0d1bb67f9c6ee8306f0318ab7251d56dc99d6" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 06 10:19:23 2016 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 06 13:30:13 2016 +0100" }, "message": "Inline and optimize interface calls.\n\n- Support for inlining methods with invoke-interface (the\n previous performance limitation is now fixed with the new\n ImtConflictTable).\n- Turn non inlineable invoke-interface into invoke-virtual to\n avoid any potential execution of the conflict trampoline.\n\ntest:609-checker-inline-interface\n\nChange-Id: Ibe33bc945deaada8fb78541e6e0bf034ebb52420\n" }, { "commit": "f7ba875851ba537237ca797f7dcdbca064e87c34", "tree": "a5942f4a3f904f8d2f888e6e65c4c58a59885ad8", "parents": [ "5aef803591b8677c3eef990ecc29d0a49af27a7d", "e14dc86d4e84d52426510d0fafbac3d7e04f960c" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jul 05 08:24:46 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jul 05 08:24:46 2016 +0000" }, "message": "Merge \"Simplification for associative and commutative operations on constants\"" }, { "commit": "e3fb245fbdb5e91cf8a9750504df40bd629e0080", "tree": "a3882db92b7942b2edd6add3090b5c875fef2d09", "parents": [ "1fdb340de4e608a88e8683c857cad5d0da2c16de" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue May 10 16:08:05 2016 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Fri Jul 01 14:10:14 2016 -0700" }, "message": "MIPS32: Improve method invocation\n\nImprovements include:\n- CodeGeneratorMIPS::GenerateStaticOrDirectCall() supports:\n - MethodLoadKind::kDirectAddressWithFixup (via literals)\n - CodePtrLocation::kCallDirectWithFixup (via literals)\n - MethodLoadKind::kDexCachePcRelative\n- 32-bit literals to support the above (not ready for general-\n purpose applications yet because RA is not saved in leaf\n methods, but is clobbered on MIPS32R2 when simulating\n PC-relative addressing (MIPS32R6 is OK because it has\n PC-relative addressing with the lwpc instruction))\n- shorter instruction sequences for recursive static/direct\n calls\n\nTested:\n- test-art-host-gtest\n- test-art-target-gtest and test-art-target-run-test-optimizing on:\n - MIPS32R2 QEMU\n - CI20 board\n - MIPS32R6 (2nd arch) QEMU\n\nChange-Id: Id5b137ad32d5590487fd154c9a01d3b3e7e044ff\n" }, { "commit": "e14dc86d4e84d52426510d0fafbac3d7e04f960c", "tree": "7ec03801e3dd8d4a6f428239308f1f7700c815fc", "parents": [ "1fdb340de4e608a88e8683c857cad5d0da2c16de" ], "author": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Fri May 13 17:56:15 2016 +0100" }, "committer": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Fri Jul 01 17:45:30 2016 +0100" }, "message": "Simplification for associative and commutative operations on constants\n\nThe purpose of this change is to enable the instruction simplifier\nto recognize patterns such as\n\nOP y, x, const1\nOP z, y, const2\n\nwhere OP is both an associative and a commutative operation on integral\ntypes, and replace them with\n\nOP z, x, const3\n\nSince subtraction on integral types is equivalent to addition with a\nnegated operand, it receives a similar treatment, even though it is\nnot commutative.\n\nChange-Id: I278cac39bd39bc843d250a976931cb000876ea88\n" }, { "commit": "1fdb340de4e608a88e8683c857cad5d0da2c16de", "tree": "e502857a3010f03e11c8898c8150615eb5ff6633", "parents": [ "4890a7c1acab3dcead07bc0c7e8202659764de84", "e90049140fdfb89080e5cc9b000b0c9be8c18bcd" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Jul 01 13:32:35 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jul 01 13:32:36 2016 +0000" }, "message": "Merge \"Create a typedef for HInstruction::GetInputs() return type.\"" }, { "commit": "e90049140fdfb89080e5cc9b000b0c9be8c18bcd", "tree": "66b45c052b6778fabd7847a44af5e610808fa867", "parents": [ "a77ceae14a7be2494874d9256327efa8c522e234" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jun 16 16:50:52 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jul 01 13:26:24 2016 +0100" }, "message": "Create a typedef for HInstruction::GetInputs() return type.\n\nAnd some other cleanup after\n https://android-review.googlesource.com/230742\n\nTest: No new tests. ART test suite passed (tested on host).\nChange-Id: I4743bf17544d0234c6ccb46dd0c1b9aae5c93e17\n" }, { "commit": "7fe30f952f37dd1e829b8d215d023b301cb82ef9", "tree": "af6ffbaaf461f5a99a5deb78d867471d4b5f40f3", "parents": [ "d5ff99ab27db221e23942a0c93fa8d40b9e0c38b" ], "author": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Wed Jun 29 17:03:40 2016 +0100" }, "committer": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Fri Jul 01 11:09:44 2016 +0100" }, "message": "Make the Compute() method of all HIRs static.\n\nChange-Id: Ibd7687dac907150c8e100791ed7d20d1ae18c9be\n" }, { "commit": "04e5e590f4eece8bd88b36d761edd8733f5065a1", "tree": "575cfd219346a5f9357a1c7cf2fc478f989a2dee", "parents": [ "60245ae99539b03e8231b4959e726686c7b34548", "52be7e759acecc3841dca0ac1b703034d8cad60d" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Jun 30 19:44:20 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jun 30 19:44:21 2016 +0000" }, "message": "Merge \"Improvements in induction range analysis.\"" }, { "commit": "e4305391dab34a6ea117c261e5602e9a7457b312", "tree": "b9f36651a2a36cf1c026fef5efa36a5404d63d5e", "parents": [ "46a8e03c9d5104fd70122ba0c0eb70d8093bc6d9", "35ca3594ab923dc06e7424bcf0453c9ff6b5a0fb" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 30 08:36:58 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jun 30 08:36:59 2016 +0000" }, "message": "Merge \"Revert \"Integer.bitCount and Long.bitCount intrinsics for ARM\"\"" }, { "commit": "35ca3594ab923dc06e7424bcf0453c9ff6b5a0fb", "tree": "8a89f45c0d4856b8abaeb140c5e74ffb1487d887", "parents": [ "2a17419c2e54f8ada0df56daa379c78f8ae8a9e8" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 30 08:36:33 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jun 30 08:36:33 2016 +0000" }, "message": "Revert \"Integer.bitCount and Long.bitCount intrinsics for ARM\"\n\nFails 564:\n\n[ 80% 771/967] build test-art-target-run-test-debug-prebuild-optimizing-relocate-ntrace-cms-checkjni-image-npictest-ndebuggable-564-checker-bitcount32\nchecker exit status: 1\n/b/build/slave/hammerhead-debug/build/art/test/564-checker-bitcount: FAILED!\n \n#################### info\n# Unit test for 32-bit and 64-bit bit count operation.\n#################### diffs\n--- expected.txt\t2016-06-08 02:57:45.570840797 -0700\n+++ output.txt\t2016-06-29 09:45:45.813173505 -0700\n@@ -1 +1,3 @@\n passed\n+error: Test case not found in the CFG file\n+Main.java:32: int Main.$noinline$BitCountByte(byte) intrinsics_recognition (after)\n####################\n \n564-checker-bitcount files deleted from host \nand from target\ntest-art-target-run-test-debug-prebuild-optimizing-relocate-ntrace-cms-checkjni-image-npictest-ndebuggable-564-checker-bitcount32 FAILED\n\nThis reverts commit 2a17419c2e54f8ada0df56daa379c78f8ae8a9e8.\n\nChange-Id: I263cfc09ebf78956cd1e86a0bb59ba1b36ffeafe\n" }, { "commit": "8bf8117c6b421d4e81c2be76825ffc83703f1ef1", "tree": "9a063897fa29f859dba265825af60b9781bd2a56", "parents": [ "04a23d7e10fa42c5047b6f08048dbaacd1e74fcd", "c7591b4c0dd405a766f4d701deea6c3750101978" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jun 29 17:20:53 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jun 29 17:20:53 2016 +0000" }, "message": "Merge \"Fix merging HLoadClass with HNewInstance.\"" }, { "commit": "52be7e759acecc3841dca0ac1b703034d8cad60d", "tree": "c6ed5e85c33d8938dbbe2b7ca5ecf7e00292884c", "parents": [ "4dd9d82d6c1260b3da908a0d1a22b7d209b87496" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Jun 23 11:20:41 2016 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Jun 29 09:34:28 2016 -0700" }, "message": "Improvements in induction range analysis.\n\nRationale:\nUses range analysis while determining whether trip-counts\nare \"safe\", which improves analysis of triangular loops.\nAlso implements more effective triangular loop analysis\nby evaluating induction information only once and using\na top level hint (instead of the \"iterative refinement\"\nthat was used earlier). Also fixes analysis of triangular\ntrip counts that may wrap-around. All with tests.\n\nTest: see induction_var_range_test/530-checker-loops*\n\nBUG\u003d27151190\n\nChange-Id: I1877c8ce0c9a52005900eb9dfdbb1918df100278\n" }, { "commit": "c7591b4c0dd405a766f4d701deea6c3750101978", "tree": "1cfc5ed4117fad1ca89bc764c0cdc0011a5d2c24", "parents": [ "f249230400a1da6280887542a746f1b47a4b8863" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jun 29 14:59:07 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jun 29 17:12:25 2016 +0100" }, "message": "Fix merging HLoadClass with HNewInstance.\n\nDo not merge HLoadClass with HNewInstance if they do not\ncome from the same dex instruction. This is the same check\nas for moving the clinit check responsibility around.\n\nTest: Added a regression test, run standard ART test suite\nplus gcstress and ndebug modes on host and Nexus 9.\n\nBug: 29570861\nBug: 29321958\nChange-Id: Id8b67492ec1f58326ca0509af3f5a57257e7aea3\n" }, { "commit": "2a17419c2e54f8ada0df56daa379c78f8ae8a9e8", "tree": "43040832138f995c796aa5a7f3f3fd200cfc968d", "parents": [ "9c23cec9532fdc4bb5cce470890c5d317dbee934" ], "author": { "name": "xueliang.zhong", "email": "xueliang.zhong@linaro.org", "time": "Tue May 24 15:37:28 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Jun 29 12:43:11 2016 +0000" }, "message": "Integer.bitCount and Long.bitCount intrinsics for ARM\n\nChange-Id: Ia535865721313e72925fdec851a759470173cf89\n" }, { "commit": "fdbc39551e08fa6a17e1b4bf6904860ccc052aa2", "tree": "0ade9d5225b067f4d0369e5369975c1e8d9f345f", "parents": [ "34bccc1d85787658a5d04d2caa52b6eeca18710f", "e8e1127da3f154fae8d2eb16a94203544a182159" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Wed Jun 29 12:33:23 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jun 29 12:33:23 2016 +0000" }, "message": "Merge \"Do checks on the fault address when we think it\u0027s an NPE.\"" }, { "commit": "34bccc1d85787658a5d04d2caa52b6eeca18710f", "tree": "37485e533353bcf1c86bd9cba749980dc403f39d", "parents": [ "bb8d501c9bb882a8927c6ceda07bf9577e06c3e1", "bde6ae1c6e1bc0ea1c8d80e3b0ec401517c6d7f7" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Wed Jun 29 11:34:00 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jun 29 11:34:00 2016 +0000" }, "message": "Merge \"ARM64: Ensure stricter alignment when loading and storing register pairs\"" }, { "commit": "e8e1127da3f154fae8d2eb16a94203544a182159", "tree": "930aa5bd3f4e81dcf1b27043844da55a3dcb5cc4", "parents": [ "739dc72773c5dee583a1d322f91b5abd61f9889d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Jun 28 18:08:46 2016 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 29 12:31:52 2016 +0100" }, "message": "Do checks on the fault address when we think it\u0027s an NPE.\n\nbug:29321958\nChange-Id: I28f4da56eb3e0b48721d3ac41114858bc80daadb\n" }, { "commit": "88f288e3564d79d87c0cd8bb831ec5a791ba4861", "tree": "dd051a7b2985d1af3fea91ad6000de4bdc701a19", "parents": [ "e36389f20c83083c0aaba2dcac0888951e55cae1" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 29 08:17:52 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 29 08:41:25 2016 +0000" }, "message": "Revert \"Optimize IMT\"\n\nBug: 29188168 (for initial CL)\nBug: 29778499 (reason for revert)\n\nThis reverts commit badee9820fcf5dca5f8c46c3215ae1779ee7736e.\n\nChange-Id: I32b8463122c3521e233c34ca95c96a5078e88848\n" }, { "commit": "e36389f20c83083c0aaba2dcac0888951e55cae1", "tree": "3fe74b637f8dc90e3cbc8ad3949f3f340236537f", "parents": [ "abf64415cf99a9a7ee048ae26c76f7bbe972a6b9", "d4ceecc85a5aab2ec23ea1bd010692ba8c8aaa0c" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 29 08:40:14 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jun 29 08:40:14 2016 +0000" }, "message": "Merge \"Revert \"Refactor GetIMTIndex\"\"" }, { "commit": "d4ceecc85a5aab2ec23ea1bd010692ba8c8aaa0c", "tree": "982948a67a88a1f9a734c935f919f8d307969f48", "parents": [ "50706437d8216e41f0fea1e413cda7891324d397" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 29 08:39:47 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 29 08:39:47 2016 +0000" }, "message": "Revert \"Refactor GetIMTIndex\"\n\nI need to revert this to get https://android-review.googlesource.com/#/c/244190/ to cleanly revert. Matthew, do you mind rewriting it?\n\nThis reverts commit 50706437d8216e41f0fea1e413cda7891324d397.\n\nChange-Id: I5c1435f5dffb46dbb5b613b22adb88c7770304f2\n" }, { "commit": "f249230400a1da6280887542a746f1b47a4b8863", "tree": "2a4be6c96b961fcd2451c04ba02c8a2cf8d998e6", "parents": [ "d5d0c7b6ab545a1ffb8bc1063ecbed1aac10922e", "50518449afe8fa7eb741f42c904fb4baf6c34da2" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Jun 28 10:33:35 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jun 28 10:33:36 2016 +0000" }, "message": "Merge \"Optimize away useless masking operations on shift amounts.\"" }, { "commit": "d5d0c7b6ab545a1ffb8bc1063ecbed1aac10922e", "tree": "4c267f649fe397c4709d17b010cdf31e81c17339", "parents": [ "99376148af84b3c2bcc0b39c15313f69cef82fb9", "047664d88280f3517fe3d2c9cccf32521f6e80fd" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Jun 28 10:29:56 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jun 28 10:29:56 2016 +0000" }, "message": "Merge \"MIPS64: Remove the workaround in VisitInvokeStaticOrDirect\"" }, { "commit": "bde6ae1c6e1bc0ea1c8d80e3b0ec401517c6d7f7", "tree": "b8b358dbab45a235af3413b6750db13419d81dc2", "parents": [ "47fe36d8dea0309e5ff08fc77244a371ba10d9db" ], "author": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Fri Jun 10 17:46:12 2016 +0100" }, "committer": { "name": "Anton Kirilov", "email": "anton.kirilov@linaro.org", "time": "Tue Jun 28 11:07:24 2016 +0100" }, "message": "ARM64: Ensure stricter alignment when loading and storing register pairs\n\nThe impetus for this change is the fact that loads that cross a 64 byte\nboundary and stores that cross a 16 byte boundary are a performance issue\non Cortex-A57 and A72.\n\nChange-Id: I81263dc72272192ad2d190b741a955f175880461\n" }, { "commit": "47fe36d8dea0309e5ff08fc77244a371ba10d9db", "tree": "62eeef0f074b1536ca1901c07158ea8ec2b74602", "parents": [ "05f0167cdd207edecaebf2cac7eea879678147c5", "a871ef1e61f901093abf90607ba272b7a8ce1100" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Jun 28 09:49:33 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jun 28 09:49:33 2016 +0000" }, "message": "Merge \"MIPS32: Drop redundant moves in integer conversions\"" }, { "commit": "50518449afe8fa7eb741f42c904fb4baf6c34da2", "tree": "e88f92b642b79e136a1c8c20680e9430ed4c1cfb", "parents": [ "105683791e6b3f017a1a5673df22bf2185e19b54" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Mon Jun 27 11:39:19 2016 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Tue Jun 28 09:32:41 2016 +0100" }, "message": "Optimize away useless masking operations on shift amounts.\n\nChange-Id: I90d69757cc45312eda3d57cc2d32bfb4e47963f5" }, { "commit": "a871ef1e61f901093abf90607ba272b7a8ce1100", "tree": "a16254aaa37a2279c781531c7cef4627e96fdbf1", "parents": [ "12e6e9f3f1352ed58ddd41c7f31831011695b9e4" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Jun 27 15:20:11 2016 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Jun 27 15:34:19 2016 -0700" }, "message": "MIPS32: Drop redundant moves in integer conversions\n\nChange-Id: I0e3f393d87538eb9e35b3012ea36e81c8b7a225e\n" }, { "commit": "b93a16517dce12b83e9d5d3b599446e25fcc157a", "tree": "64de16f7af5a1d8de3c33072309248ff18e24f4d", "parents": [ "1e28d1e145a898e34dbb43bb655d905653e9c1e9" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 27 10:03:29 2016 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jun 27 16:33:19 2016 +0100" }, "message": "Do not remove loads/store with unresolved accesses.\n\nDue to AOT and compiling classes that are not ready yet\n(eg missing a super class), we need to be conservative when\naccessing fields and can end up in a situation where the same\nfield can be resolved and unresolved within the same method\n(because of inlining). Therefore, disable removing loads and\nstores in a method when there are unresolved accesses.\n\nbug:29433999\n\nChange-Id: I8fcfb52c584222474a8220eb16c6581350b702e0\n" }, { "commit": "1e28d1e145a898e34dbb43bb655d905653e9c1e9", "tree": "eba79ad8458091c9224768259efede81f7dc8533", "parents": [ "7caad2a084dcd66ea26cd98934ee0d278e7ce806", "7f7f6dae98b0b1959348ffc84d8e347a26561226" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Fri Jun 24 18:58:53 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jun 24 18:58:54 2016 +0000" }, "message": "Merge \"ART: OneBit intrinsics should use 1ULL for 64-bit shift\"" }, { "commit": "31167a5785f7a5124de96535066db9890559f546", "tree": "3d0ddb1bb390389532b5fc94dd6f2f5c8d648582", "parents": [ "bad21cb538d76105712c967b62d1cf677777a956", "3d31242300c3525e5c85665d9e34acf87002db63" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jun 24 13:04:36 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jun 24 13:04:37 2016 +0000" }, "message": "Merge changes I4d8da7ce,I4da5be01,Idfbead82\n\n* changes:\n Re-enable most intrinsics with read barriers.\n Fix ARM \u0026 ARM64 UnsafeGetObject intrinsics with read barriers.\n Fix x86 \u0026 x86-64 UnsafeGetObject intrinsics with read barriers.\n" }, { "commit": "7f7f6dae98b0b1959348ffc84d8e347a26561226", "tree": "cd1026c21e9c5b0dfbfa2b79b357b2fcf16f2774", "parents": [ "79fb0a294c2a98c6456484207368a31a86b8e085" ], "author": { "name": "Pavel Vyssotski", "email": "pavel.n.vyssotski@intel.com", "time": "Wed Jun 22 12:36:10 2016 +0600" }, "committer": { "name": "Pavel Vyssotski", "email": "pavel.n.vyssotski@intel.com", "time": "Fri Jun 24 11:52:22 2016 +0600" }, "message": "ART: OneBit intrinsics should use 1ULL for 64-bit shift\n\nChange-Id: I91cbe769081045e6a45a95154a8a8acf1ec352ef\nSigned-off-by: Pavel Vyssotski \u003cpavel.n.vyssotski@intel.com\u003e\n" }, { "commit": "79fb0a294c2a98c6456484207368a31a86b8e085", "tree": "cd03117442a13e0b77a1c7cd8a5039cdfced72b5", "parents": [ "156d8ca8c104ae1379c33d3cd0279e7a6a3f8f45", "94ab38f01dc2cf3ed0c6e73e2a6b594c14758d67" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Jun 23 17:37:51 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jun 23 17:37:51 2016 +0000" }, "message": "Merge \"ART: Run RTP if invoke inputs have more specific type\"" }, { "commit": "047664d88280f3517fe3d2c9cccf32521f6e80fd", "tree": "181bd4e4c6e044084b34495b0e39bd13714c871b", "parents": [ "ee2d222cc5a2e498540b7f767e76d602efc27178" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Jun 23 11:49:30 2016 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Jun 23 17:53:19 2016 +0200" }, "message": "MIPS64: Remove the workaround in VisitInvokeStaticOrDirect\n\nThis is not needed since $s2-$s8 are not blocked any more. This is\nfollow-up change for I325ab403752c6b9cd788147cb8b21d42aaff629e.\n\nChange-Id: I934a21adb85581e137a6dcb3355605742b085d83\n" }, { "commit": "94ab38f01dc2cf3ed0c6e73e2a6b594c14758d67", "tree": "c6da419571e7bb8d3c83ffb4a80e15042e3667a0", "parents": [ "9a8620e45e6eedadaa476322841e26858d10eeee" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Jun 21 17:48:19 2016 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Jun 23 14:55:42 2016 +0100" }, "message": "ART: Run RTP if invoke inputs have more specific type\n\nMoving RTP inside the graph builder introduced a regression where\nreplacing the inner parameters with the actual arguments of the\nHInvoke would not build the inner graph with types more specific\nthan the method\u0027s signature.\n\nThis patch runs RTP on the inner graph again when it is detected\nthat RTP may improve typing precision.\n\nBug: 29595335\nChange-Id: I351babc8497c83c2fba589aa51f46eaa0b7ab33c\n" }, { "commit": "3d31242300c3525e5c85665d9e34acf87002db63", "tree": "c7f66d95fa3d65241a1c9f10381c1e0ec0989a4e", "parents": [ "bfea33585e229973f7887afbf51fe45c2ba41e91" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jun 23 13:53:42 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jun 23 14:05:17 2016 +0100" }, "message": "Re-enable most intrinsics with read barriers.\n\nAlso extend sun.misc.Unsafe test coverage to exercise\nsun.misc.Unsafe.{get,put}{Int,Long,Object}Volatile.\n\nBug: 26205973\nBug: 29516905\nChange-Id: I4d8da7cee5c8a310c8825c1631f71e5cb2b80b30\nTest: Covered by ART\u0027s run-tests.\n" }, { "commit": "bfea33585e229973f7887afbf51fe45c2ba41e91", "tree": "018aff4a08f760fc489e5784a2b71e90a29a9084", "parents": [ "0fcd2b84210db2bcf8b2d7a2b98a1a2bca367cac" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jun 23 13:48:47 2016 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jun 23 14:05:17 2016 +0100" }, "message": "Fix ARM \u0026 ARM64 UnsafeGetObject intrinsics with read barriers.\n\nThe implementation was incorrectly interpreting the \u0027offset\u0027\ninput as an index in a (4-byte) object reference array,\nwhereas it is a (1-byte) offset to an object reference field\nwithin the \u0027base\u0027 (object) input.\n\nBug: 29516905\nChange-Id: I4da5be0193217965f25e5d141c242592dea6ffe8\nTest: Covered by test/004-UnsafeTest.\n" }, { "commit": "0fcd2b84210db2bcf8b2d7a2b98a1a2bca367cac", "tree": "4619d1fb4bda64c01df3a6588b5c726510a72a1c", "parents": [ "61b370e4559a84910fe5bf0b2b1d7216ce805315" ], "author": { "name": "Sang, Chunlei", "email": "chunlei.sang@intel.com", "time": "Tue Apr 05 17:12:59 2016 +0800" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jun 23 14:05:17 2016 +0100" }, "message": "Fix x86 \u0026 x86-64 UnsafeGetObject intrinsics with read barriers.\n\nThe implementation was incorrectly interpreting the \u0027offset\u0027\ninput as an index in a (4-byte) object reference array,\nwhereas it is a (1-byte) offset to an object reference field\nwithin the \u0027base\u0027 (object) input.\n\nBug: 29516905\nChange-Id: Idfbead8289222b55069816a81284401eff791e85\nTest: Covered by test/004-UnsafeTest.\n" }, { "commit": "d5cc68352e84f33e90a7f8007cd0859c3c1f949d", "tree": "4a1bcb6164bf2179cfd7dc1884d4d8de404e1f97", "parents": [ "5f5560dbce6cd81e885c0d9351c1e6d732c2e0ca" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Jun 22 16:34:46 2016 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Jun 22 16:34:46 2016 -0700" }, "message": "Fixed typo in comment.\n\nChange-Id: I818e5e67d664dfd2bddd464ed8e4f5efceb1fb22\n" }, { "commit": "abc9f689d35b97738401ba1981d45ab06519f3ad", "tree": "f879ccdac60c1c2130d5a740e47b0090ae0fa513", "parents": [ "4692c35c151951aa1fa901ca24bfa302a9beeacf", "782be11b39b4b3636e6928afc8b9bbac541a50ea" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Jun 21 16:54:17 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jun 21 16:54:17 2016 +0000" }, "message": "Merge \"MIPS64: Unblock callee-save registers\"" }, { "commit": "4692c35c151951aa1fa901ca24bfa302a9beeacf", "tree": "8d28d7714dd7fa0ae1ff44888ae61f3c8786bfeb", "parents": [ "f6d4f6e0e61977777b7a9ca18b75bcd26e98e9f9", "87f3fcbd0db352157fc59148e94647ef21b73bce" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 21 16:18:10 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jun 21 16:18:10 2016 +0000" }, "message": "Merge \"Replace String.charAt() with HIR.\"" }, { "commit": "87f3fcbd0db352157fc59148e94647ef21b73bce", "tree": "5bdeabb246f5de86704333b3fcbccc6e9146d246", "parents": [ "b94b5706f0b8e2e1c7e1db22274f9f4bae0c4b5a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Apr 28 15:52:11 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 21 15:17:38 2016 +0100" }, "message": "Replace String.charAt() with HIR.\n\nReplace String.charAt() with HArrayLength, HBoundsCheck and\nHArrayGet. This allows GVN on the HArrayLength and BCE on\nthe HBoundsCheck as well as using the infrastructure for\nHArrayGet, i.e. better handling of constant indexes than\nthe old intrinsic and using the HArm64IntermediateAddress.\n\nBug: 28330359\nChange-Id: I32bf1da7eeafe82537a60416abf6ac412baa80dc\n" }, { "commit": "dbb7f5bef10138ade0fb202da1d61f562b2df649", "tree": "f0aa4b390c534b215a6e000c865783cdd9852353", "parents": [ "b94b5706f0b8e2e1c7e1db22274f9f4bae0c4b5a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Mar 30 13:23:58 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 21 15:11:57 2016 +0100" }, "message": "Improve HLoadClass code generation.\n\nFor classes in the boot image, use either direct pointers\nor PC-relative addresses. For other classes, use PC-relative\naccess to the dex cache arrays for AOT and direct address of\nthe type\u0027s dex cache slot for JIT.\n\nFor aosp_flounder-userdebug:\n - 32-bit boot.oat: -252KiB (-0.3%)\n - 64-bit boot.oat: -412KiB (-0.4%)\n - 32-bit dalvik cache total: -392KiB (-0.4%)\n - 64-bit dalvik-cache total: -2312KiB (-1.0%)\n (contains more files than the 32-bit dalvik cache)\nFor aosp_flounder-userdebug forced to compile PIC:\n - 32-bit boot.oat: -124KiB (-0.2%)\n - 64-bit boot.oat: -420KiB (-0.5%)\n - 32-bit dalvik cache total: -136KiB (-0.1%)\n - 64-bit dalvik-cache total: -1136KiB (-0.5%)\n (contains more files than the 32-bit dalvik cache)\n\nBug: 27950288\nChange-Id: I4da991a4b7e53c63c92558b97923d18092acf139\n" }, { "commit": "782be11b39b4b3636e6928afc8b9bbac541a50ea", "tree": "ff7f0755263aff0ca2cedea6558759be36a61c23", "parents": [ "b94b5706f0b8e2e1c7e1db22274f9f4bae0c4b5a" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Tue Jun 21 12:39:04 2016 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Tue Jun 21 14:13:28 2016 +0200" }, "message": "MIPS64: Unblock callee-save registers\n\nCallee-save registers shouldn\u0027t be blocked, except floating point\nregisters if the graph is debuggable.\n\nChange-Id: I325ab403752c6b9cd788147cb8b21d42aaff629e\n" }, { "commit": "d5aa626b286b61efba49067c5fd6f75957c7969e", "tree": "93e48121cb0ba9ed978e6d4c8e5e24b71a848481", "parents": [ "30564fd3c9e4d4a8ef2e82da3fe9c9da1b7ccd01", "3fdab77aa9949e18aee2734a9eac271f36dedefb" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 17 12:02:41 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jun 17 12:02:41 2016 +0000" }, "message": "Merge \"ARM: Improve String.getCharsNoCheck intrinsic.\"" }, { "commit": "3fdab77aa9949e18aee2734a9eac271f36dedefb", "tree": "d37a864b177222eb116491a4740119016fa7d32c", "parents": [ "453134813e9ba2b91622550d76ddff44a1ab48ab" ], "author": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Mon Apr 25 11:32:37 2016 +0100" }, "committer": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Fri Jun 17 09:16:33 2016 +0100" }, "message": "ARM: Improve String.getCharsNoCheck intrinsic.\n\n- Optimize for short retrievals.\n- Improve performance of longer retrievals with unrolled LDR/STR.\n\nChange-Id: I24ec52067104b2f68799c04aebb61d20fff94020\n" }, { "commit": "7adaab070bbe9783130e78eea163c459303c980b", "tree": "fe92c29bf891076c094ceb40a314a8b694d6187d", "parents": [ "48f9f28c9b7b0b9c0f6339da8df2aa41c89d0254" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Thu Apr 21 14:49:20 2016 -0700" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Thu Jun 16 09:38:38 2016 -0700" }, "message": "MIPS64: java.lang.Math.round\n\n- int java.lang.Math.round(float)\n- long java.lang.Math.round(double)\n\nBUG\u003d26327751\n\nChange-Id: I8bb7a5f32375b06b886a0babf39eb3e20df3a085\n" }, { "commit": "8a0b9bf88aa055b2669825048dff6353dd04aafb", "tree": "51ed6b7a5436f191acea09f42def0c44c2ee6bd3", "parents": [ "edbcf54199cab8557f93ef3d136e4c2f335b915e", "50706437d8216e41f0fea1e413cda7891324d397" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Thu Jun 16 00:28:15 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jun 16 00:28:15 2016 +0000" }, "message": "Merge \"Refactor GetIMTIndex\"" }, { "commit": "abdda2fb52eb7e9a6916899a913f78251d8ed277", "tree": "165a31831ae077827b1e7b973bd5602125b5b142", "parents": [ "2b87a47c09823031c4fe336dcef0867605debfd7", "badee9820fcf5dca5f8c46c3215ae1779ee7736e" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed Jun 15 17:44:14 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jun 15 17:44:14 2016 +0000" }, "message": "Merge \"Optimize IMT\"" }, { "commit": "50706437d8216e41f0fea1e413cda7891324d397", "tree": "23c7c5d1198b8cdde6261198626cfe443eab59ba", "parents": [ "badee9820fcf5dca5f8c46c3215ae1779ee7736e" ], "author": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Tue Jun 14 11:31:04 2016 -0700" }, "committer": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Wed Jun 15 09:08:35 2016 -0700" }, "message": "Refactor GetIMTIndex\n\nThis allows us to more easily maintain and experiment with\ninterface method table indexing and hashing.\n\nChange-Id: I719920fae7490dcedcda7c1c36db225c2b8b16df\n" }, { "commit": "badee9820fcf5dca5f8c46c3215ae1779ee7736e", "tree": "982948a67a88a1f9a734c935f919f8d307969f48", "parents": [ "614968198625a6693666bdc1e5609e2f663f5638" ], "author": { "name": "Nelli Kim", "email": "nelli.kim@samsung.com", "time": "Fri May 13 13:08:53 2016 +0300" }, "committer": { "name": "Matthew Gharrity", "email": "gharrma@google.com", "time": "Tue Jun 14 10:05:47 2016 -0700" }, "message": "Optimize IMT\n\n* Remove IMT for classes which do not implement interfaces\n* Remove IMT for array classes\n* Share same IMT\n\nSaved memory (measured on hammerhead):\nboot.art:\nTotal number of classes: 3854\nNumber of affected classes: 1637\nSaved memory: 409kB\n\nChrome (excluding classes in boot.art):\nTotal number of classes: 2409\nNumber of affected classes: 1259\nSaved memory: 314kB\n\nGoogle Maps (excluding classes in boot.art):\nTotal number of classes: 6988\nNumber of affected classes: 2574\nSaved memory: 643kB\n\nPerformance regression on benchmarks/InvokeInterface.java benchmark\n(measured timeCall10Interface)\n1st launch: 9.6%\n2nd launch: 6.8%\n\nChange-Id: If07e45390014a6ee8f3c1c4ca095b43046f0871f\n" }, { "commit": "63e0a7d057adbe17ba0d34624d83f1120cb1162f", "tree": "48e74e115ce02a27cbe8b72d22b1dab041b01278", "parents": [ "294ce238cb0cdd9cd9854994df2c9b23b8c6ce76", "df109d9cb1fd4544e464fa7f7798f04268eb436e" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 14 09:06:24 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jun 14 09:06:25 2016 +0000" }, "message": "Merge \"ARM64: Improve String.getCharsNoCheck intrinsic.\"" }, { "commit": "880f119810869ae8dad3803dfd4d3a02c94a8711", "tree": "df2328d07e0ebde211e64cc0add062a97e2139b5", "parents": [ "cace1ba2ab3a28c335005c73d160d9c0401a0e4e" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Mon Jun 13 16:04:50 2016 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Mon Jun 13 16:04:50 2016 +0100" }, "message": "ARM64: Use VIXL\u0027s conditional select helper.\n\nChange-Id: Id6bb880e2fffb54cf1f480191fc734eaaf4cd293" }, { "commit": "df109d9cb1fd4544e464fa7f7798f04268eb436e", "tree": "705593edcaaa9844d8c25372d8f075546bf82bc3", "parents": [ "834f4445e70543bfdbcdd6435ccceb7a6dd82c4d" ], "author": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Fri Apr 22 11:35:56 2016 +0100" }, "committer": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Mon Jun 13 15:00:36 2016 +0100" }, "message": "ARM64: Improve String.getCharsNoCheck intrinsic.\n\n- Optimize for \u003c 8 characters.\n- Improve performance of longer retrievals with LDP/STP.\n\nChange-Id: Ib9a9507ae652a439c7fdcab5cc916e1930722228\n" }, { "commit": "206fbf51ccd2dbbcf106e480cc6c5bb96fc7befb", "tree": "38c57afab97083c1d805a381c1dfa0764605fec6", "parents": [ "834f4445e70543bfdbcdd6435ccceb7a6dd82c4d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jun 10 16:06:34 2016 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Jun 13 14:14:43 2016 +0100" }, "message": "Remove too aggressive DCHECKs.\n\nA class can move from a state greater or equal than resolved\nto erroneous concurrently to the verifier or the compiler.\n\nbug:29239283\nChange-Id: I89f3fe1c1d9556c6c99b8e005b3ec02de7f01b85\n(cherry picked from commit f7d994622aabcc689f62253a9253e0c67d9e787e)\n" }, { "commit": "296fbb4c3a629ec99149e512ddb66d7b4d7854fe", "tree": "efdf1998a9bd2aa55a0962d01300412c366c0042", "parents": [ "88b970c24162c0b223f724e664a6da08ae6bfc5c" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Jun 07 13:49:12 2016 -0700" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Jun 08 09:41:33 2016 -0700" }, "message": "Do not place null check on unresolved method calls.\n\nRationale:\nThese invokes drop through the runtime anyway where various\nchecks are done, including null check. A few of these\nchecks need to occur before the null check.\n\nWith fail-before/pass-after smali test.\n\nBUG\u003d29068831\n\nChange-Id: I260715e742365433a323598d97f7fdab321e8512\n" }, { "commit": "88b970c24162c0b223f724e664a6da08ae6bfc5c", "tree": "68cadc43e2c0bb665511a247339964ec51e6f764", "parents": [ "83968f1a0949972e728d2302a26f9ae98dff34b2", "31883646547a036f58b9fa0894eb0fac0bcf05a1" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Jun 07 18:16:05 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jun 07 18:16:06 2016 +0000" }, "message": "Merge \"Do not hide instance field hard failure with soft failure\"" } ], "next": "31883646547a036f58b9fa0894eb0fac0bcf05a1" }