)]}' { "log": [ { "commit": "dce016eab87302f02b0bd903dd2cd86ae512df2d", "tree": "3af3c0e6b9d845e611b560484882e6b438ef439a", "parents": [ "a246510965fc57ec51d1b202649304535adfe9f3" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Apr 28 13:10:02 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon May 09 20:40:32 2016 +0100" }, "message": "Intrinsify String.length() and String.isEmpty() as HIR.\n\nUse HArrayLength for String.length() in anticipation of\nchanging the String.charAt() to HBoundsCheck+HArrayGet to\nallow the existing BCE to seamlessly work for strings.\nUse HArrayLength+HEqual for String.isEmpty().\n\nWe previously relied on inlining but we now want to apply\nthe new intrinsics even when we do not inline, i.e. when\ncompiling debuggable (as is currently the case for boot\nimage) or when we hit inlining limits, i.e. depth, size,\nor the number of accumulated dex registers.\n\nBug: 28330359\nChange-Id: Iab9d2f6d2967bdd930a72eb461f27efe8f37c103\n" }, { "commit": "c01a66465a398ad15da90ab2bdc35b7f4a609b17", "tree": "e85cb2aa05be5c1491814fa83b94748439b8394b", "parents": [ "dad35b0762f97ce79ce3b9a35c9df5021b7dbd17" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Apr 15 11:54:06 2016 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Apr 15 11:54:06 2016 +0100" }, "message": "Fix: correctly destruct VIXL labels.\n\nBug: 27505766\nChange-Id: I077465e3d308f4331e7a861902e05865f9d99835" }, { "commit": "d58b837ae41c6d8ce010c362e8f85bd938715900", "tree": "a7c8e90ff825838bb27707d14487c0333f2cc5f6", "parents": [ "ec9a828fa4a4638d2d17124c4fa835f15c7c5589" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Apr 12 18:51:43 2016 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Apr 12 21:04:13 2016 +0100" }, "message": "Allocate code generators on the arena.\n\nChange-Id: If8cf0ee43711f6e13171443e3c057ff370ccfbaa\n" }, { "commit": "dee58d6bb6d567fcd0c4f39d8d690c3acaf0e432", "tree": "5a2f20546ca3c1544c44bee560062580e22dc79c", "parents": [ "391e155a6936a05bd39b171031ec21d2dee62133" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Apr 07 09:54:26 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Apr 07 16:03:16 2016 +0000" }, "message": "Revert \"Revert \"Refactor HGraphBuilder and SsaBuilder to remove HLocals\"\"\n\nThis patch merges the instruction-building phases from HGraphBuilder\nand SsaBuilder into a single HInstructionBuilder class. As a result,\nit is not necessary to generate HLocal, HLoadLocal and HStoreLocal\ninstructions any more, as the builder produces SSA form directly.\n\nSaves 5-15% of arena-allocated memory (see bug for more data):\n GMS 20.46MB \u003d\u003e 19.26MB (-5.86%)\n Maps 24.12MB \u003d\u003e 21.47MB (-10.98%)\n YouTube 28.60MB \u003d\u003e 26.01MB (-9.05%)\n\nThis CL fixed an issue with parsing quickened instructions.\n\nBug: 27894376\nBug: 27998571\nBug: 27995065\n\nChange-Id: I20dbe1bf2d0fe296377478db98cb86cba695e694\n" }, { "commit": "60328910cad396589474f8513391ba733d19390b", "tree": "01702f6df5c39925b354a3152dd04289e7d97062", "parents": [ "e3ff7b293be2a6791fe9d135d660c0cffe4bd73f" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Apr 04 17:47:42 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Apr 04 17:47:42 2016 +0000" }, "message": "Revert \"Refactor HGraphBuilder and SsaBuilder to remove HLocals\"\n\nBug: 27995065\nThis reverts commit e3ff7b293be2a6791fe9d135d660c0cffe4bd73f.\n\nChange-Id: I5363c7ce18f47fd422c15eed5423a345a57249d8\n" }, { "commit": "e3ff7b293be2a6791fe9d135d660c0cffe4bd73f", "tree": "d578d27cb78e6d2caef683cd8ac94c9a9752b192", "parents": [ "86ea7eeabe30c98bbe1651a51d03cb89776724e7" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Wed Mar 02 16:48:20 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Apr 04 11:21:30 2016 +0100" }, "message": "Refactor HGraphBuilder and SsaBuilder to remove HLocals\n\nThis patch merges the instruction-building phases from HGraphBuilder\nand SsaBuilder into a single HInstructionBuilder class. As a result,\nit is not necessary to generate HLocal, HLoadLocal and HStoreLocal\ninstructions any more, as the builder produces SSA form directly.\n\nSaves 5-15% of arena-allocated memory (see bug for more data):\n GMS 20.46MB \u003d\u003e 19.26MB (-5.86%)\n Maps 24.12MB \u003d\u003e 21.47MB (-10.98%)\n YouTube 28.60MB \u003d\u003e 26.01MB (-9.05%)\n\nBug: 27894376\nChange-Id: Iefe28d40600c169c5d306fd2c77034ae19476d90\n" }, { "commit": "cac5a7e871f1f346b317894359ad06fa7bd67fba", "tree": "2df7d4892216a7c976dfe848c9893cb5eb8fa6a5", "parents": [ "6f51d7756a9c66007fe7666b19399e1f60ff6092" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Feb 22 10:39:50 2016 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Mar 29 19:27:40 2016 +0100" }, "message": "Optimizing: Improve const-string code generation.\n\nFor strings in the boot image, use either direct pointers\nor pc-relative addresses. For other strings, use PC-relative\naccess to the dex cache arrays for AOT and direct address of\nthe string\u0027s dex cache slot for JIT.\n\nFor aosp_flounder-userdebug:\n - 32-bit boot.oat: -692KiB (-0.9%)\n - 64-bit boot.oat: -948KiB (-1.1%)\n - 32-bit dalvik cache total: -900KiB (-0.9%)\n - 64-bit dalvik cache total: -3672KiB (-1.5%)\n (contains more files than the 32-bit dalvik cache)\nFor aosp_flounder-userdebug forced to compile PIC:\n - 32-bit boot.oat: -380KiB (-0.5%)\n - 64-bit boot.oat: -928KiB (-1.0%)\n - 32-bit dalvik cache total: -468KiB (-0.4%)\n - 64-bit dalvik cache total: -1928KiB (-0.8%)\n (contains more files than the 32-bit dalvik cache)\n\nBug: 26884697\nChange-Id: Iec7266ce67e6fedc107be78fab2e742a8dab2696\n" }, { "commit": "e943c3b831dc0da4a6b09e940ae25c3285850e96", "tree": "b4756bbc16f49d50087a881b40722657451e6eac", "parents": [ "7c06aef061fa176331b77a88c1ff2c6ae401a5f0", "d28f4a00933a4a3b8d5e9db73b8532924d0f989d" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Fri Mar 18 12:37:03 2016 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Mar 18 12:37:03 2016 +0000" }, "message": "Merge \"Generate native debug stackmaps before calls as well.\"" }, { "commit": "d28f4a00933a4a3b8d5e9db73b8532924d0f989d", "tree": "1205844a68ee9e2c502f8ecbfd2d5cf96acd4190", "parents": [ "fbc61e19578d281d05728bcd120e1ace57c2fbd8" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Mon Mar 14 17:14:24 2016 +0000" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu Mar 17 16:58:55 2016 +0000" }, "message": "Generate native debug stackmaps before calls as well.\n\nThe debugger looks up PC of the call instruction, so the runtime\u0027s\nstackmap is not sufficient since it is at PC after the instruction.\n\nChange-Id: I0dd06c0b52e8079ea5d064ea10beb12c93584092\n" }, { "commit": "2ae48182573da7087bffc2873730bc758ec29696", "tree": "d6955329ad876aefd477f7ef8905b070b9ab95dd", "parents": [ "6915898b28cea6c9836ca1be6814d87e89cc6d76" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Mar 16 14:05:09 2016 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Mar 16 14:10:27 2016 +0000" }, "message": "Clean up NullCheck generation and record stats about it.\n\nThis removes redundant code from the generators and allows for easier\nstat recording.\n\nChange-Id: Iccd4368f9e9d87a6fecb863dee4e2145c97851c4\n" }, { "commit": "9cd6d378bd573cdc14d049d32bdd22a97fa4d84a", "tree": "be293c89806b919143b7dcd203bae14f5f4eaf04", "parents": [ "0e02ee9efbf1dbdde05d2b10f7307bbe191c52f5" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Feb 09 15:24:47 2016 +0000" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Feb 24 10:25:29 2016 +0000" }, "message": "Associate slow paths with the instruction that they belong to.\n\nAlmost all slow paths already know the instruction they belong to,\nthis CL just moves the knowledge to the base class as well.\n\nThis is needed to be be able to get the corresponding dex pc for\nslow path, which allows us generate better native line numbers,\nwhich in turn fixes some native debugging stepping issues.\n\nChange-Id: I568dbe78a7cea6a43a4a71a014b3ad135782c270\n" }, { "commit": "c7098ff991bb4e00a800d315d1c36f52a9cb0149", "tree": "3a150e927bc7f4894f5b148ec6f5a2b796cdd80d", "parents": [ "5322e55ab9a15996a197456ca39d9c77488cd5c1" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Feb 09 14:30:11 2016 +0000" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Feb 24 10:21:57 2016 +0000" }, "message": "Remove HNativeDebugInfo from start of basic blocks.\n\nWe do not require full environment at the start of basic block.\nThe dex pc contained in basic block is sufficient for line mapping.\n\nChange-Id: I5ba9e5f5acbc4a783ad544769f9a73bb33e2bafa\n" }, { "commit": "6e332529c33be4d7dae5dad3609a839f4c0d3bfc", "tree": "cedd2e1beb170fd5821136fe974e3f34adfcddc2", "parents": [ "d3caabd4f85f86dd744da432993e12935d843a83" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Feb 02 16:15:27 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Feb 12 15:17:50 2016 +0000" }, "message": "ART: Remove HTemporary\n\nChange-Id: I21b984224370a9ce7a4a13a9652503cfb03c5f03\n" }, { "commit": "b331febbab8e916680faba722cc84b66b84218a3", "tree": "35f985b021e476914bfe91492da23fee218014a7", "parents": [ "586996afc905518ed926e4680aab67bedabec9b7" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Feb 05 16:51:53 2016 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Feb 05 17:11:54 2016 +0000" }, "message": "Revert \"Revert \"Implement on-stack replacement for arm/arm64/x86/x86_64.\"\"\n\nThis reverts commit bd89a5c556324062b7d841843b039392e84cfaf4.\n\nChange-Id: I08d190431520baa7fcec8fbdb444519f25ac8d44\n" }, { "commit": "58282f4510961317b8d5a364a6f740a78926716f", "tree": "5d97c0db9fe01dd6e8df2357ef11f614abb853e8", "parents": [ "b8bb9f6d0b59be125066f604f134155f8998f5ae" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Jan 14 12:45:10 2016 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Jan 18 16:39:30 2016 +0000" }, "message": "ART: Remove Baseline compiler\n\nWe don\u0027t need Baseline any more and it hasn\u0027t been maintained for\na while anyway. Let\u0027s remove it.\n\nChange-Id: I442ed26855527be2df3c79935403a25b1ee55df6\n" }, { "commit": "42249c3602c3d0243396ee3627ffb5906aa77c1e", "tree": "1e822a21c87331246cbde3923eac88fa315fa2cc", "parents": [ "922698ded1e80cad1ecce4c2172a88c76a216373" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Thu Jan 07 15:33:50 2016 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Tue Jan 12 16:39:20 2016 -0800" }, "message": "Reduce code size by sharing slow paths.\n\nRationale:\nSharing identical slow path code reduces code size.\n\nBackground:\nCurrently, slow paths with the same dex-pc, same physical register\nspilling code, and identical stack maps are shared (making this\nonly useful for deopt slow paths). The newly introduced mechanism\nis sufficiently general to allow future improvements by e.g.\nallowing different dex-pc (by passing this to runtime) or even\nthe kind of slow paths (by passing runtime addresses to the slowpath).\n\nChange-Id: I819615c47b4fd98440a241f681f93e4fc22d12e0\n" }, { "commit": "b7070a2db8b0b7eca14f01f932be305be64ded57", "tree": "06ba87d56a708712fb206e23d3abd55f21934373", "parents": [ "ae6f23c83e1c8dcfbc4f74186ea1a37f1044414b" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Fri Jan 08 18:13:53 2016 +0000" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Mon Jan 11 12:22:17 2016 +0000" }, "message": "Generate Nops to ensure that debug stack maps have distinct PC.\n\nChange-Id: I5740ec958a20d236634b66df0e675382ed5c16fc\n" }, { "commit": "f71b3ade9c99ce2fec2f5049ce9c5968721e1b81", "tree": "fcda284846a6a468e39aec2783812d2d1129a35e", "parents": [ "d48015603a54b820d287d92709825765159615f0" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Dec 08 15:05:08 2015 +0000" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu Dec 10 16:18:54 2015 +0000" }, "message": "Get source mapping table from stack maps.\n\nStack maps contain pc to dex mapping.\nReuse them instead of maintaining separate map.\n\nChange-Id: Iaaec9a6bd2603eace1dfc8f4344087883d88cce3\n" }, { "commit": "0d5a281c671444bfa75d63caf1427a8c0e6e1177", "tree": "fd9bbe0f1c581bcc7c05bbfb2643ffe0b1fb014e", "parents": [ "dd4cbcc924c8ba2a578914a4a366996693bdcd74" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Nov 13 10:07:31 2015 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Sun Nov 15 12:16:41 2015 +0000" }, "message": "x86/x86-64 read barrier support for concurrent GC in Optimizing.\n\nThis first implementation uses slow paths to instrument heap\nreference loads and GC root loads for the concurrent copying\ncollector, respectively calling the artReadBarrierSlow and\nartReadBarrierForRootSlow (new) runtime entry points.\n\nNotes:\n- This implementation does not instrument HInvokeVirtual\n nor HInvokeInterface instructions (for class reference\n loads), as the corresponding read barriers are not stricly\n required with the current concurrent copying collector.\n- Intrinsics which may eventually call (on slow path) are\n disabled when read barriers are enabled, as the current\n slow path infrastructure does not support this case.\n- When read barriers are enabled, the code generated for a\n HArraySet instruction always go into the array set slow\n path for object arrays (delegating the operation to the\n runtime), as we are lacking a mechanism to keep a\n temporary register live accross a runtime call (needed for\n the instrumentation of type checking code, which requires\n two successive read barriers).\n\nBug: 12687968\nChange-Id: I14cd6107233c326389120336f93955b28ffbb329\n" }, { "commit": "0f7dca4ca0be8d2f8776794d35edf8b51b5bc997", "tree": "cb2d99a0e9b7c50eb853a64b477268baaa77c11b", "parents": [ "ce0f43b97ffb5e4d14c5df6607d8efb46a5dc9d2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Nov 02 14:36:43 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Nov 12 10:43:47 2015 +0000" }, "message": "Optimizing/X86: PC-relative dex cache array addressing.\n\nAdd PC-relative dex cache array addressing for X86 and use\nit for better invoke-static/-direct dispatch. Also delay\nthe initialization to the PC-relative base until needed.\n\nChange-Id: Ib8634d5edce4920cd70172fd13211809cf6948d1\n" }, { "commit": "d28b969c273ab777ca9b147b87fcef671b4f695f", "tree": "ca66ecfd809afdcd31443bbe50bf38a836302cc5", "parents": [ "6bf6e438cd4746effce0b26d504c54100191c988" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Nov 04 14:36:55 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Nov 05 10:37:48 2015 +0000" }, "message": "Code cleanup to avoid CompilerDriver abstractions in JIT.\n\nAvoids allocating a CompiledMethod.\n\nChange-Id: I35b4aa0d7c74daba68e827a01e71c300fce3b3bf\n" }, { "commit": "dc151b2346bb8a4fdeed0c06e54c2fca21d59b5d", "tree": "391d8ccb44ff9e6fc1c8fa8975e534e20cc002ff", "parents": [ "823e693aa946ba75cd047429e1290011a2ed8729" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 15 18:02:30 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Oct 23 14:45:32 2015 +0100" }, "message": "Optimizing: Determine invoke-static/-direct dispatch early.\n\nDetermine the dispatch type of invoke-static/-direct in a\nspecial pass right after the type inference. This allows the\ninliner to pass the \"needs dex cache\" check and inline more.\nIt also allows the code generator to avoid requesting a\nregister location for the ArtMethod* for kDexCachePcRelative\nand direct methods.\n\nThe supported dispatch check handles also situations that\nthe CompilerDriver currently doesn\u0027t allow. The cleanup of\nthe CompilerDriver and required changes to Quick will come\nin a separate change.\n\nChange-Id: I3f8e903a119949e95871d8ab0a995f4731a13a07\n" }, { "commit": "5bd05a5c9492189ec28edaf6396d6a39ddf03367", "tree": "186488cafe4d815ab834097e91c75f2c20009e2b", "parents": [ "439ffb8d4fa25b4ac7518a3bd5cbc3f3769ead48" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 13 09:48:30 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Oct 13 17:29:19 2015 +0100" }, "message": "Implement System.arraycopy intrinsic for arm.\n\nChange-Id: I58ae1af5103e281fe59fbe022b718d6d8f293a5e\n" }, { "commit": "b95fb775cc4c08349d0d905adbc96ad85e50601d", "tree": "f8d0212508d5c21f792a1781983d8668d1491aa1", "parents": [ "b2e436ffcda1d7a87e7bf9133d8ed878388c73c2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 30 13:32:31 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Oct 08 11:59:48 2015 +0100" }, "message": "Optimizing: Clean up after tagging arena allocations.\n\nChange-Id: Id6ee1fe44c4c57d373db7a39530f29a5ca9aee18\n" }, { "commit": "98893e146b0ff0e1fd1d7c29252f1d1e75a163f2", "tree": "a14bb10d039fcee10a7e0cacb494bb60d08b2039", "parents": [ "7b5c395e9a50f988ca2275a429df17b6abbcc475" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Oct 02 21:05:03 2015 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Oct 06 13:42:55 2015 +0100" }, "message": "Add support for unresolved classes in optimizing.\n\nChange-Id: I0e299a81e560eb9cb0737ec46125dffc99333b54\n" }, { "commit": "e460d1df1f789c7c8bb97024a8efbd713ac175e9", "tree": "3511036fb18828dd0ee140d33a8bcd0535ebeab6", "parents": [ "25217af2a7cae96b32ba566aaf697288f3374c99" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Sep 29 04:52:17 2015 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Oct 02 02:25:18 2015 +0100" }, "message": "Revert \"Revert \"Support unresolved fields in optimizing\"\n\nThe CL also changes the calling convetion for 64bit static field set\nto use kArg2 instead of kArg1. This allows optimizing to keep\nthe asumptions:\n- arm pairs are always of form (even_reg, odd_reg)\n- ecx_edx is not used as a register on x86.\n\nThis reverts commit e6f49b47b6a4dc9c7684e4483757872cfc7ff1a1.\n\nChange-Id: I93159917565824084abc96775f31be1a4249f2f3\n" }, { "commit": "5233f93ee336b3581ccdb993ff6342c52fec34b0", "tree": "225dc0ab491263ef56362a8d0fe2926266bd5047", "parents": [ "de8a3f4dce1e9ff0e3be16956b06bafc8cd4f397" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Sep 29 19:01:15 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Sep 29 19:46:03 2015 +0100" }, "message": "Optimizing: Tag even more arena allocations.\n\nTag previously \"Misc\" arena allocations with more specific\nallocation types. Move some native heap allocations to the\narena in BCE.\n\nBug: 23736311\nChange-Id: If8ef15a8b614dc3314bdfb35caa23862c9d4d25c\n" }, { "commit": "225b6464a58ebe11c156144653f11a1c6607f4eb", "tree": "3f1c6067c3841c892edaa1a60a61af9c559cb4e4", "parents": [ "6a9984e62c08bcd78c8e49dd40b1f0f9d53513b7" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Sep 28 12:17:40 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Sep 29 10:49:35 2015 +0100" }, "message": "Optimizing: Tag arena allocations in code generators.\n\nAnd completely remove the deprecated GrowableArray.\n\nReplace GrowableArray with ArenaVector in code generators\nand related classes and tag arena allocations.\n\nLabel arrays use direct allocations from ArenaAllocator\nbecause Label is non-copyable and non-movable and as such\ncannot be really held in a container. The GrowableArray\nnever actually constructed them, instead relying on the\nzero-initialized storage from the arena allocator to be\ncorrect. We now actually construct the labels.\n\nAlso avoid StackMapStream::ComputeDexRegisterMapSize() being\npassed null references, even though unused.\n\nChange-Id: I26a46fdd406b23a3969300a67739d55528df8bf4\n" }, { "commit": "85b62f23fc6dfffe2ddd3ddfa74611666c9ff41d", "tree": "c916b01b1608558a7d8c9d100274c4c6b6706386", "parents": [ "6766eae2d91e894b4ceab9f29cc983900e7bc0c7" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Sep 09 13:15:38 2015 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Sep 17 14:41:52 2015 -0700" }, "message": "ART: Refactor intrinsics slow-paths\n\nRefactor slow paths so that there is a default implementation for\ncommon cases (only arm64 with vixl is special). Write a generic\nintrinsic slow-path that can be reused for the specific architectures.\nMove helper functions into CodeGenerator so that they are accessible.\n\nChange-Id: Ibd788dce432601c6a9f7e6f13eab31f28dcb8550\n" }, { "commit": "e6f49b47b6a4dc9c7684e4483757872cfc7ff1a1", "tree": "6a5f45136832f73138ced75fcd3c6110b74116ea", "parents": [ "23a8e35481face09183a24b9d11e505597c75ebb" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Sep 17 14:04:33 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Sep 17 14:04:33 2015 +0000" }, "message": "Revert \"Support unresolved fields in optimizing\"\nbreaks debuggable tests.\n\nThis reverts commit 23a8e35481face09183a24b9d11e505597c75ebb.\n\nChange-Id: I8e60b5c8f48525975f25d19e5e8066c1c94bd2e5\n" }, { "commit": "23a8e35481face09183a24b9d11e505597c75ebb", "tree": "bcaafb6ea001349acbf160c2cc89334fab4a38dc", "parents": [ "175dc732c80e6f2afd83209348124df349290ba8" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Sep 08 19:56:31 2015 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Sep 17 12:29:59 2015 +0100" }, "message": "Support unresolved fields in optimizing\n\nChange-Id: I9941fa5fcb6ef0a7a253c7a0b479a44a0210aad4\n" }, { "commit": "175dc732c80e6f2afd83209348124df349290ba8", "tree": "6a5f45136832f73138ced75fcd3c6110b74116ea", "parents": [ "5d01db1aa7634a012109d43e6403451b76de1daa" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Aug 25 15:42:32 2015 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Sep 17 12:29:51 2015 +0100" }, "message": "Support unresolved methods in Optimizing\n\nChange-Id: If2da02b50d2fa668cd58f134a005f1752e7746b1\n" }, { "commit": "fe157012b6d760c275d944ff83e8bea371c59b09", "tree": "a2b013dded6e25cab1d3ff5abf09c426904e142c", "parents": [ "aef880c4b872ccf1a63a3c563cb056ae117fc9c8", "ecc4366670e12b4812ef1653f7c8d52234ca1b1f" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Sep 16 14:33:16 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Sep 16 14:33:16 2015 +0000" }, "message": "Merge \"Add OptimizingCompilerStats to the CodeGenerator class.\"" }, { "commit": "fa6b93c4b69e6d7ddfa2a4ed0aff01b0608c5a3a", "tree": "3528c88e104dac8e58ae5370ab066b8b1dd0218f", "parents": [ "e295be4a95d7861f6ec179edf6565f58cad747cc" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Sep 15 10:15:55 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 16 13:21:33 2015 +0100" }, "message": "Optimizing: Tag arena allocations in HGraph.\n\nReplace GrowableArray with ArenaVector in HGraph and related\nclasses HEnvironment, HLoopInformation, HInvoke and HPhi,\nand tag allocations with new arena allocation types.\n\nChange-Id: I3d79897af405b9a1a5b98bfc372e70fe0b3bc40d\n" }, { "commit": "77a48ae01bbc5b05ca009cf09e2fcb53e4c8ff23", "tree": "780c7d6bdee784c2f8248979de348491cfb63b34", "parents": [ "659562aaf133c41b8d90ec9216c07646f0f14362" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Sep 15 12:34:04 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Sep 15 12:34:04 2015 +0000" }, "message": "Revert \"Revert \"ART: Register allocation and runtime support for try/catch\"\"\n\nThe original CL triggered b/24084144 which has been fixed\nby Ib72e12a018437c404e82f7ad414554c66a4c6f8c.\n\nThis reverts commit 659562aaf133c41b8d90ec9216c07646f0f14362.\n\nChange-Id: Id8980436172457d0fcb276349c4405f7c4110a55\n" }, { "commit": "659562aaf133c41b8d90ec9216c07646f0f14362", "tree": "be1beae390262bf2f5a17bfa44de93081a849d07", "parents": [ "b022fa1300e6d78639b3b910af0cf85c43df44bb" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Sep 14 21:26:33 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Sep 14 21:26:33 2015 +0000" }, "message": "Revert \"ART: Register allocation and runtime support for try/catch\"\n\nBreaks libcore test org.apache.harmony.security.tests.java.security.KeyStorePrivateKeyEntryTest#testGetCertificateChain. Need to investigate.\n\nThis reverts commit b022fa1300e6d78639b3b910af0cf85c43df44bb.\n\nChange-Id: Ib24d3a80064d963d273e557a93469c95f37b1f6f\n" }, { "commit": "b022fa1300e6d78639b3b910af0cf85c43df44bb", "tree": "780c7d6bdee784c2f8248979de348491cfb63b34", "parents": [ "e481c006e8b055a31d9c7cff27f4145e57e3c113" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Aug 20 17:47:48 2015 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Sep 14 20:42:58 2015 +0100" }, "message": "ART: Register allocation and runtime support for try/catch\n\nThis patch completes a series of CLs that add support for try/catch\nin the Optimizing compiler. With it, Optimizing can compile all\nmethods containing try/catch, provided they don\u0027t contain catch loops.\nFuture work will focus on improving performance of the generated code.\n\nSsaLivenessAnalysis was updated to propagate liveness information of\ninstructions live at catch blocks, and to keep location information on\ninstructions which may be caught by catch phis.\n\nRegisterAllocator was extended to spill values used after catch, and\nto allocate spill slots for catch phis. Catch phis generated for the\nsame vreg share a spill slot as the raw value must be the same.\n\nLocation builders and slow paths were updated to reflect the fact that\nthrowing an exception may not lead to escaping the method.\n\nInstruction code generators are forbidden from using of implicit null\nchecks in try blocks as live registers need to be saved before handing\nover to the runtime.\n\nCodeGenerator emits a stack map for each catch block, storing locations\nof catch phis. CodeInfo and StackMapStream recognize this new type of\nstack map and store them separate from other stack maps to avoid dex_pc\nconflicts.\n\nAfter having found the target catch block to deliver an exception to,\nQuickExceptionHandler looks up the dex register maps at the throwing\ninstruction and the catch block and copies the values over to their\nrespective locations.\n\nThe runtime-support approach was selected because it allows for the\nbest performance in the normal control-flow path, since no propagation\nof catch phi values is necessary until the exception is thrown. In\naddition, it also greatly simplifies the register allocation phase.\n\nConstantHoisting was removed from LICMTest because it instantiated\n(now abstract) HConstant and was bogus anyway (constants are always in\nthe entry block).\n\nChange-Id: Ie31038ad8e3ee0c13a5bbbbaf5f0b3e532310e4e\n" }, { "commit": "2a7c1ef95c850abae915b3a59fbafa87e6833967", "tree": "7b83b227bbaa36465f313542bba9206ac631a8fd", "parents": [ "6d889e0e5004ae4d548e6c623a1218f010d1e89b" ], "author": { "name": "Yevgeny Rouban", "email": "yevgeny.y.rouban@intel.com", "time": "Wed Jul 22 18:36:24 2015 +0600" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu Sep 03 10:38:41 2015 +0100" }, "message": "Add more dwarf debug line info for Optimized methods.\n\nOptimizing compiler generates minimum debug line info that\nis built using the dex_pc information about suspend points.\nThis is not enough for performance and debugging needs.\n\nThis CL generates additional debug line information for\ninstructions which have known dex_pc and it ensures that\nwhole call sites are mapped (as opposed to suspend points\nwhich map only one instruction past the function call).\n\nBug: 23157336\nChange-Id: I9f2b1c2038e3560847c175b8121cf9496b8b58fa\nSigned-off-by: Yevgeny Rouban \u003cyevgeny.y.rouban@intel.com\u003e\n" }, { "commit": "f9f6441c665b5ff9004d3ed55014f46d416fb1bb", "tree": "3d66a0b44e1ac927156eec6e6488de5fd52b982b", "parents": [ "fe3879e6011f629d0dd6b04fab00b9496bd4ea08" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 02 14:05:49 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Sep 02 20:16:58 2015 +0100" }, "message": "Optimizing: Tag Arena allocations with their source.\n\nThis adds the ability to track where we allocate memory\nwhen the kArenaAllocatorCountAllocations flag is turned on.\n\nAlso move some allocations from native heap to the Arena\nand remove some unnecessary utilities.\n\nBug: 23736311\nChange-Id: I1aaef3fd405d1de444fe9e618b1ce7ecef07ade3\n" }, { "commit": "ecc4366670e12b4812ef1653f7c8d52234ca1b1f", "tree": "fe7be52b1025b8122547b34d8765248d5959cd3a", "parents": [ "772cc4a2d4f978888d1b1e5a78c1c16a108260ed" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Thu Aug 13 13:33:12 2015 +0100" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Thu Aug 27 15:28:25 2015 +0100" }, "message": "Add OptimizingCompilerStats to the CodeGenerator class.\n\nJust refactoring, not yet used, but will be used by the incoming patch\nseries and future CodeGen specific stats.\n\nChange-Id: I7d20489907b82678120518a77bdab9c4cc58f937\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@linaro.org\u003e\n" }, { "commit": "4ab02352db4051d590b793f34d166a0b5c633c4a", "tree": "33082d241095549c8f6497f1409483399d6ae303", "parents": [ "772cc4a2d4f978888d1b1e5a78c1c16a108260ed" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Wed Aug 12 11:52:22 2015 +0100" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Thu Aug 27 14:39:28 2015 +0100" }, "message": "Use CodeGenerator::RecordPcInfo instead of SlowPathCode::RecordPcInfo.\n\nPart of a clean-up and refactoring series. SlowPathCode::RecordPcInfo\nis currently just a wrapper around CodGenerator::RecordPcInfo.\n\nChange-Id: Iffabef4ef37c365051130bf98a6aa6dc0a0fb254\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@linaro.org\u003e\n" }, { "commit": "581550137ee3a068a14224870e71aeee924a0646", "tree": "f62dd0d07c66a8ce4d7d994ee0e9c27bd8014bb1", "parents": [ "32f264e67afa8654a5570d38b627515fb73fc333" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 19 12:49:41 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 19 18:54:36 2015 +0100" }, "message": "Revert \"Revert \"Optimizing: Better invoke-static/-direct dispatch.\"\"\n\nFixed kCallArtMethod to use correct callee location for\nkRecursive. This combination is used when compiling with\ndebuggable flag set.\n\nThis reverts commit b2c431e80e92eb6437788cc544cee6c88c3156df.\n\nChange-Id: Idee0f2a794199ebdf24892c60f8a5dcf057db01c\n" }, { "commit": "b2c431e80e92eb6437788cc544cee6c88c3156df", "tree": "6c0ac5f843845e4b09829eb0fd9f1b3013cf4494", "parents": [ "9b688a095afbae21112df5d495487ac5231b12d0" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 19 12:45:42 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 19 12:45:42 2015 +0000" }, "message": "Revert \"Optimizing: Better invoke-static/-direct dispatch.\"\n\nReverting due to failing ndebug tests.\n\nThis reverts commit 9b688a095afbae21112df5d495487ac5231b12d0.\n\nChange-Id: Ie4f69da6609df3b7c8443412b6cf7f5c43c2c5d9\n" }, { "commit": "9b688a095afbae21112df5d495487ac5231b12d0", "tree": "e5e881d4d124803e66f1e90c1e0a0e4c90d22e13", "parents": [ "009c34cba875885d9540696f33255a9b355d6e15" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 06 14:12:42 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Aug 19 12:23:37 2015 +0100" }, "message": "Optimizing: Better invoke-static/-direct dispatch.\n\nAdd framework for different types of loading ArtMethod*\nand code pointer retrieval. Implement invoke-static and\ninvoke-direct calls the same way as Quick. Document the\ndispatch kinds in HInvokeStaticOrDirect\u0027s new enumerations\nMethodLoadKind and CodePtrLocation.\n\nPC-relative loads from dex cache arrays are used only for\nx86-64 and arm64. The implementation for other architectures\nwill be done in separate CLs.\n\nChange-Id: I468ca4d422dbd14748e1ba6b45289f0d31734d94\n" }, { "commit": "78e3ef6bc5f8aa149f2f8bf0c78ce854c2f910fa", "tree": "b8aa83bef462e20e2e7e09650e6c15d3a8d97fa6", "parents": [ "6a5037eb3340e4c981fd7de3ff45167ee5b7fc82" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Wed Aug 12 13:43:29 2015 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Wed Aug 12 13:43:29 2015 +0100" }, "message": "Add a GVN dependency \u0027GC\u0027 for garbage collection.\n\nThis will be used by incoming architecture specific optimizations. The\ndependencies must be conservative. When an HInstruction is created we\nmay not be sure whether it can trigger GC. In that case the\n\u0027ChangesGC\u0027 dependency must be set. We control at code-generation time\nthat HInstructions that can call have the \u0027ChangesGC\u0027 dependency\nset.\n\nChange-Id: Iea6a7f430009f37a9599b0a0039207049906e45d\n" }, { "commit": "8158f28b6689314213eb4dbbe14166073be71f7e", "tree": "fced445e53f639b2db42cb5a0e96d5aa04750861", "parents": [ "33407564904d2186f536107e1ca8d88f2c760c83" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Aug 07 10:26:17 2015 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Aug 07 10:26:17 2015 +0100" }, "message": "Ensure coherency of call kinds for LocationSummary.\n\nThe coherency is enforced with checks added in the `InvokeRuntime`\nhelper, that we now also use on x86 and x86_64.\n\nChange-Id: I8cb92b042f25dc3c5fd390e9c61a45b477d081f4\n" }, { "commit": "45b83aff85a8a8dfcae0da90d010fa2d7eb299a7", "tree": "ab9859f385b166831204d002878677d3cd30a031", "parents": [ "f7aa6c05a1c7d70182d43abaf3ff43b6d463eec0" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jul 06 15:12:53 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jul 06 16:20:59 2015 +0100" }, "message": "Revert \"Revert \"Fix LSRA bug with explicit register temporaries\"\"\n\nThis reverts commit a5fc140ff315dda9bc0a8e59963ed547676cd941.\n\nChange-Id: Ic322484176e55d0c7cd7250d629b9e5046006a4f\n" }, { "commit": "a5fc140ff315dda9bc0a8e59963ed547676cd941", "tree": "fd82c469e06a21bd1274dccc2d98f0613e45c51f", "parents": [ "283b8541546e7673d33d104241623d07c91cf500" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Jul 06 15:09:54 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Jul 06 15:09:54 2015 +0000" }, "message": "Revert \"Fix LSRA bug with explicit register temporaries\"\n\nregister_allocator_test32 fails.\n\nThis reverts commit 283b8541546e7673d33d104241623d07c91cf500.\n\nChange-Id: I2a46f3c68de3e8273e402102065c13797045c481\n" }, { "commit": "283b8541546e7673d33d104241623d07c91cf500", "tree": "ef57722d3b0ea62c079b014c6ca3636fb4e5d54d", "parents": [ "51f38e3adf58ba4e35b5374fb8c4b87cb3112abd" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Jul 03 08:26:41 2015 -0400" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jul 06 14:50:50 2015 +0100" }, "message": "Fix LSRA bug with explicit register temporaries\n\nA temporary with an explicit RegisterLocation, such as ESI on x86 didn\u0027t\nhave the register marked as allocated. This caused it to not be\nsaved/restored in the prologue/epilogue, causing problems in the caller\nroutine, which expected it to be saved. Found while implementing\nhttps://android-review.googlesource.com/#/c/157522/.\n\nChange-Id: I22ca2b24c2d21b1c6ab6cfb7dec26cb38034a891\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "eb7b7399dbdb5e471b8ae00a567bf4f19edd3907", "tree": "a0a488040883c14cc6cbec3186654137459d44ff", "parents": [ "8ec0e20347e13592539a8c0786b1db1735149800" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Jun 19 14:47:01 2015 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Jun 22 11:57:36 2015 +0100" }, "message": "Opt compiler: Add disassembly to the \u0027.cfg\u0027 output.\n\nThis is automatically added to the \u0027.cfg\u0027 output when using the usual\n`--dump-cfg` option.\n\nChange-Id: I864bfc3a8299c042e72e451cc7730ad8271e4deb\n" }, { "commit": "9931f319cf86c56c2855d800339a3410697633a6", "tree": "94e98f4a670d9bded4ed3fbc194c31e4c733d198", "parents": [ "edb83c606e034d76bed1331f34cdc435df47bb95" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Jun 19 14:47:01 2015 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Jun 19 14:47:01 2015 +0100" }, "message": "Opt compiler: Add a description to slow paths.\n\nChange-Id: I22160d90de3fe0ab3e6a2acc440bda8daa00e0f0\n" }, { "commit": "cf93a5cd9c978f59113d42f9f642fab5e2cc8877", "tree": "55162627fcbf2cb7913a735c7ed89e8e4b5e84d7", "parents": [ "db40ea768bd914125c3754dacb9b6f534a2e2399" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 16 11:33:24 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Jun 17 09:43:51 2015 +0100" }, "message": "Revert \"Revert \"ART: Implement literal pool for arm, fix branch fixup.\"\"\n\nThis reverts commit fbeb4aede0ddc5b1e6a5a3a40cc6266fe8518c98.\n\nAdjust block label positions. Bad catch block labels were the\nreason for the revert.\n\nChange-Id: Ia6950d639d46b9da6b07f3ade63ab46d03d63310\n" }, { "commit": "fbeb4aede0ddc5b1e6a5a3a40cc6266fe8518c98", "tree": "76ab28cf259def4dccec529df217fd760f27d2aa", "parents": [ "f38caa68cce551fb153dff37d01db518e58ed00f" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 16 11:32:01 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jun 16 11:32:01 2015 +0000" }, "message": "Revert \"ART: Implement literal pool for arm, fix branch fixup.\"\n\nThis reverts commit f38caa68cce551fb153dff37d01db518e58ed00f.\n\nChange-Id: Id88b82cc949d288cfcdb3c401b96f884b777fc40\nReason: broke the tests.\n" }, { "commit": "f38caa68cce551fb153dff37d01db518e58ed00f", "tree": "723612f20666f429b7c67321f0353d57425b1c63", "parents": [ "bd8c725e465cc7f44062745a6f2b73248f5159ed" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri May 29 15:50:18 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jun 15 15:13:28 2015 +0100" }, "message": "ART: Implement literal pool for arm, fix branch fixup.\n\nChange-Id: Iecc91418bb4ee1c957f42fefb737d0ee2ba960e7\n" }, { "commit": "bd8c725e465cc7f44062745a6f2b73248f5159ed", "tree": "76ab28cf259def4dccec529df217fd760f27d2aa", "parents": [ "6a1c92f1e4a455d802ab0d0ac47504cdd7c12f0f" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 12 10:06:32 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 12 10:28:34 2015 +0100" }, "message": "Optimizing: Remove PcInfo, use the StackMapStream instead.\n\nChange-Id: I474f3a89f6c7ee5c7accd21791b1c1e311104158\n" }, { "commit": "fd88f16100cceafbfde1b4f095f17e89444d6fa8", "tree": "fdb6d0520ca419acef9e953e74dcbd7d908bc4dd", "parents": [ "1aebdae18678403bdac078cbbe1f7dd4243c44f3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 03 11:23:52 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jun 03 11:23:52 2015 +0100" }, "message": "Factorize code for common LocationSummary of HInvoke.\n\nThis is one step forward, we could factorize more, but\nI wanted to get this out of the way first.\n\nChange-Id: I6ae411a737eebaecb64974f47af507ce0cfbae85\n" }, { "commit": "e401d146407d61eeb99f8d6176b2ac13c4df1e33", "tree": "17927f9bfe7d2041b5942c89832d55f9dedb24c5", "parents": [ "2006b7b9b8e32722bd0d640c62549d8a0ac624b6" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed Apr 22 13:56:20 2015 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Fri May 29 18:45:49 2015 -0700" }, "message": "Move mirror::ArtMethod to native\n\nOptimizing + quick tests are passing, devices boot.\n\nTODO: Test and fix bugs in mips64.\n\nSaves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS.\nSome of the savings are from removal of virtual methods and direct\nmethods object arrays.\n\nBug: 19264997\nChange-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d\n" }, { "commit": "2f9d1379fdebcdeeac52eaeff25ad5697c6b6ffb", "tree": "6fe7dd64fc17928540cac48162c4b6471fc2ab6a", "parents": [ "5969307a254fb731a464119506b2cef9404871b9", "da40309f61f98c16d7d58e4c34cc0f5eef626f93" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 18 15:25:39 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon May 18 15:25:40 2015 +0000" }, "message": "Merge \"Opt compiler: ARM64: Use ldp/stp on arm64 for slow paths.\"" }, { "commit": "17f1bc531ea2f8c1a6fac3def13dee1b901949dd", "tree": "52c00a20bd620cce4df94d297cb001dd7e7e62ce", "parents": [ "9ee371e2324d979ff7d11ac58b8201f29888c682", "b1d0f3f7e92fdcc92fe2d4c48cbb1262c005583f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 18 13:00:29 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon May 18 13:00:29 2015 +0000" }, "message": "Merge \"Support InlineInfo in StackMap.\"" }, { "commit": "b1d0f3f7e92fdcc92fe2d4c48cbb1262c005583f", "tree": "0e3ce752f82ff5d7f10d37d46bda058ca54d7e40", "parents": [ "119b21a6dfdb09d983a9e56a837fbf5c98e57096" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu May 14 12:41:51 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 18 13:00:29 2015 +0100" }, "message": "Support InlineInfo in StackMap.\n\nChange-Id: I9956091775cedc609fdae7dec1433fcb8858a477\n" }, { "commit": "e82549b14c7def0a45461183964f7e6a34cbb70c", "tree": "9293e5bf58657883923fe08ff1964e92e81e8851", "parents": [ "c3912c8a2db109a15603554fd456f56cd0a69ad0" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed May 06 10:55:34 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed May 13 16:20:48 2015 -0400" }, "message": "[optimizing] Fold HTypeConversion of constants\n\nWhile looking into optimizing long shifts on x86, I found that the\ncompiler wasn\u0027t folding HTypeConversion of constants. Add simple\nconversions of constants, taking care of float/double values\nwith NaNs and small/large values, ensuring Java conversion semantics.\n\nAdd checker cases to see that constant folding of HTypeConversion is\ndone.\n\nEnsure 422-type-conversion type conversion routiness don\u0027t get\ninlined to avoid compile time folding.\n\nChange-Id: I5a4eb376b64bc4e41bf908af5875bed312efb228\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "ec525fc30848189051b888da53ba051bc0878b78", "tree": "b2cf56e0279a584344fc07eb019da14bba2b9a6f", "parents": [ "b6829c2ee05124d64a19c7a52ada4a23f624fb91" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Apr 28 15:50:20 2015 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Apr 29 15:31:13 2015 +0100" }, "message": "Factor MoveArguments methods in Optimizing\u0027s intrinsics handlers.\n\nAlso add a precondition similar to the one present in code\ngenerators, regarding static invoke related explicit clinit\ncheck elimination in non-baseline compilations.\n\nChange-Id: I26f4dcb5d02824d7556f90b4b0c85b08b737fa53\n" }, { "commit": "2d27c8e338af7262dbd4aaa66127bb8fa1758b86", "tree": "e01e0bc57359df0bdf00c3da694c5403fb7fc9e6", "parents": [ "3adfc4bbe6c42d574bd2069d8e38a13d5ad98ccf" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Apr 28 15:48:45 2015 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Apr 29 14:09:17 2015 +0100" }, "message": "Refactor InvokeDexCallingConventionVisitor in Optimizing.\n\nChange-Id: I7ede0f59d5109644887bf5d39201d4e1bf043f34\n" }, { "commit": "3e3d73349a2de81d14e2279f60ffbd9ab3f3ac28", "tree": "69ad3378263c9a4b967cb7e27de0027264c12eb6", "parents": [ "a0ee862288b702468f8c2b6d0ad0f1c61be0b483" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Apr 28 11:00:54 2015 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Apr 28 11:00:54 2015 +0100" }, "message": "Have HInvoke instructions know their number of actual arguments.\n\nAdd an art::HInvoke::GetNumberOfArguments routine so that\nart::HInvoke and its subclasses can return the number of\nactual arguments of the called method. Use it in code\ngenerators and intrinsics handlers.\n\nConsequently, no longer remove a clinit check as last input\nof a static invoke if it is still present during baseline\ncode generation, but ensure that static invokes have no such\ncheck as last input in optimized compilations.\n\nChange-Id: Iaf9e07d1057a3b15b83d9638538c02b70211e476\n" }, { "commit": "da40309f61f98c16d7d58e4c34cc0f5eef626f93", "tree": "7525c544dc9acae0e1041757149be2eabb733dc8", "parents": [ "021190bf584662e75b269ef47cd48e2044e34fe4" ], "author": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Fri Apr 24 17:35:39 2015 +0800" }, "committer": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Fri Apr 24 17:38:13 2015 +0800" }, "message": "Opt compiler: ARM64: Use ldp/stp on arm64 for slow paths.\n\nIt should be a bit faster than load/store single registers and reduce\nthe code size.\n\nChange-Id: I67b8302adf6174b7bb728f7c2afd2c237e34ffde\n" }, { "commit": "9021825d1e73998b99c81e89c73796f6f2845471", "tree": "13e1038931cbb8bf8b8d0f4e3f51553ba1bfa983", "parents": [ "858d28ca2e73a785977f53141e775a7d4841b89d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Apr 15 11:56:51 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Apr 15 12:53:42 2015 +0100" }, "message": "Type MoveOperands.\n\nThe ParallelMoveResolver implementation needs to know if a move\nis for 64bits or not, to handle swaps correctly.\n\nBug found, and test case courtesy of Serguei I. Katkov.\n\nChange-Id: I9a0917a1cfed398c07e57ad6251aea8c9b0b8506\n" }, { "commit": "c6b4dd8980350aaf250f0185f73e9c42ec17cd57", "tree": "ef8d73e37abc04aecb430072a8bc463c73398fee", "parents": [ "dd97393aca1a3ff2abec4dc4f78d7724300971bc" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Apr 07 20:32:43 2015 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu Apr 09 16:47:50 2015 +0100" }, "message": "Implement CFI for Optimizing.\n\nCFI is necessary for stack unwinding in gdb, lldb, and libunwind.\n\nChange-Id: I1a3480e3a4a99f48bf7e6e63c4e83a80cfee40a2\n" }, { "commit": "da4d79bc9a4aeb9da7c6259ce4c9c1c3bf545eb8", "tree": "151dd61c4b6a8fd512ea4c2c862af28b02f4ed9c", "parents": [ "af87659f462ac650009fce295097cae3dabce171" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Mar 24 14:36:11 2015 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Mar 24 16:02:21 2015 +0000" }, "message": "Unify ART\u0027s various implementations of bit_cast.\n\nART had several implementations of art::bit_cast:\n\n1. one in runtime/base/casts.h, declared as:\n\n template \u003cclass Dest, class Source\u003e\n inline Dest bit_cast(const Source\u0026 source);\n\n2. another one in runtime/utils.h, declared as:\n\n template\u003ctypename U, typename V\u003e\n static inline V bit_cast(U in);\n\n3. and a third local version, in runtime/memory_region.h,\n similar to the previous one:\n\n template\u003ctypename Source, typename Destination\u003e\n static Destination MemoryRegion::local_bit_cast(Source in);\n\nThis CL removes versions 2. and 3. and changes their callers\nto use 1. instead. That version was chosen over the others\nas:\n- it was the oldest one in the code base; and\n- its syntax was closer to the standard C++ cast operators,\n as it supports the following use:\n\n bit_cast\u003cDestination\u003e(source)\n\n since `Source\u0027 can be deduced from `source\u0027.\n\nChange-Id: I7334fd5d55bf0b8a0c52cb33cfbae6894ff83633\n" }, { "commit": "522e2241f5b5f331d0aa2f8508f4c97973f7f012", "tree": "7b438281eb239aee475b1d7d4c87c13621626055", "parents": [ "94e480778b0946d1ab405ecf901e5d41ed54cc17" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Mar 17 18:48:28 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Mar 17 18:57:24 2015 +0000" }, "message": "ART: Fix condition for StoreNeedsWriteBarrier\n\nCodegen\u0027s StoreNeedsWriteBarrier assumed nulls are represented as\ninteger constants and generated a barrier when not needed. This patch\nfixes the bug.\n\nChange-Id: I79247f1009b1fe6f24dba0d57e846ecc55806d4d\n" }, { "commit": "eeefa1276e83776f08704a3db4237423b0627e20", "tree": "d7c647ca77703f3712f567704f40b00d59a125de", "parents": [ "02c0bac34c246c1bd974dbb86d292d4b52ba98e4" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 18:52:59 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Mar 16 10:48:21 2015 +0000" }, "message": "Update locations of registers after slow paths spilling.\n\nChange-Id: Id9aafcc13c1a085c17ce65d704c67b73f9de695d\n" }, { "commit": "02c0bac34c246c1bd974dbb86d292d4b52ba98e4", "tree": "83774758f02a48a0b59e042d2c6f4a4a7edf60a2", "parents": [ "ccac273186a7f624ee20d1a3e19ea34bb3fd305f", "fead4e4f397455aa31905b2982d4d861126ab89d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 18:46:44 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Mar 13 18:46:44 2015 +0000" }, "message": "Merge \"[optimizing] Don\u0027t record None locations in the stack maps.\"" }, { "commit": "fead4e4f397455aa31905b2982d4d861126ab89d", "tree": "21e4ccd99472bbf5cf1fac3bc20d0bca6f176022", "parents": [ "cc22e3946baf035c8732e9417ab132bfe663aa45" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 14:39:40 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 18:28:19 2015 +0000" }, "message": "[optimizing] Don\u0027t record None locations in the stack maps.\n\n- moved environment recording from code generator to stack map stream\n- added creation/loading factory methods for the DexRegisterMap (hides\ninternal details)\n- added new tests\n\nChange-Id: Ic8b6d044f0d8255c6759c19a41df332ef37876fe\n" }, { "commit": "a8ac9130b872c080299afacf5dcaab513d13ea87", "tree": "2bd0a2a88cbb6e7a3ae79dff84c466bed9189eb5", "parents": [ "cc22e3946baf035c8732e9417ab132bfe663aa45" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 16:36:36 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 16:47:44 2015 +0000" }, "message": "Refactor code in preparation of correct stack maps in slow path.\n\nMove the logic of saving/restoring live registers in slow path\nin the SlowPathCode method. Also add a RecordPcInfo helper to\nSlowPathCode, that will act as the placeholder of saving correct\nstack maps.\n\nChange-Id: I25c2bc7a642ef854bbc8a3eb570e5c8c8d2d030c\n" }, { "commit": "234d69d075d1608f80adb647f7935077b62b6376", "tree": "f6b68ff38722dc91bd0de2387609ee0ce950e0ce", "parents": [ "31df246d330c45f5691e226d176d0c59450f8435" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Mar 09 10:28:50 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 11 14:23:38 2015 +0000" }, "message": "Revert \"Revert \"[optimizing] Enable x86 long support.\"\"\n\nThis reverts commit 154552e666347d41d95d7619c6ee56249ff4feca.\n\nChange-Id: Idc726551c249a888b7ff5fde8508ae50e81b2e13\n" }, { "commit": "154552e666347d41d95d7619c6ee56249ff4feca", "tree": "b8bdb820be33317f23ef1d3e43d13b2b6bfb3ba5", "parents": [ "b4ba354cf8d22b261205494875cc014f18587b50" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 06 16:10:14 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 06 16:10:14 2015 +0000" }, "message": "Revert \"[optimizing] Enable x86 long support.\"\n\nFew libcore failures.\n\nThis reverts commit b4ba354cf8d22b261205494875cc014f18587b50.\n\nChange-Id: I4a28d853e730dff9b69aec9555505803cf2fcd63\n" }, { "commit": "b4ba354cf8d22b261205494875cc014f18587b50", "tree": "b6ce1e89f56f4d5adf238188df5b02fd7e2c23ac", "parents": [ "af8db2ea18135588b267fe9a0b2f7af734b906cc" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Mar 05 11:28:58 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 06 11:37:33 2015 +0000" }, "message": "[optimizing] Enable x86 long support.\n\nChange-Id: I9006972a65a1f191c45691104a960366747f9d16\n" }, { "commit": "5f8741860d465410bfed495dbb5f794590d338da", "tree": "cf295594b5b018e96959ddf474e7c8b7374006b5", "parents": [ "c670efd6ba9dbd1166bfd8c805bb6b2df7d4313a" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Mar 04 15:42:45 2015 -0500" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Mar 05 11:08:33 2015 +0000" }, "message": "[optimizing] Use callee-save registers for x86\n\nAdd ESI, EDI, EBP to available registers for non-baseline mode. Ensure\nthat they aren\u0027t used when byte addressible registers are needed.\n\nChange-Id: Ie7130d4084c2ae9cfcd1e47c26eb3e5dcac1ebd6\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "d6138ef1ea13d07ae555542f8898b30d89e9ac9a", "tree": "a8ffd5fd966512fd280bc1b3214f4e57a9e1805f", "parents": [ "92095533ac28879ddd8b44b559d700527ca12b8a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Feb 18 14:48:53 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Feb 19 14:01:18 2015 +0000" }, "message": "Ensure the graph is correctly typed.\n\nWe used to be forgiving because of HIntConstant(0) also being\nused for null. We now create a special HNullConstant for such uses.\n\nAlso, we need to run the dead phi elimination twice during ssa\nbuilding to ensure the correctness.\n\nChange-Id: If479efa3680d3358800aebb1cca692fa2d94f6e5\n" }, { "commit": "aa9b7c48069699e2aabedc6c0f62cb131fee0c73", "tree": "dafc6b514825490e65ecee4385f08f066add8c95", "parents": [ "cf3fb94a90d74361b13e7bae5aa6e0e4ae58479d" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Feb 17 15:40:09 2015 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Feb 19 12:13:09 2015 +0000" }, "message": "Have the opt. compiler set the size of \"empty\" frames to zero.\n\nThis is to mimic Quick\u0027s behavior and honor stack frame\nalignment constraints after changes introduced by Change-Id\nI0fdb31e8c631e99091b818874a558c9aa04b1628.\n\nThis issue use to make oatdump crash on oat files produced by\nthe optimized compiler (e.g.\nout/host/linux-x86/framework/x86_64/core-optimizing.oat).\n\nChange-Id: I8ba52601edb0a0993eaf8923eba55aafdce5043e\n" }, { "commit": "dc23d8318db08cb42e20f1d16dbc416798951a8b", "tree": "e7a883bb3263ccb971898df98bc58700604c1d1d", "parents": [ "e5f5953e744060fde3b4489cea4d934d529e3e32" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Feb 16 11:15:43 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Feb 18 09:53:32 2015 +0000" }, "message": "Avoid generating jmp +0.\n\nWhen a block branches to a non-following block, but blocks\nin-between do branch to it, we can avoid doing the branch.\n\nChange-Id: I9b343f662a4efc718cd4b58168f93162a24e1219\n" }, { "commit": "c0572a451944f78397619dec34a38c36c11e9d2a", "tree": "2cc6f3c6f5ad45b4b85fb62627e797fe7e7734e1", "parents": [ "0f2433bfcb02a662fe739e8e2b068abc2958e4c1" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Feb 06 14:35:25 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Feb 06 17:37:57 2015 +0000" }, "message": "Optimize leaf methods.\n\nAvoid suspend checks and stack changes when not needed.\n\nChange-Id: I0fdb31e8c631e99091b818874a558c9aa04b1628\n" }, { "commit": "4c204bafbc8d596894f8cb8ec696f5be1c6f12d8", "tree": "3608d188815a8a80e86f98611edcfe3bbaad8b17", "parents": [ "08029544d72bd9bec162956978afcb59204ea97b" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Feb 03 15:12:35 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Feb 03 17:13:17 2015 +0000" }, "message": "Use a different block order when not compiling baseline.\n\nUse the linearized order instead, as it puts blocks logically\nnext to each other in a better way. Also, it does not contain\ndead blocks.\n\nChange-Id: Ie65b56041a093c8155e6c1e06351cb36a4053505\n" }, { "commit": "4dee636d21d9ce54386cdfbb824e5eb2a9c1af0d", "tree": "ee8650cc14ec18ce0d7abf089c7d2e0dfc9e079d", "parents": [ "336247fa6deba2948f5ede1df806f48cf67c790a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 23 18:23:14 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Sat Jan 24 14:34:01 2015 +0000" }, "message": "Support callee-save registers on ARM.\n\nChange-Id: I7c519b7a828c9891b1141a8e51e12d6a8bc84118\n" }, { "commit": "d97dc40d186aec46bfd318b6a2026a98241d7e9c", "tree": "5cf0257eda25e2722a1adafb9de22690c06a56d8", "parents": [ "c698b78a17043d8898deb817098181595fbe734e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 22 13:50:01 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 23 09:20:42 2015 +0000" }, "message": "Support callee save floating point registers on x64.\n\n- Share the computation of core_spill_mask and fpu_spill_mask\n between backends.\n- Remove explicit stack overflow check support: we need to adjust\n them and since they are not tested, they will easily bitrot.\n\nChange-Id: I0b619b8de4e1bdb169ea1ae7c6ede8df0d65837a\n" }, { "commit": "988939683c26c0b1c8808fc206add6337319509a", "tree": "876e94428276547a29c27ccf17509a42dfe7cda1", "parents": [ "59add47cabce3735ccd470cd3b5dac8b112e09ab" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 12:32:32 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 18:50:25 2015 +0000" }, "message": "Enable core callee-save on x64.\n\nWill work on other architectures and FP support in other CLs.\n\nChange-Id: I8cef0343eedc7202d206f5217fdf0349035f0e4d\n" }, { "commit": "77520bca97ec44e3758510cebd0f20e3bb4584ea", "tree": "2e3be6fdc182e5cf5ae390019457af5e9c1ed242", "parents": [ "4d2c611bf17ff309abfa152e56c0b98a21ec8787" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Jan 12 18:45:46 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Jan 21 14:26:35 2015 +0000" }, "message": "Record implicit null checks at the actual invoke time.\n\nImplicitNullChecks are recorded only for instructions directly (see NB\nbelow) preceeded by NullChecks in the graph. This way we avoid recording\nredundant safepoints and minimize the code size increase.\n\nNB: ParallalelMoves might be inserted by the register allocator between\nthe NullChecks and their uses. These modify the environment and the\ncorrect action would be to reverse their modification. This will be\naddressed in a follow-up CL.\n\nChange-Id: Ie50006e5a4bd22932dcf11348f5a655d253cd898\n" }, { "commit": "cd6dffedf1bd8e6dfb3fb0c933551f9a90f7de3f", "tree": "0d83e9fdf65bded684d6e836078f253e63b7e11f", "parents": [ "12c03ac7575db242a6f35739bb459e8277115da4" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Jan 08 17:35:35 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Jan 16 17:27:03 2015 +0000" }, "message": "Add implicit null checks for the optimizing compiler\n\n- for backends: arm, arm64, x86, x86_64\n- fixed parameter passing for CodeGenerator\n- 003-omnibus-opcodes test verifies that NullPointerExceptions work as\nexpected\n\nChange-Id: I1b302acd353342504716c9169a80706cf3aba2c8\n" }, { "commit": "f85a9ca9859ad843dc03d3a2b600afbaf2e9bbdd", "tree": "a802042fa7a3a8cb820916d558e630596daaa9b4", "parents": [ "8fccea249b1a6f1469eeea42c2b2cca06ce1c70d" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Jan 13 09:20:58 2015 -0500" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Jan 15 11:21:37 2015 -0500" }, "message": "[optimizing compiler] Compute live spill size\n\nThe current stack frame calculation assumes that each live register to\nbe saved/restored has the word size of the machine. This fails for X86,\nwhere a double in an XMM register takes up 8 bytes. Change the\ncalculation to keep track of the number of core registers and number of\nfp registers to handle this distinction.\n\nThis is slightly pessimal, as the registers may not be active at the\nsame time, but the only way to handle this would be to allocate both\nclasses of registers simultaneously, or remember all the active\nintervals, matching them up and compute the size of each safepoint\ninterval.\n\nChange-Id: If7860aa319b625c214775347728cdf49a56946eb\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "11adb76fbc2dc3d8cbb6665945ff5d6733e2a8e6", "tree": "f1a5cb2ce14e1592dd557c28bd1e1ba3c5ea071e", "parents": [ "f3401f7a21c99ebec7355de27ab7bc0840f28726", "12df9ebf72255544b0147c81b1dca6644a29764e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jan 12 10:46:18 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jan 12 10:46:18 2015 +0000" }, "message": "Merge \"Move code around in OptimizingCompiler::Compile to reduce stack space.\"" }, { "commit": "12df9ebf72255544b0147c81b1dca6644a29764e", "tree": "93a47865d0c93922cfc036fba1f2490b64549912", "parents": [ "4270e74152d8a7cd979ab5a92fe2a8f84adb8a42" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 09 14:53:50 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jan 12 08:49:25 2015 +0000" }, "message": "Move code around in OptimizingCompiler::Compile to reduce stack space.\n\nAlso fix an (intentional) memory leak, by allocating the CodeGenerator\non the heap instead of the arena: they construct an Assembler object\nthat requires destruction.\n\nBUG:18787334\n\nChange-Id: I8cf0667cb70ce5b14d4ac334bd4487a562635f1b\n" }, { "commit": "840e5461a85f8908f51e7f6cd562a9129ff0e7ce", "tree": "ea8b4cbc5a0e3dea96fefcd9247e6c06b17ac518", "parents": [ "893e8881e31180721512c1b9e5ffacb03aad2e45" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 07 16:01:24 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 08 13:57:51 2015 +0000" }, "message": "Implement double and float support for arm in register allocator.\n\nThe basic approach is:\n- An instruction that needs two registers gets two intervals.\n- When allocating the low part, we also allocate the high part.\n- When splitting a low (or high) interval, we also split the high\n (or low) equivalent.\n- Allocation follows the (S/D register) requirement that low\n registers are always even and the high equivalent is low + 1.\n\nChange-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797\n" }, { "commit": "3416601a9e9be81bb7494864287fd3602d18ef13", "tree": "dd228519bfb9733aa7627b9cea81ecb28974a1ab", "parents": [ "8558375377946aabbbda6ab584e13f754590bd89" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Dec 19 17:22:29 2014 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Jan 05 16:25:59 2015 +0000" }, "message": "Look at instruction set features when generating volatiles code\n\nChange-Id: Ia882405719fdd60b63e4102af7e085f7cbe0bb2a\n" }, { "commit": "e21dc3db191df04c100620965bee4617b3b24397", "tree": "2ad762c6afb024bf95e1eced3d584649a4d57d23", "parents": [ "6d1a047b4b3f9707d4ee1cc19e99717ee021ef48" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Dec 08 16:59:43 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Dec 22 10:01:27 2014 -0800" }, "message": "ART: Swap-space in the compiler\n\nIntroduce a swap-space and corresponding allocator to transparently\nswitch native allocations to memory backed by a file.\n\nBug: 18596910\n\n(cherry picked from commit 62746d8d9c4400e4764f162b22bfb1a32be287a9)\n\nChange-Id: I131448f3907115054a592af73db86d2b9257ea33\n" }, { "commit": "5b4b898ed8725242ee6b7229b94467c3ea3054c8", "tree": "46f6df76e49f9a42dae89a6b9cf8336eae1da519", "parents": [ "6004796d6c630696127df2494dcd4f30d1367a34" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 17:45:56 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 17:45:56 2014 +0000" }, "message": "Revert \"Don\u0027t block quick callee saved registers for optimizing.\"\n\nX64 has one libcore test failing, and codegen_test on\narm is failing.\n\nThis reverts commit 6004796d6c630696127df2494dcd4f30d1367a34.\n\nChange-Id: I20e00431fa18e11ce4c0cb6fffa91977fa8e9b4f\n" }, { "commit": "6004796d6c630696127df2494dcd4f30d1367a34", "tree": "850f3e82a47061200c4e34e2c7e7a934f4769a97", "parents": [ "407d77f344cfbdbbfb50531c5f0766bc0892e2fe" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Dec 15 00:01:18 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Dec 18 14:59:50 2014 +0000" }, "message": "Don\u0027t block quick callee saved registers for optimizing.\n\nThis change builds on:\nhttps://android-review.googlesource.com/#/c/118983/\n\n- Also fix x86_64 assembler bug triggered by this change.\n- Fix (and improve) x86\u0027s backend byte register usage.\n- Fix a bug in baseline register allocator: a fixed\n out register must prevent inputs from allocating it.\n\nChange-Id: I4883862e29b4e4b6470f1823cf7eab7e7863d8ad\n" }, { "commit": "624279f3c70f9904cbaf428078981b05d3b324c0", "tree": "a81f8d8facfc28cac479a68a1042edc74c36d25b", "parents": [ "9a64a46e8edfa89402598d8650b8ebb337ba3d52" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Dec 04 11:54:28 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Dec 04 11:54:28 2014 +0000" }, "message": "Add support for float-to-long in the optimizing compiler.\n\n- Add support for the float-to-long Dex instruction in the\n optimizing compiler.\n- Add a Dex PC field to art::HTypeConversion to allow the\n x86 and ARM code generators to produce runtime calls.\n- Instruct art::CodeGenerator::RecordPcInfo not to record\n PC information for HTypeConversion instructions.\n- Add S0 to the list of ARM FPU parameter registers.\n- Have art::x86_64::X86_64Assembler::cvttss2si work with\n 64-bit operands.\n- Generate x86, x86-64 and ARM (but not ARM64) code for\n float to long HTypeConversion nodes.\n- Add related tests to test/422-type-conversion.\n\nChange-Id: I954214f0d537187883f83f7a83a1bb2dd8a21fd4\n" }, { "commit": "3f8f936aff35f29d86183d31c20597ea17e9789d", "tree": "3abc4e5f99cf7de74dbc65cafb6c045074e25381", "parents": [ "fc600dccd7797a9a10cdd457034ea8e148ccd631" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Dec 02 17:45:01 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Dec 03 12:09:28 2014 +0000" }, "message": "Add support for float-to-int in the optimizing compiler.\n\n- Add support for the float-to-int Dex instruction in the\n optimizing compiler.\n- Factor type conversion related lines in\n compiler/optimizing/builder.cc.\n- Generate x86, x86-64 and ARM (but not ARM64) code for\n float to int HTypeConversion nodes.\n- Add related tests to test/422-type-conversion.\n\nChange-Id: I2382dfc04bf394ed75f675148cfcf98216d65bc6\n" }, { "commit": "32f5b4d2c8c9b52e9522941c159577b21752d0fa", "tree": "1b30de145c7865fd8a79f17a4cfe67b1b890878c", "parents": [ "eea79dd779ba199658ada7264f8f96d776e53f19" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Tue Nov 25 20:05:46 2014 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Fri Nov 28 12:02:58 2014 +0000" }, "message": "Vixl: Update the VIXL interface to VIXL 1.7 and enable VIXL debug.\n\nThis patch updates the interface to VIXL 1.7 and enables the debug version of\nVIXL when ART is built in debug mode.\n\nChange-Id: I443fb941bec3cffefba7038f93bb972e6b7d8db5\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "6d0e483dd2e0b63e952de060738c10e2abd12ff7", "tree": "b396377926d2645f0df982f0b03c41149632a3de", "parents": [ "7c97e855ceb9b45a1cc738fb144bd3312c4e09a8" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 27 18:31:21 2014 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Nov 27 18:36:14 2014 +0000" }, "message": "Add support for long-to-float in the optimizing compiler.\n\n- Add support for the long-to-float Dex instruction in the\n optimizing compiler.\n- Have art::x86_64::X86_64Assembler::cvtsi2ss work with\n 64-bit operands.\n- Generate x86, x86-64 and ARM (but not ARM64) code for\n long to float HTypeConversion nodes.\n- Add related tests to test/422-type-conversion.\n\nChange-Id: Ic983cbeb1ae2051add40bc519a8f00a6196166c9\n" }, { "commit": "900f6eb15db5215deeea23e4e087b553b4f696f7", "tree": "ee2a824d581098147b5410539b294473f3b55c82", "parents": [ "6d541424eb0cb82ec3c2262d9c27d5fd97530cb8" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Nov 17 09:51:16 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Nov 17 09:51:16 2014 +0000" }, "message": "Fix lint error.\n\nChange-Id: Ia0fa12f2208507b6bec0581edf4345025b877580\n" } ], "next": "c1d4ec95c9dc69a7373e2eca0e69965e54d9cf03" }