)]}' { "log": [ { "commit": "3acee732f9475fbfc6b046e0044b764e7ff5ac01", "tree": "3b87f8b93c427c05e7690ea8d14577ce3e9eb502", "parents": [ "34937e2ed46fa9f56d99e9f32e0bfad050e5e798" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Wed Nov 18 13:31:08 2015 -0800" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Wed Feb 10 16:12:56 2016 -0800" }, "message": "MIPS32: peek*/poke*, and String.charAt intrinsics.\n\n- byte libcore.io.Memory.peekByte(long address)\n- short libcore.io.Memory.peekShort(long address)\n- int libcore.io.Memory.peekInt(long address)\n- long libcore.io.Memory.peekLong(long address)\n- void libcore.io.Memory.pokeByte(long address, byte value)\n- void libcore.io.Memory.pokeShort(long address, short value)\n- void libcore.io.Memory.pokeInt(long address, int value)\n- void libcore.io.Memory.pokeLong(long address, long value)\n- char java.lang.String.charAt(int index)\n\nChange-Id: I5ff30b61d87313d00f0fd3f0ee09f1c454f9c9fa\n" }, { "commit": "8cdbc2aef0ece0f3665966e793c075844b52b67d", "tree": "df2370a274b937f5d2a911019efd8fa42f59bdd6", "parents": [ "fc06b93dee031ec16272ec64fca92a0e639ae73e" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Feb 10 12:52:59 2016 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Feb 10 13:18:41 2016 +0000" }, "message": "ART/Thumb2: Disassemble SBFX/UBFX.\n\nChange-Id: I856206de81f41959f68de0653db021903dd1a210\n" }, { "commit": "3f67e692860d281858485d48a4f1f81b907f1444", "tree": "a14d3bdc1416dc3db74983d34a408a8b48cbce9c", "parents": [ "6aadaef35ea52506db61e463910c2520b702ca5e" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Fri Jan 15 14:35:12 2016 -0800" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Jan 20 20:14:00 2016 -0800" }, "message": "Implemented BitCount as an intrinsic. With unit test.\n\nRationale:\nRecognizing this important operation as an intrinsic has\nvarious advantages:\n(1) having the no-side-effects/no-throw allows for\n much more GVN/LICM/BCE.\n(2) Some architectures, like x86_64, provide direct\n support for this operation.\n\nPerformance improvements on X86_64:\nCheckersEvalBench (32-bit bitboard): 27,210KNS -\u003e 36,798KNS \u003d + 35%\nReversiEvalBench (64-bit bitboard): 52,562KNS -\u003e 89,086KNS \u003d + 69%\n\nChange-Id: I65d549b0469b7909b12c6611cdc34a8640a5751f\n" }, { "commit": "92d9060c0cdff7c726549a9d9494e5655404bed7", "tree": "22c1274193e7f1a3bd9872a2455c758394587dee", "parents": [ "376a6f3dbae7b71a6fc2c339ec416d3407277308" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Fri Dec 18 18:16:36 2015 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Jan 04 20:53:44 2016 -0800" }, "message": "MIPS: Implement HRor\n\nThis also fixes differentiation between the SRL and ROTR\ninstructions in the disassembler.\n\nChange-Id: Ie19697f8d6ea8fa4e338adde3e3cf8e4a0383eae\n" }, { "commit": "5c7aed3b9844e240cf785e5885524ac133a04396", "tree": "acc868d1478f0410fda4d0f6de3c60755aa6680e", "parents": [ "1c70f18dce7705ff70147ddebf65a97f66df8d5c" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Nov 25 19:41:54 2015 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Dec 16 15:33:30 2015 -0800" }, "message": "MIPS32: improvements in code generation (mostly 64-bit ALU ops)\n\nSpecifically:\n- Use the delay slot in InvokeRuntime() for direct entry points\n- Use kNoOutputOverlap wherever possible\n- Improve and/or/xor/add/sub with 64-bit integer constants\n- Improve 64-bit shifts by a constant amount on R2+\n- More efficient load/store of 64-bit constants (especially, 0 \u0026 +0.0)\n\nChange-Id: I86d2217c8b5b8e2a9371effc2ce38b9eec62782b\n" }, { "commit": "cd7b0ee296b0462961c63e51d99c9c323e2690df", "tree": "57a9071635389e58a8912d98b99d7e114c1efcc6", "parents": [ "0bbc1727c446ee5f4cc3c28e68127164ef379594" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Dec 03 16:46:38 2015 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Dec 15 14:29:48 2015 -0800" }, "message": "MIPS32: Fuse long and FP compare \u0026 condition in Optimizing.\n\nThis also does a minor clean-up in the assembler and\nits test.\n\nBug: 25559148\nChange-Id: I9bad3c500b592a09013b56745f70752eb284a842\n" }, { "commit": "e384547851a9d9e5d89ae5bb4c16bfd7d93cc12e", "tree": "41ba461c62b6a89253b59117a68beae05df5006f", "parents": [ "70014c8af8d3a20c2987c308788bc86671bc39e9" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Wed Nov 18 12:27:15 2015 -0800" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Mon Nov 30 17:27:36 2015 -0800" }, "message": "MIPS32: int java.lang.*.numberOfLeadingZeros\n\n- int java.lang.Integer.numberOfLeadingZeros(int)\n- int java.lang.Long.numberOfLeadingZeros(long)\n\nChange-Id: Icaf746cb807863f944ff4ebb5da6e6b2846eac58\n" }, { "commit": "7d4152f3520a3899ab57b61b884a17a2ba49a2ad", "tree": "cb57603e94688a4736798b18d157e4b325885509", "parents": [ "e033ea69bcd1f343c3cf944d78beec726faf348f" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Mon Oct 19 15:17:16 2015 -0700" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Mon Oct 19 17:26:50 2015 -0700" }, "message": "MIPS64: Disassembler support for rotate instructions.\n\nAlso, tighten the tests for recognizing the various shift commands. The\ntests, previously, would be unable to distinguish between \"shift right\nlogical\" and \"rotate right\" commands. In particular:\n\n- SRLV vs. ROTRV\n- DSRLV vs. DROTRV,\n- DSRL vs. DROTR, and\n- DSRL32 vs. DROTR32\n\nChange-Id: I7a6df8ab0d76fd3d34b1207da9915369ad84fa97\n" }, { "commit": "8c434dcc78d497e18590461700894d1c3e96013d", "tree": "6fc88cc839c0415aa90a1bbff25e93a09705d19b", "parents": [ "35ef974da353b13938fb0f3272c03070ad728431" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Aug 26 14:39:44 2015 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Tue Oct 06 16:34:25 2015 +0200" }, "message": "MIPS: Assemblers changes needed for optimizing compiler\n\nAlso add assembler tests for MIPS32.\n\nChange-Id: I3ab1fba7f3b06eb3b5058861946d675494a30775\n" }, { "commit": "e295be4a95d7861f6ec179edf6565f58cad747cc", "tree": "a994a7f270e8dd81e3bb1a704c4ee5f6ea98aa7c", "parents": [ "9ea4a93674b42f213334bb83d1982db11091b96a", "2fadd7bb67abf5bc3c5370f9508cfb5959d6e536" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Sep 16 04:21:39 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Sep 16 04:21:39 2015 +0000" }, "message": "Merge \"Additional MIPS64 instructions needed by intrinsics code.\"" }, { "commit": "bcee092d7b0cbb7181d428115ad98d25ce844061", "tree": "dab00e7f7dc19b002948020a8c2cbde665203c0e", "parents": [ "b505997b2176bd29a108cb6c33d06d4ef29ba001" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Sep 15 21:45:01 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Sep 15 21:45:01 2015 -0400" }, "message": "Add X86 bsf and rotate instructions\n\nThese are for use in new intrinsics. Bsf (Bit Scan Forward) is used in\n{Long,Integer}NumberOfTrailingZeros and the rotates are used in\n{Long,Integer}Rotate{Left,Right}.\n\nChange-Id: Icb599d7e1eec4e4ea9e5b4f0b1654c7b8d4de678\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "2fadd7bb67abf5bc3c5370f9508cfb5959d6e536", "tree": "efdfc90c1cdb4b688c0cdf6c2cf2cfe7b8121d1c", "parents": [ "010c7fd437932e0132fc4b44de6274480573ff30" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Fri Aug 14 14:56:10 2015 -0700" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Thu Sep 10 10:59:11 2015 -0700" }, "message": "Additional MIPS64 instructions needed by intrinsics code.\n\nChange-Id: If2a48300aac7a10dadf485d1765fb5bdeed975fe\n" }, { "commit": "2a5c4681ba19411c1cb22e9a7ab446dab910af1c", "tree": "883ea0c07aad9efdb7c86960056cbefd7992b2bc", "parents": [ "228b3973b2b24783c727a55fda2b4b80375f7207" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Aug 14 08:22:54 2015 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Aug 17 15:42:25 2015 -0700" }, "message": "ART: Some header cleaning around bit-utils\n\nTry to remove dependencies where they are not necessary.\n\nChange-Id: I5ff35cb17aea369bed3725b1610b50d7eb05b81e\n" }, { "commit": "8ae3ffb29489a127f2a6242c33845dac8d50e508", "tree": "cb5cc72e4a699a8ef6b044d530539c13b02604b7", "parents": [ "f67ab129d868b8355a8403a9627f96ac1e41a796" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Aug 12 21:16:41 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Aug 14 12:58:40 2015 -0400" }, "message": "Add \u0027bsr\u0027 instruction to x86 and x86_64\n\nAdd support for \u0027bsr\u0027 instruction. Add tests.\n\nChange-Id: I1cd8b30d7f3f5ee7fbeef8124cc6a31bf8ce59d5\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "b9c4bbee9364a9351376fd1fec9604e7c84778d8", "tree": "2e0fb139b709cb0bb10f4a15067c9b302eeb0dce", "parents": [ "1cad8c7c63b600a3da83bf05fb645e08ac8fafc0" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Jul 01 14:26:52 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Aug 14 11:07:57 2015 -0400" }, "message": "Add rep movsw to x86 and x86_64 instructions.\n\nAdd \u0027REP MOVSW\u0027 as a supported instruction for x86 32 and 64 bit.\n\nAdded tests.\n\nChange-Id: I1c615ac1e7fa46c48983c90f791b92be0375c8b8\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "3887c468d731420e929e6ad3acf190d5431e94fc", "tree": "67dacb849e722e33e118b97714a48e467c06cbd5", "parents": [ "6a5037eb3340e4c981fd7de3ff45167ee5b7fc82" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Aug 12 18:15:42 2015 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Aug 12 18:15:42 2015 +0100" }, "message": "Remove unnecessary `explicit` qualifiers on constructors.\n\nChange-Id: Id12e392ad50f66a6e2251a68662b7959315dc567\n" }, { "commit": "5e2c8d323fbab4db8a71041ff94b6baf3953bca9", "tree": "12030091e7359b656abe46f601aa5230b1dec880", "parents": [ "1f3f766d3b365d01f36b85dc19d40f754fa48533" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Thu Aug 06 14:49:28 2015 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Aug 06 15:32:28 2015 +0100" }, "message": "Introduce arch-specific checker tests.\n\n- The \u0027.cfg\u0027 output is now created on target.\n- Arch-specific checker tests can be created by inserting a\n suffix. For example:\n /// CHECK-START-ARM64: int Main.foo(int) register (after)\n /// CHECK-DAG: \u003c\u003cArg:i\\d+\u003e\u003e ParameterValue\n\nChange-Id: I55cdb37f8e806c7ffdde6b676c8f44ac30b59051\n" }, { "commit": "611d3395e9efc0ab8dbfa4a197fa022fbd8c7204", "tree": "9a0a3b6750caae13b963b244719e03b8cfb49c44", "parents": [ "0c9c5bbdd6976c21602b92d9b455e6fe5d769fb0" ], "author": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Fri Jul 10 11:42:06 2015 +0100" }, "committer": { "name": "Scott Wakeling", "email": "scott.wakeling@linaro.org", "time": "Tue Aug 04 09:02:56 2015 +0100" }, "message": "ARM/ARM64: Implement numberOfLeadingZeros intrinsic.\n\nChange-Id: I4042fb7a0b75140475dcfca23e8f79d310f5333b\n" }, { "commit": "124b392d35595f5a8e31e6a9dbefcff5b3ef5760", "tree": "ee2e8c02bde328814d045c98067874ad3a302136", "parents": [ "5d2ed003020feee437683b84e4ea6b8c6a5753e0" ], "author": { "name": "agicsaki", "email": "agicsaki@google.com", "time": "Thu Jul 30 13:40:13 2015 -0700" }, "committer": { "name": "agicsaki", "email": "agicsaki@google.com", "time": "Thu Jul 30 13:58:52 2015 -0700" }, "message": "Added disassembler support for repe_cmpsw instruction in x86, x86_64\n\nAlso included support for repe_cmpsl instruction. This is a follow up to\ncommit 71311f868e2 which added support for repe_cmpsw in the x86 and\nx86_64 assemblers.\n\nChange-Id: I2beac05a57341539acf96cdf77062facd031a864\n" }, { "commit": "eb7b7399dbdb5e471b8ae00a567bf4f19edd3907", "tree": "a0a488040883c14cc6cbec3186654137459d44ff", "parents": [ "8ec0e20347e13592539a8c0786b1db1735149800" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri Jun 19 14:47:01 2015 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Jun 22 11:57:36 2015 +0100" }, "message": "Opt compiler: Add disassembly to the \u0027.cfg\u0027 output.\n\nThis is automatically added to the \u0027.cfg\u0027 output when using the usual\n`--dump-cfg` option.\n\nChange-Id: I864bfc3a8299c042e72e451cc7730ad8271e4deb\n" }, { "commit": "4dda3376b71209fae07f5c3c8ac3eb4b54207aa8", "tree": "0d96a327d1b3a7e09eff178a66c0b5fb946cfc85", "parents": [ "71af6f7aab7491665fe2d6beb9af4c251a99ad56" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Jun 01 18:31:49 2015 -0700" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jun 19 15:43:58 2015 +0100" }, "message": "MIPS: Initial version of optimizing compiler for MIPS64R6.\n\nBug: 21555893\nChange-Id: I874dc356eee6ab061a32f8f3df5f8ac3a4ab7dcf\nSigned-off-by: Alexey Frunze \u003cAlexey.Frunze@imgtec.com\u003e\nSigned-off-by: Douglas Leung \u003cdouglas.leung@imgtec.com\u003e\n" }, { "commit": "12bd7210bb2f5738e33dfa3f2f1cba2e0aab4955", "tree": "ceff4c27b7d3173da61dda12b1b05e062e82e3d9", "parents": [ "2519fc40d4ae89322d28d1ff610fe81bb90fb564" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jun 04 17:50:27 2015 +0100" }, "committer": { "name": "Hiroshi Yamauchi", "email": "yamauchi@google.com", "time": "Thu Jun 04 11:26:19 2015 -0700" }, "message": "If heap poisoning is on, pass the relevant flag to LOCAL_ASFLAGS.\n\nThis change ensures assembly files honoring heap poisoning\n(notably used by stub_test) are compiled with\n-DART_HEAP_POISONING\u003d1 when this feature is turned on.\n\nBug: 21621105\nChange-Id: I13fe456cd2733a09bdfd3a9808cfd70513b14698\n" }, { "commit": "9bd88b0933a372e6a7b64b850868e6a7998567e2", "tree": "bcd275674c1234842b757ea8e100c4030f9ac6fe", "parents": [ "01cb410f4ad23135671d821ba36c269f8c82affa" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@linaro.org", "time": "Wed Apr 22 16:24:46 2015 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@linaro.org", "time": "Fri May 22 12:01:07 2015 +0100" }, "message": "ARM64: Move xSELF from x18 to x19.\n\nThis patch moves xSELF to callee saved x19 and removes support for\nETR (external thread register), previously used across native calls.\n\nChange-Id: Icee07fbb9292425947f7de33d10a0ddf98c7899b\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@linaro.org\u003e\n" }, { "commit": "e0705f51fdc71e9670a29f8c3a47168f50724b35", "tree": "4a9a2d808441843bed332b0bdad3aec0a7aa4cee", "parents": [ "64db01714f91bf255a79c0a88813641c240c9857" ], "author": { "name": "nikolay serdjuk", "email": "nikolay.y.serdjuk@intel.com", "time": "Mon Apr 27 17:52:57 2015 +0600" }, "committer": { "name": "nikolay serdjuk", "email": "nikolay.y.serdjuk@intel.com", "time": "Wed Apr 29 12:17:35 2015 +0600" }, "message": "Fix for incorrect encode and parse of PEXTRW instruction\n\nThe instruction PEXTRW encoded by sequence 66 0F 3A 15\nwas incorrectly encoded in compiler table and incorrectly\nparsed by disassembler.\n\nChange-Id: Ib4d4db923cb15a76e74f13f6b5514cb0d1cbe164\nSigned-off-by: nikolay serdjuk \u003cnikolay.y.serdjuk@intel.com\u003e\n" }, { "commit": "2cebb24bfc3247d3e9be138a3350106737455918", "tree": "d04d27d21b3c7733d784e303f01f873bb99e7770", "parents": [ "1f02f1a7b3073b8fef07770a67fbf94afad317f0" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Tue Apr 21 16:50:40 2015 -0700" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed Apr 22 12:44:27 2015 -0700" }, "message": "Replace NULL with nullptr\n\nAlso fixed some lines that were too long, and a few other minor\ndetails.\n\nChange-Id: I6efba5fb6e03eb5d0a300fddb2a75bf8e2f175cb\n" }, { "commit": "6daa9efe959b631d063eeb8d715a740c279f6c57", "tree": "099cbe401a71c3951ae9f0cfcef969c42f1c167a", "parents": [ "ee3b260e6b46982047a6c249b70bab3b077d7780", "403e0d55a3e9c18d4228d0aab31dec0c908dc73d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Apr 09 23:33:24 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 09 23:33:25 2015 +0000" }, "message": "Merge \"[MIPS] Refactoring code for disassembler\"" }, { "commit": "03fe9c80f514de61d52b65f6972d66b464a3d2fd", "tree": "fe4ac169af548b9720e0bdb5786328f9b2b56e88", "parents": [ "19361054a362957e152db65c9033408486c6af28", "bd4e6a828fc4aefea7d34a1bbedb81c560c60b6b" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Apr 09 16:40:40 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 09 16:40:40 2015 +0000" }, "message": "Merge \"Fix for incorrect parse of PEXTRW instruction\"" }, { "commit": "403e0d55a3e9c18d4228d0aab31dec0c908dc73d", "tree": "22beb87b8be836e2851bb2637446ceb47d9d4389", "parents": [ "1576be32be4a99a1cffdaaf209a3cd67e8b2f88a" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Apr 08 16:26:05 2015 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Apr 09 08:23:53 2015 +0200" }, "message": "[MIPS] Refactoring code for disassembler\n\nCode for mips64 is merged with code for mips.\n\nChange-Id: I2e3f2118c69a189787ae8e7f09adb4ee5c0d00d9\n" }, { "commit": "caff30245889729f102af87e79705893401251ef", "tree": "4793d6d6bc4adab2ad61e6876b5a24996fb365d6", "parents": [ "030d304aec321a21a4d577f3e7b4cd8e912ef901", "d2c80c419f1e16875f556de371e10257bcb59075" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Apr 07 12:38:57 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Apr 07 12:38:59 2015 +0000" }, "message": "Merge \"Fix address formatting in Mips64 disassembler.\"" }, { "commit": "030d304aec321a21a4d577f3e7b4cd8e912ef901", "tree": "540a947026809e5fc69f45d9019f4b0063f901c5", "parents": [ "47cf461b1b4125aedfef42aa5b4162f63aa8b8f3", "588e8e1359d3ef05aca27743e70d45fe57acd304" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Apr 07 12:38:16 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Apr 07 12:38:18 2015 +0000" }, "message": "Merge \"Build 32-bit version of the disassembler as well.\"" }, { "commit": "bd4e6a828fc4aefea7d34a1bbedb81c560c60b6b", "tree": "980f9eaa46f3368927e70c0122c9542b92e3368e", "parents": [ "a68a7cf8f3a6fef22d71a14350176115cb13857f" ], "author": { "name": "nikolay serdjuk", "email": "nikolay.y.serdjuk@intel.com", "time": "Fri Mar 27 16:32:27 2015 +0600" }, "committer": { "name": "nikolay serdjuk", "email": "nikolay.y.serdjuk@intel.com", "time": "Tue Apr 07 11:42:00 2015 +0600" }, "message": "Fix for incorrect parse of PEXTRW instruction\n\nThe instruction PEXTRW encoded by sequence 66 0F C5 has form:\nPEXTRW reg, xmm, imm8. Its reg is encoded in the REG part and\nxmm is encoded in the R/M part of ModR/M byte. Since the order\nis opposite to the PEXTRB and PEXTRD, we have to set \u0027load\u0027 to\ntrue and \u0027store\u0027 leave as false.\n\nChange-Id: I32c42ea005eec29f7bf969f275c36ffa0a95fa6d\n" }, { "commit": "65b798ea10dd716c1bb3dda029f9bf255435af72", "tree": "774e9901b6917989a63f07f927c3b4d8b921a013", "parents": [ "c411c6cc327d3f2b3b4d1987b07dd442205d9454" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Apr 06 09:35:22 2015 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Apr 06 14:05:07 2015 -0700" }, "message": "ART: Enable more Clang warnings\n\nChange-Id: Ie6aba02f4223b1de02530e1515c63505f37e184c\n" }, { "commit": "d2c80c419f1e16875f556de371e10257bcb59075", "tree": "4005dceed1de90663568bee06f154521b9befba6", "parents": [ "9d231cc422b7b32d00bd43ca6993b2dd7e9989ea" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Mon Apr 06 18:42:26 2015 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Mon Apr 06 18:45:58 2015 +0100" }, "message": "Fix address formatting in Mips64 disassembler.\n\nUse FormatInstructionPointer like all the other disassemblers.\nThis ensures that the \u0027absolute_addresses\u0027 option is honoured.\n\nChange-Id: I5580319cc4fad40e00f3fbbde25b142f7c689390\n" }, { "commit": "588e8e1359d3ef05aca27743e70d45fe57acd304", "tree": "aac3e447b0cc2ac23a05ad2d01b6aa5c51944cb7", "parents": [ "9d231cc422b7b32d00bd43ca6993b2dd7e9989ea" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Mon Apr 06 18:36:59 2015 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Mon Apr 06 18:36:59 2015 +0100" }, "message": "Build 32-bit version of the disassembler as well.\n\nChange-Id: I22ecc2611c3b05b1031b42abdb5bf8c245220e03\n" }, { "commit": "97597c9be7f4eb5263a80e7de4684dbfa1427e9a", "tree": "690dc04c72690a056aa84ac0206f96e5f513b3c2", "parents": [ "7775d2c1e48c0bb0880f720f3dfbd4b4d0de7c6e", "fb8d279bc011b31d0765dc7ca59afea324fd0d0c" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Apr 02 23:10:46 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 02 23:10:46 2015 +0000" }, "message": "Merge \"[optimizing] Implement x86/x86_64 math intrinsics\"" }, { "commit": "fb8d279bc011b31d0765dc7ca59afea324fd0d0c", "tree": "01b21964ce0516bda835faa15b260ac290714fe0", "parents": [ "dcff612c3a6e1427749771c4559f198fa480f709" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Mar 31 22:16:59 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Apr 01 08:45:38 2015 -0400" }, "message": "[optimizing] Implement x86/x86_64 math intrinsics\n\nImplement floor/ceil/round/RoundFloat on x86 and x86_64.\nImplement RoundDouble on x86_64.\n\nAdd support for roundss and roundsd on both architectures. Support them\nin the disassembler as well.\n\nAdd the instruction set features for x86, as the \u0027round\u0027 instruction is\nonly supported if SSE4.1 is supported.\n\nFix the tests to handle the addition of passing the instruction set\nfeatures to x86 and x86_64.\n\nAdd assembler tests for roundsd and roundss to x86_64 assembler tests.\n\nChange-Id: I9742d5930befb0bbc23f3d6c83ce0183ed9fe04f\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "82e52ce8364e3e1c644d0d3b3b4f61364bf7089a", "tree": "d26020cbee67645a46838c57747d2ba1533ba5d1", "parents": [ "ebbb1e322d8c89e69424a543faa03402e5b63673" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Thu Mar 26 16:50:57 2015 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Tue Mar 31 15:53:57 2015 +0100" }, "message": "ARM64: Update to VIXL 1.9.\n\nUpdate VIXL\u0027s interface to VIXL 1.9.\n\nChange-Id: Iebae947539cbad65488b7195aaf01de284b71cbb\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "027f0ff64c2512b9a5f1f54f3fea1bec481eb0f5", "tree": "9202535f219d7343b4c26d5c43f0bcb7c31650df", "parents": [ "6cc763c8b8157fb42dd44e1dfb84812546500dc1" ], "author": { "name": "Douglas Leung", "email": "douglas.leung@imgtec.com", "time": "Fri Feb 27 19:05:03 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Mar 20 16:51:56 2015 -0700" }, "message": "ART: Add Mips32r6 backend support\n\nAdd Mips32r6 compiler support.\n\nDon\u0027t use deprecated Mips32r2 instructions if running in Mips32r6\nmode.\n\nChange-Id: I54e689aa8c026ccb75c4af515aa2794f471c9f67\n" }, { "commit": "6ea651f0f4c7de4580beb2e887d86802c1ae0738", "tree": "fd97dcbd7301892cb785ca34aee21ad86437c3b3", "parents": [ "0e242b5cad3c0b68b72f28c1e5fd3fdd4c05bfd8" ], "author": { "name": "Maja Gagic", "email": "maja.gagic@imgtec.com", "time": "Tue Feb 24 16:55:04 2015 +0100" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Mar 06 13:05:47 2015 -0800" }, "message": "Initial support for quick compiler on MIPS64r6.\n\nChange-Id: I6f43027b84e4a98ea320cddb972d9cf39bf7c4f8\n" }, { "commit": "d737ab33a458537fca6207e9e4e25198a1511113", "tree": "5d365b8def0e9a8a87ff86c5b12559ff74e8f831", "parents": [ "65405378f4fd207dcd7d99916c2397a0da08438f" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Fri Mar 06 09:11:12 2015 +0000" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Fri Mar 06 10:45:10 2015 +0000" }, "message": "ART: Enable the use of relative addresses in the arm64 disassembler.\n\nAlso, only keep register aliases for the link register \u0027lr\u0027 and the\nthread register \u0027tr\u0027 in the arm64 disassembler. Other aliases are not\nvery important, and this way we don\u0027t have to provide aliases\nspecialised for Quick or Optimizing.\n\nChange-Id: Ie7a04910f0c587710a0cf2648203d7e89eab5d1f\n" }, { "commit": "1cd27903529ee10229fa639dc8438a75517de492", "tree": "c3689e5286876ea6deb967a79869bac5d270551f", "parents": [ "f5c224cca603ef1dba9bb80952613facc22598fa" ], "author": { "name": "Douglas Leung", "email": "douglas.leung@imgtec.com", "time": "Fri Feb 13 16:55:57 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Sat Feb 28 00:11:26 2015 +0000" }, "message": "ART: Fix Mips disassembler for some floating point instructions.\n\nChange-Id: I2b661a8dae4cd924c081df85f570007cf645769c\n" }, { "commit": "a34e760fa5cc3102ce1998f10816d380c37f43aa", "tree": "887177774ce2875a2938acc9be1cac18f74ba6be", "parents": [ "5a7c634406b2acc4917009b43dcc7def2178a79b" ], "author": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Tue Feb 03 12:03:15 2015 +0800" }, "committer": { "name": "Zheng Xu", "email": "zheng.xu@arm.com", "time": "Tue Feb 03 18:39:12 2015 +0800" }, "message": "ARM/ARM64: Dump thread offset.\n\nDump thread offset in compiler verbose log for arm32/arm64 and\noatdump for arm64.\n\nBefore patch :\n0x4e: ldr lr, [rSELF, #604]\nAfter patch :\n0x4e: ldr lr, [rSELF, #604] ; pTestSuspend\n\nChange-Id: I514e69dc44b1cf4c8a8fa085b31f93cf6a1b7c91\n" }, { "commit": "5d718dcd46a0a3c65b3635449d80947f342b1d2f", "tree": "cd7ab915520775c8ab7ea2563c0b6badc066c494", "parents": [ "e5deafe9cdd81238c3916b04301ea884c93f46b5", "031b00dc87cca699f02ce4206a9ecd99d59090dd" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Feb 02 15:57:09 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Feb 02 15:57:10 2015 +0000" }, "message": "Merge \"ART: Fix x86 disassembler\"" }, { "commit": "31fb26054349db03b3f1627fe975ed099ade69dd", "tree": "1584fbca9d5099a25ca857531b846f5b05b61de9", "parents": [ "28acb6feb50951645c37c077bd3897ea760ca322" ], "author": { "name": "Dan Albert", "email": "danalbert@google.com", "time": "Tue Sep 30 22:10:10 2014 -0700" }, "committer": { "name": "Dan Albert", "email": "danalbert@google.com", "time": "Fri Jan 30 08:57:51 2015 -0800" }, "message": "Add options for building/testing with coverage.\n\n acov --clean\n mm -B NATIVE_COVERAGE\u003dtrue ART_COVERAGE\u003dtrue test-art-host\n acov --host\n\n-B is needed because you need to be sure you rebuild *all* of ART with\ncoverage.\n\nChange-Id: Ib94ef610bd1b44dc45624877710ed733051b7a50\n" }, { "commit": "f36df544d421aa60fc4cf8a5db6356b45f97953b", "tree": "85c2a17e6ccdee567c0aee669a6b949a9eead1a8", "parents": [ "ab7f56d9b9838811cb01773e45999e2cda4aa03a" ], "author": { "name": "Dan Albert", "email": "danalbert@google.com", "time": "Thu Jan 29 13:28:13 2015 -0800" }, "committer": { "name": "Dan Albert", "email": "danalbert@google.com", "time": "Thu Jan 29 13:28:13 2015 -0800" }, "message": "Remove libcxx.mk cruft.\n\nThis is on by default now. No need to leave it in the makefiles.\n\nChange-Id: I20eab7426da4bbbf8b70ffc5b9af7b97487d885d\n" }, { "commit": "031b00dc87cca699f02ce4206a9ecd99d59090dd", "tree": "931769ccc85050469f5e5cb502021d8d35d5ae30", "parents": [ "94fc0e7be35ab1dd42c6336071ea53dfc565faee" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Jan 26 19:30:23 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jan 27 08:44:15 2015 -0800" }, "message": "ART: Fix x86 disassembler\n\nIndex 4 in SIB is valid when given Rex.x, where it denotes r12 and\nnot the invalid rsp.\n\nBug: 19149560\nChange-Id: I1a74bcbb1ccf3686e45a3df5d852a86444f9d850\n" }, { "commit": "57b34294758e9c00993913ebe43c7ee4698a5cc6", "tree": "981821619027686f83fbe00445299b0522f1df05", "parents": [ "4945bfef00ac446d9c5458e55500229d463ab4c3" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jan 14 15:45:59 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jan 15 11:32:48 2015 -0800" }, "message": "ART: Allow to compile interpret-only mips64 files\n\nInclude enough infrastructure to allow cross-compiling for mips64,\ninterpret-only. This includes the instruction-set-features, frame\nsize info and utils assembler.\n\nAlso add a disassembler for oatdump, and support in patchoat.\n\nNote: the runtime cannot run mips64, yet.\n\nChange-Id: Id106581fa76b478984741c62a8a03be0f370d992\n" }, { "commit": "8d36591d93920e7b7830c3ffee3759b561f5339e", "tree": "3217249ce513848ed93dcec981d6ed4c13c2fc60", "parents": [ "8fccea249b1a6f1469eeea42c2b2cca06ce1c70d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jan 13 11:32:32 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jan 13 11:32:32 2015 -0800" }, "message": "ART: Use jalr instead of jr for Mips\n\nUse the jalr instruction instead of jr in stubs and compiled code.\n\nChange-Id: Idacc5167a5bb0113dc2e7716e4767e5ed07b5e0b\n" }, { "commit": "55d7c18a1d76eea6d038205ccb9f2d385247f6ac", "tree": "58d55810040aaadad98717c12cae6505cf92dede", "parents": [ "3d5872eb090a04a9444b5621d381eec3846f47a3" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 05 15:17:01 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jan 06 10:59:56 2015 +0000" }, "message": "Improve Thumb disassembler for LDR/STR/PUSH/POP/BKPT.\n\nDisassemble 16-bit Thumb PUSH, POP, BKPT.\n\nClean up 32-bit load/store to handle all cases (including\npreviously unrecognized indexed load/store) in one place;\nthis also fixes LDRSH erroneously disassembled as LDRSB.\n\nRecognize more UNDEFINED instructions and other minor\ncleanup.\n\nChange-Id: Ifdd177745b70e3f774cc0469deb81191b035f51b\n" }, { "commit": "6a0b920512b72542b3f1a3d232fba7ded45ea455", "tree": "9fb25c9217e0a0c671faf507e4990b3205bbeade", "parents": [ "f610c0597e001cb1043aa4074afe25ae79a800e3" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 16 14:54:18 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Dec 16 14:54:18 2014 +0000" }, "message": "Fix crash in x86 disassembler.\n\nProbably a typo from last refactoring.\n\nChange-Id: I086a87120ca0f0dfddbe803573b0e0f79cc6d945\n" }, { "commit": "8683038c1f59bea790d8c7691e40eed7f6250e4a", "tree": "63f168876ecb6b8416082cbc141da1d478a66988", "parents": [ "29045735a55726235e5c2c5156809cdcac61d4d7" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Dec 12 21:41:29 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Dec 15 10:27:32 2014 -0800" }, "message": "ART: Do not inline elf writer debug symbols\n\nUsing Clang, this pushes the frame size of the caller across our\nlimit. Thus forbid inlining. The function is only called once per\ncompile, impact is insignificant.\n\nBug: 18738594\nChange-Id: I19c3f1168a5104ab508a8dbf9f2a8c035cb97e3c\n" }, { "commit": "e5eb7060dbacfd7c768692a8fcc4a6017d0bd1cc", "tree": "059f7f8b927e4e5fdbef2ed1f78c2a31c36699ab", "parents": [ "d1512fed4e43bba77fb21fd1b6322c22ef7c5881" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Dec 12 18:44:19 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Dec 15 08:15:57 2014 -0800" }, "message": "ART: Break up x86 disassembler main function\n\nThe function leads to large stack frames with Clang. Break out\nsome parts and use four char* variables for opcode.\n\nBug: 18733806\nChange-Id: I8bf6da6c763175d7081c4231fa5d3b6809316220\n" }, { "commit": "a262f7707330dccfb50af6345813083182b61043", "tree": "a8ab4e42654f47c9deea517f6c4e2020c62d5724", "parents": [ "3e465bec65067ebfdf662469cf85dd82cd077bdd" ], "author": { "name": "Ningsheng Jian", "email": "ningsheng.jian@arm.com", "time": "Tue Nov 25 16:48:07 2014 +0800" }, "committer": { "name": "Ningsheng Jian", "email": "ningsheng.jian@arm.com", "time": "Thu Dec 11 09:08:22 2014 +0800" }, "message": "ARM: Combine multiply accumulate operations.\n\nTry to combine integer multiply and add(sub) into a MAC operation.\nFor AArch64, also try to combine long type multiply and add(sub).\n\nChange-Id: Ic85812e941eb5a66abc355cab81a4dd16de1b66e\n" }, { "commit": "32f5b4d2c8c9b52e9522941c159577b21752d0fa", "tree": "1b30de145c7865fd8a79f17a4cfe67b1b890878c", "parents": [ "eea79dd779ba199658ada7264f8f96d776e53f19" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Tue Nov 25 20:05:46 2014 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Fri Nov 28 12:02:58 2014 +0000" }, "message": "Vixl: Update the VIXL interface to VIXL 1.7 and enable VIXL debug.\n\nThis patch updates the interface to VIXL 1.7 and enables the debug version of\nVIXL when ART is built in debug mode.\n\nChange-Id: I443fb941bec3cffefba7038f93bb972e6b7d8db5\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "834896de1c955c04d781d2bf8c53573f94ce8c3e", "tree": "7152aa7bebe9a82f7b35b3f233aacaf6e3e72ea7", "parents": [ "7b5f98e0c17785ec64eb291856cd08dcd3d19ce1", "a37d925d405be9f589ac282869a997e73414d859" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Nov 19 21:09:12 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Nov 19 21:09:15 2014 +0000" }, "message": "Merge \"Improvements to the ARM64 disassembler.\"" }, { "commit": "847c8db052fcb3c1a945a8206547c409d3eb06fc", "tree": "013b7081bf3805b25970dcd71ee18b79944fcab5", "parents": [ "195c576fbff290d4c313b67ed24ca36f2531acc4" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Nov 17 10:22:02 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Nov 17 10:22:02 2014 +0000" }, "message": "Revert \"Arm64: Use the debug version of VIXL for debug builds.\"\n\nThis reverts commit 195c576fbff290d4c313b67ed24ca36f2531acc4.\n\nChange-Id: Id992a43ae346bb4c38a6c47639b02aea838d974a\n" }, { "commit": "195c576fbff290d4c313b67ed24ca36f2531acc4", "tree": "0565c97102cc73fa989b6df822b9f2b3f1022a6c", "parents": [ "ff5298ff1640b730ee62c90ca78fc96b7ee82ec4" ], "author": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Thu Nov 13 11:14:25 2014 +0000" }, "committer": { "name": "Serban Constantinescu", "email": "serban.constantinescu@arm.com", "time": "Fri Nov 14 19:02:47 2014 +0000" }, "message": "Arm64: Use the debug version of VIXL for debug builds.\n\nThis patch builds the debug version of ART against VIXL debug. In this\nway VIXL will assert misuses of the assembler and disassembler.\n\nChange-Id: Ic4654eb20e420f23b40e96a69be452dc50770c1c\nSigned-off-by: Serban Constantinescu \u003cserban.constantinescu@arm.com\u003e\n" }, { "commit": "d582fa4ea62083a7598dded5b82dc2198b3daac7", "tree": "c76704c266ef4687eab425612ddf3fd24f93fe8d", "parents": [ "f20076ff813b8012096ff31af236d59db3c0f4e1" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Nov 05 23:46:43 2014 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Nov 13 16:17:46 2014 -0800" }, "message": "Instruction set features for ARM64, MIPS and X86.\n\nAlso, refactor how feature strings are handled so they are additive or\nsubtractive.\nMake MIPS have features for FPU 32-bit and MIPS v2. Use in the quick compiler\nrather than #ifdefs that wouldn\u0027t have worked in cross-compilation.\nAdd SIMD features for x86/x86-64 proposed in:\n https://android-review.googlesource.com/#/c/112370/\n\nBug: 18056890\n\nChange-Id: Ic88ff84a714926bd277beb74a430c5c7d5ed7666\n" }, { "commit": "677c12fe1939cad5795e7c9f4738941508c4d56f", "tree": "362b74f16c2d73d5dd66268a206ee3b4fcbe22b6", "parents": [ "abe07109e4128ea2adc26c0cb4312539bbe2913d" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Nov 07 16:58:38 2014 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Nov 07 16:58:38 2014 -0800" }, "message": "Tidy x86 disassembler\n\nChange-Id: I2f0a2851a15f5a099a5bc0249e3ea0616cdcd94e\n" }, { "commit": "277ccbd200ea43590dfc06a93ae184a765327ad0", "tree": "d89712e93da5fb2748989353c9ee071102cf3f33", "parents": [ "ad17d41841ba1fb177fb0bf175ec0e9f5e1412b3" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Nov 03 21:36:10 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Nov 04 18:40:08 2014 -0800" }, "message": "ART: More warnings\n\nEnable -Wno-conversion-null, -Wredundant-decls and -Wshadow in general,\nand -Wunused-but-set-parameter for GCC builds.\n\nChange-Id: I81bbdd762213444673c65d85edae594a523836e5\n" }, { "commit": "872dd8208f00c667af8d9e0fd07fdd0ada56d437", "tree": "2f69282f19c72ef157dad9fdc7b6c6daf8a1bf38", "parents": [ "af62cf99a1a4320157e1074c1e65c5fbb0320349" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Oct 30 11:19:14 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Oct 30 11:19:14 2014 -0700" }, "message": "Tidy and reduce ART library dependencies on the host.\n\nMove to shared rather than static libraries. Avoids capture of all static\nlibraries library dependencies.\n\nChange-Id: I2be96e92dad4ed1842d76b044745f2a2e15372eb\n" }, { "commit": "a37d925d405be9f589ac282869a997e73414d859", "tree": "f48473337f07df6fb9f505651d653ed01b9d2eda", "parents": [ "be29639a910daaa5bdb0c32be1e03477cf12babb" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Mon Oct 27 11:28:14 2014 +0000" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Wed Oct 29 09:01:14 2014 +0000" }, "message": "Improvements to the ARM64 disassembler.\n\nThis contains three changes:\n- Use register aliases in the disassembly.\n- When loading from a literal pool, show what is being loaded.\n- Disassemble using absolute addresses on ARM64.\n This ensures that addresses disassembled are coherent with instruction\n location addresses shown.\n\nExamples of disassembled instructions before and after the changes:\n\nBefore:\n movz w17, #0x471f\n ldr d9, pc+736 (addr 0x72690d50)\n\nAfter:\n movz wip1, #0x471f\n ldr d9, pc+736 (addr 0x72690d50) (-745.133)\n\nChange-Id: I72fdc160fac26f74126921834f17a581c26fd5d8" }, { "commit": "2c4257be8191c5eefde744e8965fcefc80a0a97d", "tree": "9db3e1f1c60f2df29638ba3ce9d5d5bb8b26ca2c", "parents": [ "98c271d517bc4d25fc6879b4b8e35ea93885d9e2" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Oct 24 14:20:06 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Oct 24 14:23:42 2014 -0700" }, "message": "Tidy logging code not using UNIMPLEMENTED.\n\nChange-Id: I7a79c1671a6ff8b2040887133b3e0925ef9a3cfe\n" }, { "commit": "cf7f19135f0e273f7b0136315633c2abfc715343", "tree": "ffa4d9efd9c45f4b6789acc1f534bb9327052b7e", "parents": [ "aea6888b056be21adf762e066c7f33b8939b8a06" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Oct 22 22:06:39 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Oct 22 22:21:57 2014 -0700" }, "message": "C++11 related clean-up of DISALLOW_..\n\nMove DISALLOW_COPY_AND_ASSIGN to delete functions. By no having declarations\nwith no definitions this prompts better warning messages so deal with these\nby correcting the code.\nAdd a DISALLOW_ALLOCATION and use for ValueObject and mirror::Object.\nMake X86 assembly operand types ValueObjects to fix compilation errors.\nTidy the use of iostream and ostream.\nAvoid making cutils a dependency via mutex-inl.h for tests that link against\nlibart. Push tracing dependencies into appropriate files and mutex.cc.\nx86 32-bit host symbols size is increased for libarttest, avoid copying this\nin run-test 115 by using symlinks and remove this test\u0027s higher than normal\nulimit.\nFix the RunningOnValgrind test in RosAllocSpace to not use GetHeap as it\nreturns NULL when the heap is under construction by Runtime.\n\nChange-Id: Ia246f7ac0c11f73072b30d70566a196e9b78472b\n" }, { "commit": "c7dd295a4e0cc1d15c0c96088e55a85389bade74", "tree": "0c08a2236bc9ba5d9a4dc75d4dd0ed2d76f8f1c6", "parents": [ "94e5af8602150efa95bde35cc9be9891ddf30135" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Oct 21 23:31:19 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Oct 22 12:06:23 2014 -0700" }, "message": "Tidy up logging.\n\nMove gVerboseMethods to CompilerOptions. Now \"--verbose-methods\u003d\" option to\ndex2oat rather than runtime argument \"-verbose-methods:\".\nMove ToStr and Dumpable out of logging.h, move LogMessageData into logging.cc\nexcept for a forward declaration.\nRemove ConstDumpable as Dump methods are all const (and make this so if not\ncurrently true).\nMake LogSeverity an enum and improve compile time assertions and type checking.\nRemove log_severity.h that\u0027s only used in logging.h.\nWith system headers gone from logging.h, go add to .cc files missing system\nheader includes.\nAlso, make operator new in ValueObject private for compile time instantiation\nchecking.\n\nChange-Id: I3228f614500ccc9b14b49c72b9821c8b0db3d641\n" }, { "commit": "6f3dbbadf4ce66982eb3d400e0a74cb73eb034f3", "tree": "f7a20779e4d665f948c5fbcd26dac0071dafb8d4", "parents": [ "2df6840f68dd18d7dd8dbf53f8b6181bbfdc4fc4" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Oct 14 17:41:57 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Oct 16 19:27:28 2014 -0700" }, "message": "Make ART compile with GCC -O0 again.\n\nTidy up InstructionSetFeatures so that it has a type hierarchy dependent on\narchitecture.\nAdd to instruction_set_test to warn when InstructionSetFeatures don\u0027t agree\nwith ones from system properties, AT_HWCAP and /proc/cpuinfo.\nClean-up class linker entry point logic to not return entry points but to\ntest whether the passed code is the particular entrypoint. This works around\nimage trampolines that replicate entrypoints.\nBug: 17993736\n\nChange-Id: I5f4b49e88c3b02a79f9bee04f83395146ed7be23\n" }, { "commit": "fef019c52ed7b131990d51a1e0d4444a3adf9b7b", "tree": "662ba622c502a487f49ab1658567fccf2ca2eb0f", "parents": [ "f8e28f575b1382e984edb2e8c9846a27a1bdea10" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Fri Oct 10 17:14:18 2014 +0100" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Mon Oct 13 14:12:33 2014 +0100" }, "message": "ART: ARM64: Fix instruction addresses in the disassembly.\n\nChange-Id: Ic8b6e0d5cd15e029de9bc82e0a4fc2e33d07936c\n" }, { "commit": "fc787ecd91127b2c8458afd94e5148e2ae51a1f5", "tree": "ef48c0f511ee9bf4ed85607cc4d530bace7e6cae", "parents": [ "8fa8c904f7c783204a1dc9438429391d256658da" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Oct 09 21:56:44 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Oct 09 22:22:46 2014 -0700" }, "message": "Enable -Wimplicit-fallthrough.\n\nFalling through switch cases on a clang build must now annotate the fallthrough\nwith the FALLTHROUGH_INTENDED macro.\nBug: 17731372\n\nChange-Id: I836451cd5f96b01d1ababdbf9eef677fe8fa8324\n" }, { "commit": "c8ccf68b805c92674545f63e0341ba47e8d9701c", "tree": "fb360323538cb242ebf7c5c0aca27d3a0bce0abb", "parents": [ "fcabfbe577c0fd40910b565beb681bd4b66f6c5d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Sep 29 20:07:43 2014 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Sep 29 20:13:48 2014 -0700" }, "message": "ART: Fix some -Wpedantic errors\n\nRemove extra semicolons.\n\nDollar signs in C++ identifiers are an extension.\n\nNamed variadic macros are an extension.\n\nBinary literals are a C++14 feature.\n\nEnum re-declarations are not allowed.\n\nOverflow.\n\nChange-Id: I7d16b2217b2ef2959ca69de84eaecc754517714a\n" }, { "commit": "2cbaccb67e22c0b313a9785bfc65bcb4b25d0676", "tree": "daeb766e19880b651fd9c4a719c9a07dd7d4bd0e", "parents": [ "bace0378d720a1d2938ec7f6be17e2814671d20a" ], "author": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Sun Sep 14 20:34:17 2014 -0700" }, "committer": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Tue Sep 16 12:50:08 2014 -0700" }, "message": "Avoid printing absolute addresses in oatdump\n\n- Added printing of OatClass offsets.\n- Added printing of OatMethod offsets.\n- Added bounds checks for code size size, code size, mapping table, gc map, vmap table.\n- Added sanity check of 100k for code size.\n- Added partial disassembly of questionable code.\n- Added --no-disassemble to disable disassembly.\n- Added --no-dump:vmap to disable vmap dumping.\n- Reordered OatMethod info to be in file order.\n\nBug: 15567083\n\n(cherry picked from commit 34fa79ece5b3a1940d412cd94dbdcc4225aae72f)\n\nChange-Id: I2c368f3b81af53b735149a866f3e491c9ac33fb8\n" }, { "commit": "b3a84e2f308b3ed7d17b8e96fc7adfcac36ebe77", "tree": "381fb72a42defc934f01cddab40a63299c0ba592", "parents": [ "2a09504334a3a3b4c47100197df0827cc6740433" ], "author": { "name": "Lupusoru, Razvan A", "email": "razvan.a.lupusoru@intel.com", "time": "Mon Jul 28 14:11:01 2014 -0700" }, "committer": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Wed Sep 03 10:05:40 2014 -0700" }, "message": "ART: Vectorization opcode implementation fixes\n\nThis patch fixes the implementation of the x86 vectorization opcodes.\n\nChange-Id: I0028d54a9fa6edce791b7e3a053002d076798748\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\nSigned-off-by: Udayan Banerji \u003cudayan.banerji@intel.com\u003e\nSigned-off-by: Philbert Lin \u003cphilbert.lin@intel.com\u003e\n" }, { "commit": "b5bce7cc9f1130ab4932ba8e6917c362bf871f24", "tree": "45d3b064227213da49d047c3c718e23f33b47cad", "parents": [ "3b6711faf7b0b10eaa6c48ba854160bcecd00166" ], "author": { "name": "Jean Christophe Beyler", "email": "jean.christophe.beyler@intel.com", "time": "Fri Jul 25 12:32:18 2014 -0700" }, "committer": { "name": "Chao-ying Fu", "email": "chao-ying.fu@intel.com", "time": "Tue Aug 26 11:38:04 2014 -0700" }, "message": "ART: Add non-temporal store support\n\nAdded non-temporal store support as a hint from the ME.\nAdded the implementation of the memory barrier\nextended instruction that supports non-temporal stores\nby explicitly serializing all previous store-to-memory instructions.\n\nChange-Id: I8205a92083f9725253d8ce893671a133a0b6849d\nSigned-off-by: Jean Christophe Beyler \u003cjean.christophe.beyler@intel.com\u003e\nSigned-off-by: Chao-ying Fu \u003cchao-ying.fu@intel.com\u003e\n" }, { "commit": "f40f890ae3acd7b3275355ec90e2814bba8d4fd6", "tree": "2c25813aefc9fd579a6527ccb8145fba10f5d768", "parents": [ "6324ca4706de44b75e5b8ba55473766809c4f132" ], "author": { "name": "Yixin Shou", "email": "yixin.shou@intel.com", "time": "Thu Aug 14 14:10:32 2014 -0400" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Aug 14 15:21:12 2014 -0700" }, "message": "Implement inlined shift long for 32bit\n\nAdded support for x86 inlined shift long for 32bit\n\nChange-Id: I6caef60dd7d80227c3057fd6f64b0ecb11025afa\nSigned-off-by: Yixin Shou \u003cyixin.shou@intel.com\u003e\n" }, { "commit": "76ab347dc9b89970da1451568965ee208c728c43", "tree": "9581645023d8ebceb1d9385145648f37a83cebe2", "parents": [ "99c251bbd225dd97d0deece29559a430b12a0b66" ], "author": { "name": "Junmo Park", "email": "junmoz.park@samsung.com", "time": "Mon Aug 11 21:28:16 2014 +0900" }, "committer": { "name": "Junmo Park", "email": "junmoz.park@samsung.com", "time": "Wed Aug 13 08:21:05 2014 +0900" }, "message": "Fix art build script\n\nUse ART_BUILD_HOST_NDEBUG instead of ART_BUILD_NDEBUG.\n\nChange-Id: I0ff590552f47d3354287a155b51936a7aef82f1f\nSigned-off-by: Junmo Park \u003cjunmoz.park@samsung.com\u003e\n" }, { "commit": "ec95f72490de0a7f86c35de3d00b50bb80d036a1", "tree": "d6576fb0ada8810d721f3e989e03e861e4dac03f", "parents": [ "f90283f61d6ca37abf3a9fb8447d05e79caf0160" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Wed Jul 23 12:10:07 2014 +0700" }, "committer": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Wed Jul 30 07:41:43 2014 +0000" }, "message": "ART: Correct disassembling of 64bit immediates on x86_64\n\nThe patch fixes an issue with disassembling \u0027movsxd\u0027 and \u0027movabsq\u0027\ninstructions altered with 64bit immediates: not only a REX.W prefix\nmay be prepended to these instructions.\n\nChange-Id: Ida7c7b368327a6b5cae1ff12ec00ceb0769c0a3d\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\n" }, { "commit": "3c7bb98698f77af10372cf31824d3bb115d9bf0f", "tree": "1cd4cc18babfbb16ab908f23929fa88d7678f06b", "parents": [ "98cc1e552c2ccbe5d51bc81d49e79119280f5416" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jul 23 16:04:16 2014 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Jul 28 15:44:28 2014 +0100" }, "message": "Implement array get and array put in optimizing.\n\nAlso fix a couple of assembler/disassembler issues.\n\nChange-Id: I705c8572988c1a9c4df3172b304678529636d5f6\n" }, { "commit": "79bb184ec0a661bf1276eef555dd5e20828bc528", "tree": "ccac7bc93ddca873940467ce8be7472a8b8915f5", "parents": [ "62f28f943e2da2873c7a09096c292f01a21c6478" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Tue Jul 01 18:28:43 2014 +0700" }, "committer": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Wed Jul 09 10:59:33 2014 +0000" }, "message": "ART: Correct disassembling of regs from opcodes\n\nRegisters, which are part of opcode might have 1-byte size\nor 2-byte size depending on the instruction and 66h prefix.\nThis patch makes the decoding of such instruction correct.\n\nExamples:\n - \u0027664155\u0027 should be decoded as \u0027push r13w\u0027\n (66h + REX.B)\n\n - \u002741B320\u0027 should be decoded as \u0027mov r11l, 0x20\u0027\n (byte-operand + REX.B)\n\nChange-Id: I83913e3a5f2ef03c4019c0f5eea6b11fc51ee4cc\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\n" }, { "commit": "2cfe30bd592cb6ae63bb4c28ccaf4b069d6ab565", "tree": "3eb01d4c9f9a36985f70450822c0bb3f4065db02", "parents": [ "7b68fb3b9b421d4b20c1993704986d637f1cab91", "60bfe7b3e8f00f0a8ef3f5d8716adfdf86b71f43" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Jul 09 07:44:21 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jul 08 22:56:31 2014 +0000" }, "message": "Merge \"X86 Backend support for vectorized float and byte 16x16 operations\"" }, { "commit": "60bfe7b3e8f00f0a8ef3f5d8716adfdf86b71f43", "tree": "496acee66205218843ed6bddc300ae3653794e75", "parents": [ "cecec712e1e05aab1fe3469077016320b7bf9583" ], "author": { "name": "Udayan Banerji", "email": "udayan.banerji@intel.com", "time": "Tue Jul 08 19:59:43 2014 -0700" }, "committer": { "name": "Udayan Banerji", "email": "udayan.banerji@intel.com", "time": "Tue Jul 08 19:59:43 2014 -0700" }, "message": "X86 Backend support for vectorized float and byte 16x16 operations\n\nAdd support for reserving vector registers for the duration of vector loop.\nAdd support for 16x16 multiplication, shifts, and add reduce.\n\nChanged the vectorization implementation to be able to use the dataflow\nelements for SSA recreation and fixed a few implementation details.\n\nChange-Id: I2f358f05f574fc4ab299d9497517b9906f234b98\nSigned-off-by: Jean Christophe Beyler \u003cjean.christophe.beyler@intel.com\u003e\nSigned-off-by: Olivier Come \u003colivier.come@intel.com\u003e\nSigned-off-by: Udayan Banerji \u003cudayan.banerji@intel.com\u003e\n" }, { "commit": "94f3eb0c757d0a6a145e24ef95ef7d35c091bb01", "tree": "9f9c49f151d8065633d916921071adcb1bb1f087", "parents": [ "6e524ddc060f10a493dc63fa5b6dde0deef22219" ], "author": { "name": "Serguei Katkov", "email": "serguei.i.katkov@intel.com", "time": "Tue Jun 24 13:23:17 2014 +0700" }, "committer": { "name": "Serguei Katkov", "email": "serguei.i.katkov@intel.com", "time": "Wed Jul 09 12:10:52 2014 +0700" }, "message": "x86_64: Clean-up after cmp-long fix\n\nThe patch adresses the coments from review done by Ian Rogers.\nClean-up of assembler.\n\nChange-Id: I9dbb350dfc6645f8a63d624b2b785233529459a9\nSigned-off-by: Serguei Katkov \u003cserguei.i.katkov@intel.com\u003e\n" }, { "commit": "ae2efea4582df773f80be274bdc754f732b07df3", "tree": "dab448db22bc5c01e0010cd6f78fc8017ff8f89c", "parents": [ "0da09a026fb6c612e659dc782312987b4515f472", "fb0fecffb31398adb6f74f58482f2c4aac95b9bf" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Jul 07 18:18:03 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Jul 07 17:50:18 2014 +0000" }, "message": "Merge \"ART: Add HADDPS/HADDPD/SHUFPS/SHUFPD instruction generation\"" }, { "commit": "e443a8063518fb1c5229afa3081b9fd1f6d33b16", "tree": "a4e64dea6743e787e77369241ec14f3969c43c0d", "parents": [ "ca8ff32bbb1f034b3b1f25de1fe20a9015bc87ec" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Mon Jun 30 15:44:12 2014 +0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jul 03 16:23:28 2014 -0700" }, "message": "ART: FF-opcodes are target-specific\n\nSome of the FF-opcodes\u0027 (i.e., push, call, jmp) register names\ndepend on the the target (32-bit vs 64-bit). This patch makes\nsuch opcodes target-specific.\n\nChange-Id: I4fa0b7ee5310e14f4022850ac2160c21be5d1c99\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\n" }, { "commit": "5192cbb12856b12620dc346758605baaa1469ced", "tree": "46f8727c0009978e1c15f94ea353a9fc92d2fe42", "parents": [ "7a59a24987beb52877b72b4e3f841e406413bb6d" ], "author": { "name": "Yixin Shou", "email": "yixin.shou@intel.com", "time": "Tue Jul 01 13:48:17 2014 -0400" }, "committer": { "name": "Yixin Shou", "email": "yixin.shou@intel.com", "time": "Wed Jul 02 06:40:12 2014 -0400" }, "message": "Load 64 bit constant into GPR by single instruction for 64bit mode\n\nThis patch load 64 bit constant into a register by a single movabsq\ninstruction on 64 bit bit instead of previous mov, shift, add\ninstruction sequences.\n\nChange-Id: I9d013c4f6c0b5c2e43bd125f91436263c7e6028c\nSigned-off-by: Yixin Shou \u003cyixin.shou@intel.com\u003e\n" }, { "commit": "d48b8a2bc111d30ebafdd2c661e9c0789f5c66a7", "tree": "86c281284fa1a594e9ed6ee9da349cee8c8a84fb", "parents": [ "6f9dbb8d4aa72c9b24ea45358751123b6e4c7488" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Tue Jun 24 16:40:19 2014 +0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jul 01 16:15:05 2014 -0700" }, "message": "ART: FPU instructions support in disassembler\n\nThis patch extends the disassembler with new FPU instructions:\n - fstsw\n - fucompp\n - fprem\n\nChange-Id: I9458510bc17f2b3b286edec102552f64be05147e\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\n" }, { "commit": "fb0fecffb31398adb6f74f58482f2c4aac95b9bf", "tree": "10ce833ce3912adbfbbb7b2514d483a1ae2b14bb", "parents": [ "e7248f2f1835ed194296d4f989c56251d03b834b" ], "author": { "name": "Olivier Come", "email": "olivier.come@intel.com", "time": "Fri Jun 20 11:46:16 2014 +0200" }, "committer": { "name": "Jean Christophe Beyler", "email": "jean.christophe.beyler@intel.com", "time": "Wed Jun 25 11:58:01 2014 -0700" }, "message": "ART: Add HADDPS/HADDPD/SHUFPS/SHUFPD instruction generation\n\nThe patch adds the HADDPS, HADDPD, SHUFPS, and SHUFPD instruction generation\n for X86.\n\nChange-Id: Ida105d3e57be231a5331564c1a9bc298cf176ce6\nSigned-off-by: Olivier Come \u003colivier.come@intel.com\u003e\n" }, { "commit": "afd9acc30bdd11cdd12d8209eb994cb371c65e33", "tree": "10ebfa28d992a96422fcf81eb28c98393719e9a6", "parents": [ "ba778fae99ec3b38d4f98262e6b7072bab0e9de4" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Jun 17 08:21:54 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Jun 24 16:47:31 2014 -0700" }, "message": "Multilib ART host.\n\nBuild ART for the host as a multilib project with dalvikvm32 and dalvikvm64\nrunning as 32 or 64-bit repsectfully. Note, currently multilib host builds\nare not the default, you make the so by setting BUILD_HOST_64bit\u003d1.\nExtend tests to execute in both 32 and 64-bit modes. By default both 32 and\n64-bit tests are run, add 32 or 64 to the end of a test name to run it in\npurely that flavor.\nGiven the extra spam, modify oat tests to only generate console output when\nthe test fails.\nChange the test harness so that common commands are run when a test should be\nskipped, when it passes or when it fails. Use these commands to generate a\nsummary of passing, skipped and failing tests. Tests will be skipped if they\nare known to be broken or if a test has already failed. Setting the variable\nTEST_ART_KEEP_GOING\u003dtrue will force working tests not to be skipped.\nIn this change all tests running on the optimizing compiler are marked broken\ndue to breakages running them in a multilib environment.\nBreak apart Android.common.mk into its constituent parts, along with other\npieces of reorganization.\n\nStylistic nit, we refer to make rule targets as targets thereby overloading\nthe term target. While consistent with make\u0027s terminology, its confusing with\nthe Android notion of target. I\u0027ve switched to just calling targets rules to\navoid confusion in host tests.\n\nChange-Id: I5190fc3de46800a949fbb06b3f4c258ca89ccde9\n" }, { "commit": "20dfc797dc631bf8d655dcf123f46f13332d3074", "tree": "c1d4e4f919d54f39a6d39d9d769ed5a844afb22b", "parents": [ "cbb0e809c0a4e8a4e8b7f5d3768a1864cfb381bb" ], "author": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Mon Jun 16 20:44:29 2014 -0700" }, "committer": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Tue Jun 24 09:05:27 2014 -0700" }, "message": "Add some more instruction support to optimizing compiler.\n\nThis adds a few more DEX instructions to the optimizing compiler\u0027s\nbuilder (constants, moves, if_xx, etc).\n\nAlso:\n* Changes the codegen for IF_XX instructions to use a condition\n rather than comparing a value against 0.\n* Fixes some instructions in the ARM disassembler.\n* Fixes PushList and PopList in the thumb2 assembler.\n* Switches the assembler for the optimizing compiler to thumb2\n rather than ARM.\n\nChange-Id: Iaafcd02243ccc5b03a054ef7a15285b84c06740f\n" }, { "commit": "a33720c7370d1c9e0d6569d7126bb06f2083c614", "tree": "925f6b2e03efb37148b3d52f24653656f2f84f4f", "parents": [ "b493c2983016a78de498c3a3aef302b1353dca99" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Jun 18 21:02:29 2014 -0400" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Sat Jun 21 22:28:48 2014 -0700" }, "message": "X86 Dis: Add missing mov byte; Add size suffixes\n\nYet another instruction not disassembled properly.\nAdd \u0027b\u0027, \u0027w\u0027, \u0027q\u0027 to opcodes to diffferentiate between various versions\nand make it more understandable.\n\nChange-Id: Ib794aac660bc8bc4900bfa49eab5aed682996adc\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "c5f17732d8144491c642776b6b48c85dfadf4b52", "tree": "811daa488ae5ee5dfd9b3b73bd210bc1506e5ca1", "parents": [ "08654d40cdd256f6a6c8619bf06d04d4c819714a" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Jun 05 20:48:42 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Jun 10 23:19:29 2014 -0700" }, "message": "Remove deprecated WITH_HOST_DALVIK.\n\nBug: 13751317\nFix the Mac build:\n - disable x86 selector removal that causes OS/X 10.9 kernel panics,\n - madvise don\u0027t need does zero memory on the Mac, factor into MemMap\n routine,\n - switch to the elf.h in elfutils to avoid Linux kernel dependencies,\n - we can\u0027t rely on exclusive_owner_ being available from other pthread\n libraries so maintain our own when futexes aren\u0027t available (we\n can\u0027t rely on the OS/X 10.8 hack any more),\n - fix symbol naming in assembly code,\n - work around C library differences,\n - disable backtrace in DumpNativeStack to avoid a broken libbacktrace\n dependency,\n - disable main thread signal handling logic,\n - align the stack in stub_test,\n - use $(HOST_SHLIB_SUFFIX) rather than .so in host make file variables.\n\nNot all host tests are passing on the Mac with this change. dex2oat\nworks as does running HelloWorld.\nChange-Id: I5a232aedfb2028524d49daa6397a8e60f3ee40d3\n" }, { "commit": "33ecf8d692eb192aa0ddb752d3ffe1e899e0f42e", "tree": "bf29fe047b99ff3e387c1eff5c2ea2215bdfda16", "parents": [ "6473c0ab5fe81761c34515c5049d8baf8ee1d35e" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Jun 06 15:19:45 2014 -0400" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Sun Jun 08 22:27:11 2014 -0700" }, "message": "Add Move with Sign Extend Double to disassembler\n\nI noticed another missing instruction.\n\nChange-Id: I71170496b014ac2609116eff2aeb13a13e71e263\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "88649c790cb437c130dcb6e428cddeb1ae62601c", "tree": "4952aa31790fd3016bba3c53808a2a38245aab3b", "parents": [ "32640daf36acda331719766956b25661647e2461" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Jun 04 21:20:00 2014 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Jun 05 08:29:31 2014 -0400" }, "message": "Fix X86 disassambler printing of XMM, MM registers\n\nPrinting of uint8_t is done as a char, rather than an integer.\n\nChange-Id: I996e7d7dd902695be6366ab816fea65b675c2ad9\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "f3639b2653fe4e55ce6f753b991eeb015116541d", "tree": "724905b5ebee5d32c6079c29e5e4a97a4e6c558c", "parents": [ "fd51b9fa42af1f3024d93b53ac589c52c095d7db", "122113a8a233f824c014a8fe9d90626218c4dcca" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Jun 04 15:12:40 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jun 04 15:12:40 2014 +0000" }, "message": "Merge \"ART: x86_64 disassembler improvements\"" }, { "commit": "5ca4eaace8ba513f97309bbdc2e156de4b1d648a", "tree": "3a392eb39fda9b6f6e46e05e529c85e18296bc49", "parents": [ "fa5fda3ca52678b6fa739aad46e5c6ea08ae301e" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu May 29 02:09:33 2014 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Jun 04 08:00:30 2014 -0700" }, "message": "ART: Make LOCAL_CLANG architecture dependent for the target\n\nBe selective for which target we compile with Clang. Currently we\nonly want to compile with Clang for ARM64, which means we need to\nbe careful about ARM, which is the second architecture for that.\n\nBug: 15014252\n\n(cherry picked from commit 9689e3768621130b2536564f4e00fcb6b3d25df4)\n\nChange-Id: I312e1caea08f2f3a20304b27f979d3c7b72b0a04\n" }, { "commit": "122113a8a233f824c014a8fe9d90626218c4dcca", "tree": "ba2b357fe6b2334b83f0da97118ba91fcaee1af6", "parents": [ "57795db7d44bcd6d106481fa192691400b2358c8" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Fri May 30 17:56:23 2014 +0700" }, "committer": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Wed Jun 04 12:21:28 2014 +0700" }, "message": "ART: x86_64 disassembler improvements\n\nThis patch\n (a) enables full support of 64bit extended regs r8-r15,\n including 8bit r8l-r15l, 16bit r8w-r15w and also\n 32bit r8d-r15d\n (b) fixes an issue with decoding reg from ModRM byte\n (REX.B should be used)\n (c) fixes an issue with decoding regs from SIB byte\n (regs that contain addr are target-specific)\n\nChange-Id: I6bf3d7102780907b1cbe2a46927352ac0b506295\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\n" }, { "commit": "67d18be2a5bddbd8ee9ef144b34ccaeba08a1db2", "tree": "77a7d6e731f63ec95005e52261585d1b93324929", "parents": [ "b413cd79c46b7c48ac763cb8152a55a4ed60fe9f" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri May 30 15:05:09 2014 -0400" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri May 30 13:04:11 2014 -0700" }, "message": "Support disassembly of 16-bit immediates\n\nChange-Id: I66f5ce93077241204311e52c547599f5287bae04\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "fe94578b63380f464c3abd5c156b7b31d068db6c", "tree": "d5b400472581859591e9f6794fb07b3ba9cb47c0", "parents": [ "8c895b3385ed96a0b040c35222c0338058895d49" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu May 22 09:52:36 2014 -0400" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Sat May 24 07:33:52 2014 -0700" }, "message": "Implement all vector instructions for X86\n\nAdd X86 code generation for the vector operations. Added support for\nX86 disassembler for the new instructions.\n\nChange-Id: I72b48f5efa3a516a16bb1dd4bdb5c9270a8db53a\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "2a0e954ecf7c60e6ec62d64b9382cc4ee447e224", "tree": "37d22f5d9e221ecd8a68c41d430e7b21fa3f54d1", "parents": [ "299d2a2b200a94daa49c4727fd679f4461c083c7" ], "author": { "name": "Dan Albert", "email": "danalbert@google.com", "time": "Wed May 21 14:55:02 2014 -0700" }, "committer": { "name": "Dan Albert", "email": "danalbert@google.com", "time": "Wed May 21 19:47:17 2014 -0700" }, "message": "Move art host to libc++\n\nChange-Id: Ia51a4fdfdbae7377130a43c401c2d8d241671d1e\n" }, { "commit": "700a402244a1a423da4f3ba8032459f4b65fa18f", "tree": "4c22fcda04d271bd55a37aff30650214af17a90c", "parents": [ "047c11adcbcbc0bcf210defdfcbada763961ffee" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon May 19 16:49:03 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon May 19 22:27:39 2014 -0700" }, "message": "Now we have a proper C++ library, use std::unique_ptr.\n\nAlso remove the Android.libcxx.mk and other bits of stlport compatibility\nmechanics.\n\nChange-Id: Icdf7188ba3c79cdf5617672c1cfd0a68ae596a61\n" }, { "commit": "ff093b31d75658c3404f9b51ee45760f346f06d9", "tree": "16a11ff5a78862defcc169b0af2901360a57ab6a", "parents": [ "b3016551e5f264264dbb633a1ddf03ac97f9c66c" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Apr 30 19:04:27 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu May 01 08:31:01 2014 -0700" }, "message": "Fix a few 64-bit compilation of 32-bit code issues.\n\nBug: 13423943\n\nChange-Id: I939389413af0a68c0d95b23cd598b7c42afa4383\n" }, { "commit": "e8861b30ac8b2b1ca49386f9c9218f1d6fedc511", "tree": "70ec1c5dc2b917211b9bf0428f2806694f725744", "parents": [ "3f4dcdf6c99f90a2301304d26ce29dc637b4be7f" ], "author": { "name": "Vladimir Kostyukov", "email": "vladimir.kostyukov@intel.com", "time": "Fri Apr 18 17:06:15 2014 +0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Apr 25 10:42:13 2014 -0700" }, "message": "ART: Enables x86_64 disassembly\n\nThis patch\n (a) cuts a REX prefix from the instruction and\n (b) adds missed 32bit disp to instructions with ModR/M and SIB bytes.\n\nChange-Id: I2674678224ca27746b33d4006ed38d497972309f\nSigned-off-by: Vladimir Kostyukov \u003cvladimir.kostyukov@intel.com\u003e\n" } ], "next": "96a4f29350bf279d48bff70e21e3264cce216683" }