)]}'
{
  "log": [
    {
      "commit": "e1811ed6b57a54dc8ebd327e4bd2c4422092a3a0",
      "tree": "e3ce48e66190c11a8b5342f4ec0d1046ba28d788",
      "parents": [
        "7113885fcd983b33ee1e350865d21517d6297843"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu Apr 27 16:50:47 2017 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu May 11 10:06:04 2017 +0100"
      },
      "message": "ARM64: Share address computation across SIMD LDRs/STRs.\n\nFor array accesses the element address has the following structure:\nAddress \u003d CONST_OFFSET + base_addr + index \u003c\u003c ELEM_SHIFT\n\nTaking into account ARM64 LDR/STR addressing modes address part\n(CONST_OFFSET + index \u003c\u003c ELEM_SHIFT) can be shared across array\naccess with the same data type and index.\n\nFor example, for the following loop 5 accesses can share address\ncomputation:\n\nvoid foo(int[] a, int[] b, int[] c) {\n  for (i...) {\n    a[i] \u003d a[i] + 5;\n    b[i] \u003d b[i] + c[i];\n  }\n}\n\nTest: test-art-host, test-art-target\n\nChange-Id: I46af3b4e4a55004336672cdba3296b7622d815ca\n"
    },
    {
      "commit": "f34dd206d0073fb3949be872224420a8488f551f",
      "tree": "b24b451af6efdd9f67c4cbd5c37ebb4ec6a4aaad",
      "parents": [
        "1f56cb5c594f5757085820b1042988d10f02bb0b"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Mon Apr 10 17:41:46 2017 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu Apr 20 00:21:29 2017 +0100"
      },
      "message": "ARM64: Support MultiplyAccumulate for SIMD.\n\nTest: test-art-host, test-art-target.\n\nChange-Id: I06af8415e15352d09d176cae828163cbe99ae7a7\n"
    },
    {
      "commit": "74234daabb28a4b9c804bf8bf908e7334bd4d400",
      "tree": "0b60cb00ab117c1a9a4b92983514962198b548bf",
      "parents": [
        "a7e9bfafeb64b1142433a41b05ddc263cadc61e3"
      ],
      "author": {
        "name": "Anton Kirilov",
        "email": "anton.kirilov@linaro.org",
        "time": "Fri Jan 13 14:42:47 2017 +0000"
      },
      "committer": {
        "name": "Anton Kirilov",
        "email": "anton.kirilov@linaro.org",
        "time": "Fri Feb 17 14:59:27 2017 +0000"
      },
      "message": "ARM: Merge data-processing instructions and shifts/(un)signed extensions\n\nThis commit mirrors the work that has already been done for ARM64.\n\nTest: m test-art-target-run-test-551-checker-shifter-operand\nChange-Id: Iec8c1563b035f40f0e18dcffde28d91dc21922f8\n"
    },
    {
      "commit": "328429ff48d06e2cad4ebdd3568ab06de916a10a",
      "tree": "6290ac8afc3e93488382727f6765f548a2cfff04",
      "parents": [
        "79e73245140f4115039a7284b3797d701f368fe6"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Wed Jul 06 16:23:04 2016 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Jul 21 09:16:43 2016 +0000"
      },
      "message": "ARM: Port instr simplification of array accesses.\n\nAfter changing the addressing mode for array accesses (in\nhttps://android-review.googlesource.com/248406) the \u0027add\u0027\ninstruction that calculates the base address for the array can be\nshared across accesses to the same array.\n\nBefore https://android-review.googlesource.com/248406:\n    add IP, r[Array], r[Index0], LSL #2\n    ldr r0, [IP, #12]\n    add IP, r[Array], r[Index1], LSL #2\n    ldr r0, [IP, #12]\n\nBefore this CL:\n    add IP. r[Array], #12\n    ldr r0, [IP, r[Index0], LSL #2]\n    add IP. r[Array], #12\n    ldr r0, [IP, r[Index1], LSL #2]\n\nAfter this CL:\n    add IP. r[Array], #12\n    ldr r0, [IP, r[Index0], LSL #2]\n    ldr r0, [IP, r[Index1], LSL #2]\n\nLink to the original optimization:\n    https://android-review.googlesource.com/#/c/127310/\n\nTest: Run ART test suite on Nexus 6.\nChange-Id: Iee26f9a0a7ca46abb90e3f60d19d22dc8dee4d8f\n"
    },
    {
      "commit": "7fc6350f6f1ab04b52b9cd7542e0790528296cbe",
      "tree": "26a33ef7bb2e49a9b7c7d9436194a92cb447b317",
      "parents": [
        "b7f257f353b1eb2db2732939a0404c118316891d"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Tue Feb 09 17:15:29 2016 +0000"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Fri Mar 11 12:49:27 2016 +0000"
      },
      "message": "Integrate BitwiseNegated into shared framework.\n\nShare implementation between arm and arm64.\n\nChange-Id: I0dd12e772cb23b4c181fd0b1e2a447470b1d8702\n"
    },
    {
      "commit": "4a0dad67867f389e01a5a6c0fe381d210f687c0d",
      "tree": "91f1e70f4a2d0bd32aa7eb51e546f5330d72f772",
      "parents": [
        "d15ede2df7d157ea5480614fd18c2bf0d37a6c2a"
      ],
      "author": {
        "name": "Artem Udovichenko",
        "email": "artem.u@samsung.com",
        "time": "Tue Jan 26 12:28:31 2016 +0300"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Feb 25 10:14:30 2016 +0000"
      },
      "message": "Revert \"Revert \"ARM/ARM64: Extend support of instruction combining.\"\"\n\nThis reverts commit 6b5afdd144d2bb3bf994240797834b5666b2cf98.\n\nChange-Id: Ic27a10f02e21109503edd64e6d73d1bb0c6a8ac6\n"
    },
    {
      "commit": "6b5afdd144d2bb3bf994240797834b5666b2cf98",
      "tree": "d536cd7b3aaf55c563e82c2c522521a91b2bb953",
      "parents": [
        "debeb98aaa8950caf1a19df490f2ac9bf563075b"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jan 22 09:31:52 2016 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jan 22 09:31:52 2016 +0000"
      },
      "message": "Revert \"ARM/ARM64: Extend support of instruction combining.\"\n\nThe test fails its checker parts.\n\nThis reverts commit debeb98aaa8950caf1a19df490f2ac9bf563075b.\n\nChange-Id: I49929e15950c7814da6c411ecd2b640d12de80df\n"
    },
    {
      "commit": "debeb98aaa8950caf1a19df490f2ac9bf563075b",
      "tree": "b2a7a7cc6fb2f56d4bcc6cecaa80035668f38dc4",
      "parents": [
        "6aadaef35ea52506db61e463910c2520b702ca5e"
      ],
      "author": {
        "name": "Ilmir Usmanov",
        "email": "i.usmanov@samsung.com",
        "time": "Fri Dec 11 11:39:44 2015 +0300"
      },
      "committer": {
        "name": "Artem Udovichenko",
        "email": "artem.u@samsung.com",
        "time": "Thu Jan 21 11:07:38 2016 +0300"
      },
      "message": "ARM/ARM64: Extend support of instruction combining.\n\nCombine multiply instructions in the following way:\nARM64:\nMUL/NEG -\u003e MNEG\nARM32 (32-bit integers only):\nMUL/ADD -\u003e MLA\nMUL/SUB -\u003e MLS\n\nChange-Id: If20f2d8fb060145ab6fbceeb5a8f1a3d02e0ecdb\n"
    }
  ]
}