)]}' { "log": [ { "commit": "1109fb3cacc8bb667979780c2b4b12ce5bb64549", "tree": "00b38dbb7d7cf173bb376ed0b87d015dc09a6559", "parents": [ "cde8e5da3e774a2494b051043130c0495eca09ef" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Apr 07 20:21:06 2015 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Apr 08 15:08:07 2015 +0100" }, "message": "Implement CFI for Quick.\n\nCFI is necessary for stack unwinding in gdb, lldb, and libunwind.\n\nChange-Id: Ic3b84c9dc91c4bae80e27cda02190f3274e95ae8\n" }, { "commit": "cde8e5da3e774a2494b051043130c0495eca09ef", "tree": "634d8ae50583df30fd743ee1e1e6c97591e95484", "parents": [ "8635e1886f3624154c076cf40cbf182c74e2e0e3", "8c57831b2b07185ee1986b9af68a351e1ca584c3" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Apr 08 12:30:18 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Apr 08 12:30:19 2015 +0000" }, "message": "Merge \"Remove the old CFI infrastructure.\"" }, { "commit": "8c57831b2b07185ee1986b9af68a351e1ca584c3", "tree": "862c57e602dff367ca141d3a86235b48bf47bf17", "parents": [ "caff30245889729f102af87e79705893401251ef" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Apr 07 19:46:22 2015 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Apr 07 20:07:58 2015 +0100" }, "message": "Remove the old CFI infrastructure.\n\nChange-Id: I12a17a8a1c39ffccaa499c328ebac36e4d74dc4e\n" }, { "commit": "cc23481b66fd1f2b459d82da4852073e32f033aa", "tree": "f2192d5fff8591e4e5b87d04fa6fce770f7e7f08", "parents": [ "e5c76c515a481074aaa6b869aa16490a47ba98bc" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Apr 07 09:36:09 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Apr 07 19:13:40 2015 +0100" }, "message": "Promote pointer to dex cache arrays on arm.\n\nDo the use-count analysis on temps (ArtMethod* and the new\nPC-relative temp) in Mir2Lir, rather than MIRGraph. MIRGraph\nisn\u0027t really supposed to know how the ArtMethod* is used by\nthe backend.\n\nChange-Id: Iaf56a46ae203eca86281b02b54f39a80fe5cc2dd\n" }, { "commit": "b207e1473dda1730604a28db2b4fa52f2998aeae", "tree": "f11edd5afaab57f733f18cc6cba66cf84d8a6571", "parents": [ "3795e94a8bd42a1de3a98935f45399f1805a9f6e" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Apr 02 21:25:21 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Apr 02 21:36:48 2015 +0100" }, "message": "Pass linker patches around as const.\n\nChange-Id: I0eabd713d29475db9eb6e186f331dbfb00e0cf6b\n" }, { "commit": "6f7158927fee233255f8e96719c374694b10cad3", "tree": "518cef41f4cd9c3119879eb463aa4b67af5f6ff8", "parents": [ "ef3456f872539df65c4c88ca346713f74366d803" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Mon Mar 30 14:21:42 2015 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Wed Apr 01 12:57:10 2015 +0100" }, "message": "Write .debug_line section using the new DWARF library.\n\nAlso simplify dex to java mapping and handle mapping\nin prologues and epilogues.\n\nChange-Id: I410f06024580f2a8788f2c93fe9bca132805029a\n" }, { "commit": "20f85597828194c12be10d3a927999def066555e", "tree": "486c10dca0811b036a0cd5f80c02650ac43b11a5", "parents": [ "7d8c6776d7bdcc04411154aa215ba5909939192a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Mar 19 10:07:02 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Mar 31 08:56:17 2015 +0100" }, "message": "Fixed layout for dex caches in boot image.\n\nDefine a fixed layout for dex cache arrays (type, method,\nstring and field arrays) for dex caches in the boot image.\nThis gives those arrays fixed offsets from the boot image\ncode and allows PC-relative addressing of their elements.\n\nUse the PC-relative load on arm64 for relevant instructions,\ni.e. invoke-static, invoke-direct, const-string,\nconst-class, check-cast and instance-of. This reduces the\narm64 boot.oat on Nexus 9 by 1.1MiB.\n\nThis CL provides the infrastructure and shows on the arm64\nthe gains that we can achieve by having fixed dex cache\narrays\u0027 layout. To fully use this for the boot images, we\nneed to implement the PC-relative addressing for other\narchitectures. To achieve similar gains for apps, we need\nto move the dex cache arrays to a .bss section of the oat\nfile. These changes will be implemented in subsequent CLs.\n\n(Also remove some compiler_driver.h dependencies to reduce\nincremental build times.)\n\nChange-Id: Ib1859fa4452d01d983fd92ae22b611f45a85d69b\n" }, { "commit": "356a1811f2f79d98194475fdbfb5f6b7768455b5", "tree": "d3b39e9b1f2d170386a71c5d0024f70579e43bae", "parents": [ "03910065cd025ecb07781b85c2240be69c202d75" ], "author": { "name": "Pavel Vyssotski", "email": "pavel.n.vyssotski@intel.com", "time": "Fri Mar 27 15:23:02 2015 +0600" }, "committer": { "name": "Pavel Vyssotski", "email": "pavel.n.vyssotski@intel.com", "time": "Fri Mar 27 15:40:11 2015 +0600" }, "message": "Quick: Finding upper half of kMirOpCheckPart2 should passthough empty blocks\n\nMir2Lir::InitReferenceVRegs trying to find throwing instruction for\nkMirOpCheckPart2 should traverse possible empty blocks which compiler\noptimizations could generate between them.\n\nChange-Id: I2ab29dd36635fd4c4ef2dd81b51e571e206775e6\nSigned-off-by: Pavel Vyssotski \u003cpavel.n.vyssotski@intel.com\u003e\n" }, { "commit": "6e07183e822a32856da9eb60006989496e06a9cc", "tree": "82f093c739c0806c2bbe9dc97780a0b919b72802", "parents": [ "94ead7673f90a8199d926fe161d7d021202f0aa7" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Mar 25 11:13:39 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Mar 25 11:13:39 2015 +0000" }, "message": "Quick: Fix \"select\" pattern to update data used for GC maps.\n\nFollow-up to\n https://android-review.googlesource.com/143222\n\nChange-Id: I1c12af9a19f76e64fd209f6cc2eaec5587b3083b\n" }, { "commit": "f6737f7ed741b15cfd60c2530dab69f897540735", "tree": "120c8ea6fe55ba3a8e2f9cf6eba041ef98a9b51f", "parents": [ "274395fe6649d83d723c4b912a46291b2987efd6" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Mar 23 17:05:14 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Mar 24 11:46:21 2015 +0000" }, "message": "Quick: Clean up Mir2Lir codegen.\n\nClean up WrapPointer()/UnwrapPointer() and OpPcRelLoad().\n\nChange-Id: I1a91f01e1e779599c77f3f6efcac2a6ad34629cf\n" }, { "commit": "767c752fddc64e280dba507457e4f06002b5f678", "tree": "3c7ee2333290b6d634e3cb5e0ab49d6cbee9c096", "parents": [ "0b40ecf156e309aa17c72a28cd1b0237dbfb8746" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Mar 20 12:47:30 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Mar 20 21:58:07 2015 +0000" }, "message": "Quick: Create GC map based on compiler data.\n\nThe Quick compiler and verifier sometimes disagree on dalvik\nregister types (fp/core/ref) for 0/null constants and merged\nregisters involving 0/null constants. Since the verifier is\nmore lenient it can mark a register as a reference for GC\nwhere Quick considers it a floating point register or a dead\nregister (which would have a ref/fp conflict if not dead).\nIf the compiler used an fp register to hold the zero value,\nthe core register or stack location used by GC based on the\nverifier data can hold an invalid value.\n\nPreviously, as a workaround we stored the fp zero value also\nin the stack location or core register where GC would look\nfor it. This wasn\u0027t precise and may have missed some cases.\n\nTo fix this properly, we now generate GC maps based on the\ncompiler\u0027s notion of references if register promotion is\nenabled.\n\nBug: https://code.google.com/p/android/issues/detail?id\u003d147187\nChange-Id: Id3a2f863b16bdb8969df7004c868773084aec421\n" }, { "commit": "6ea651f0f4c7de4580beb2e887d86802c1ae0738", "tree": "fd97dcbd7301892cb785ca34aee21ad86437c3b3", "parents": [ "0e242b5cad3c0b68b72f28c1e5fd3fdd4c05bfd8" ], "author": { "name": "Maja Gagic", "email": "maja.gagic@imgtec.com", "time": "Tue Feb 24 16:55:04 2015 +0100" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Mar 06 13:05:47 2015 -0800" }, "message": "Initial support for quick compiler on MIPS64r6.\n\nChange-Id: I6f43027b84e4a98ea320cddb972d9cf39bf7c4f8\n" }, { "commit": "d37f91902048b23ad5fe5b20aba0ebc92e0b4896", "tree": "47dadafacc0ba3c56293713cfb6f43606ea959b9", "parents": [ "b8fef11aef3732f97ef9192e14c49d4993c26e22" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Mar 04 14:00:56 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Mar 04 14:55:17 2015 -0800" }, "message": "ART: Do not produce CFI when not asked for\n\nInsignificant time savings on the host, but also reduces native\nallocation size.\n\nChange-Id: Iea3d335e5375a0076306059d094e5b994e24b9e6\n" }, { "commit": "80b96d1a76790527f72a660ac03d9c215eed17ce", "tree": "8af6fb3840c60c65887cd5de64d987058bb8986e", "parents": [ "39109a06015c91188232e59fa9e60e0915d24cd7" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Feb 19 15:50:28 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Feb 19 18:02:20 2015 +0000" }, "message": "Replace a few std::vector with ArenaVector in Mir2Lir.\n\nChange-Id: I7867d60afc60f57cdbbfd312f02883854d65c805\n" }, { "commit": "a78ef44266c38cc4895554e973156a7c7896dd87", "tree": "5f7648895baa548d8d633be8f9ff17b28e9ea08d", "parents": [ "5409701651407747e172d753f3fddeb6eb423927" ], "author": { "name": "Chao-ying Fu", "email": "chao-ying.fu@intel.com", "time": "Thu Feb 12 14:56:18 2015 -0800" }, "committer": { "name": "Chao-ying Fu", "email": "chao-ying.fu@intel.com", "time": "Thu Feb 12 14:56:18 2015 -0800" }, "message": "ART: Fix InsertCaseLabel to return boundary_lir always\n\nThis patch doesn\u0027t return new_label when cu_-\u003everbose, because\nwe will not assign offsets to new_label at this stage.\n\nChange-Id: Ie7f625848b0cf7cabfbba694b5c20b0784bc8501\nSigned-off-by: Chao-ying Fu \u003cchao-ying.fu@intel.com\u003e\n" }, { "commit": "72f53af0307b9109a1cfc0671675ce5d45c66d3a", "tree": "fc25359ca59f8f3b69a03a7d3726d615086ce1f4", "parents": [ "2a3611feeb12bd73ccdbb4692f9ca3705f925d56" ], "author": { "name": "Chao-ying Fu", "email": "chao-ying.fu@intel.com", "time": "Tue Nov 11 16:48:40 2014 -0800" }, "committer": { "name": "Chao-ying Fu", "email": "chao-ying.fu@intel.com", "time": "Mon Feb 09 15:15:15 2015 -0800" }, "message": "ART: Remove MIRGraph::dex_pc_to_block_map_\n\nThis patch removes MIRGraph::dex_pc_to_block_map_, adds a local\nvariable dex_pc_to_block_map inside MIRGraph::InlineMethod(), and\nupdates several functions to pass dex_pc_to_block_map.\nThe goal is to limit the scope of dex_pc_to_block_map and\nthe usage of FindBlock, so that various compiler optimizations\ncannot rely on dex pc to look up basic blocks to avoid\nduplicated dex pc issues.\nAlso, this patch changes quick targets to use successor blocks\nfor switch case target generation at Mir2Lir::InstallSwitchTables().\n\nChange-Id: I9f571efebd2706b4e1606279bd61f3b406ecd1c4\nSigned-off-by: Chao-ying Fu \u003cchao-ying.fu@intel.com\u003e\n" }, { "commit": "9c462086269324350516b3394d478f1d71a4b5d1", "tree": "4b2a29b0cda0ba50dfb09a6bcc83a4cfecf3769e", "parents": [ "04a77807a657e86495e7ececf7dc530fa5003c4c" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jan 27 14:31:40 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jan 27 15:23:06 2015 -0800" }, "message": "ART: Even more Quick cleanup\n\nRemove Backend.\n\nChange-Id: I247cc65ccda6a362ba1a8f5e73e7f12ecd980a87\n" }, { "commit": "0b9203e7996ee1856f620f95d95d8a273c43a3df", "tree": "a9715986cfdbb21e4d64f72b56fac255cc8b9309", "parents": [ "4dfe58d8f2d398963f31831a57fbd12e282e1196" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jan 22 20:39:27 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Jan 26 14:30:40 2015 -0800" }, "message": "ART: Some Quick cleanup\n\nMake several fields const in CompilationUnit. May benefit some Mir2Lir\ncode that repeats tests, and in general immutability is good.\n\nRemove compiler_internals.h and refactor some other headers to reduce\noverly broad imports (and thus forced recompiles on changes).\n\nChange-Id: I898405907c68923581373b5981d8a85d2e5d185a\n" }, { "commit": "7e499925f8b4da46ae51040e9322690f3df992e6", "tree": "a87402560b942959e6762277e630c72810dfa4cc", "parents": [ "1e862370ff2c3207afd1b2fc6f77f7ca345643b2" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jan 06 08:28:12 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jan 06 08:28:12 2015 -0800" }, "message": "ART: Remove LowestSetBit and IsPowerOfTwo\n\nRemove those functions from Mir2Lir and replace with functionality\nfrom utils.h.\n\nChange-Id: Ieb67092b22d5d460b5241c7c7931c15b9faf2815\n" }, { "commit": "e21dc3db191df04c100620965bee4617b3b24397", "tree": "2ad762c6afb024bf95e1eced3d584649a4d57d23", "parents": [ "6d1a047b4b3f9707d4ee1cc19e99717ee021ef48" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Dec 08 16:59:43 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Dec 22 10:01:27 2014 -0800" }, "message": "ART: Swap-space in the compiler\n\nIntroduce a swap-space and corresponding allocator to transparently\nswitch native allocations to memory backed by a file.\n\nBug: 18596910\n\n(cherry picked from commit 62746d8d9c4400e4764f162b22bfb1a32be287a9)\n\nChange-Id: I131448f3907115054a592af73db86d2b9257ea33\n" }, { "commit": "6c964c98400b8c0949d5e369968da2d4809b772f", "tree": "82c1893c0dbbd5a9b849b9c236fc775b4d20f3cc", "parents": [ "c4925d4c02dc8f8d51cb2653b5e7a99f6c9fd7d7", "717a3e447c6f7a922cf9c3efe522747a187a045d" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Dec 08 18:38:42 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Dec 08 18:38:43 2014 +0000" }, "message": "Merge \"Re-factor Quick ABI support\"" }, { "commit": "717a3e447c6f7a922cf9c3efe522747a187a045d", "tree": "736fca26f68838c71942f206917e5fe320a6ada9", "parents": [ "90fe256384b5fcd955018888977df07a5c0d85f4" ], "author": { "name": "Serguei Katkov", "email": "serguei.i.katkov@intel.com", "time": "Thu Nov 13 17:19:42 2014 +0600" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Dec 08 11:33:54 2014 +0000" }, "message": "Re-factor Quick ABI support\n\nNow every architecture must provide a mapper between\nVRs parameters and physical registers. Additionally as\na helper function architecture can provide a bulk copy\nhelper for GenDalvikArgs utility.\nAll other things becomes a common code stuff:\nGetArgMappingToPhysicalReg, GenDalvikArgsNoRange,\nGenDalvikArgsRange, FlushIns.\n\nMapper now uses shorty representation of input\nparameters. This is required due to location are not\nenough to detect the type of parameter (fp or core).\nFor the details\nsee https://android-review.googlesource.com/#/c/113936/.\n\nChange-Id: Ie762b921e0acaa936518ee6b63c9a9d25f83e434\nSigned-off-by: Serguei Katkov \u003cserguei.i.katkov@intel.com\u003e\n" }, { "commit": "27dee8bcd7b4a53840b60818da8d2c819ef199bd", "tree": "0cee4ca5dd80368703ac4b5a1139867fd0bba797", "parents": [ "b510c82ebaf11cf6f4f215f6237ee6a44861ef10" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Mon Dec 01 19:06:12 2014 -0500" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Dec 04 16:31:03 2014 -0500" }, "message": "X86_64 QBE: use RIP addressing\n\nTake advantage of RIP addressing in 64 bit mode to improve the code\ngeneration for accesses to the constant area as well as packed switches.\nAvoid computing the address of the start of the method, which is needed\nin 32 bit mode.\n\nTo do this, we add a new \u0027pseudo-register\u0027 kRIPReg to minimize the\nchanges needed to get the new addressing mode to be generated.\n\nChange-Id: Ia28c93f98b09939806d91ff0bd7392e58996d108\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "ab972ef472001fa113d54486d7592979e33480b3", "tree": "08a8bf01ddfc0fd3a012faac2b49fafa5853e56f", "parents": [ "8b9a97e8b6ed97ff1991596cbd0f7ce78f004766" ], "author": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed Dec 03 17:38:22 2014 -0800" }, "committer": { "name": "Mathieu Chartier", "email": "mathieuc@google.com", "time": "Wed Dec 03 18:27:43 2014 -0800" }, "message": "Remove method verification results right after compiling a method\n\nThis saves memory since it allows the code arrays from methods\ncompiled in future methods to use the ram we just freed from the\nverification results.\n\nGmsCore.apk:\nBefore: dex2oat took 77.383s (threads: 2) arena alloc\u003d6MB java alloc\u003d30MB native alloc\u003d77MB free\u003d13KB\nAfter: dex2oat took 72.180s (threads: 2) arena alloc\u003d6MB java alloc\u003d30MB native alloc\u003d60MB free\u003d13KB\n\nBug: 18596910\nChange-Id: I5d6df380e4fe58751a2b304202083f4d30b33b7c\n(cherry picked from commit 25fda92083d5b93b38cc1f6b12ac6a44d992d6a4)\n" }, { "commit": "7ab2fce83cd72c0963128b098a78606e77ea15d5", "tree": "e007ba1393b874f128d0db55fc0c90dbbec9bad8", "parents": [ "f2d52e4d32fbedee2a11692e1f1d986ba68ea493" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Nov 28 13:38:28 2014 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Nov 28 13:49:19 2014 +0000" }, "message": "Refactor handling of conditional branches with known result.\n\nDetect IF_cc and IF_ccZ instructions with known results in\nthe basic block optimization phase (instead for the codegen\nphase) and replace them with GOTO/NOP. Kill blocks that are\nunreachable as a result.\n\nChange-Id: I169c2fa6f1e8af685f4f3a7fe622f5da862ce329\n" }, { "commit": "743b98cd3d7db1cfd6b3d7f7795e8abd9d07a42d", "tree": "f84a555c7c4597f9569de48ac205e7c31f05ccd6", "parents": [ "a5de1924ddf0e6e89d98484a3b93b63b126bac76" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Nov 24 19:45:41 2014 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Nov 24 19:49:22 2014 +0000" }, "message": "Skip null check in MarkGCCard() for known non-null values.\n\nUse GVN\u0027s knowledge of non-null values to set a new MIR flag\nfor IPUT/SPUT/APUT to skip the value null check.\n\nChange-Id: I97a8d1447acb530c9bbbf7b362add366d1486ee1\n" }, { "commit": "bf535be514570fc33fc0a6347a87dcd9097d9bfd", "tree": "c78dcf5788ac11cd349b054fcc77efc308986961", "parents": [ "a500b03003c9286cc049c27fdb2e0f0750f83a30" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Nov 19 18:52:35 2014 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Nov 20 11:55:38 2014 +0000" }, "message": "Add card mark to filled-new-array.\n\nBug: 18032332\nChange-Id: I35576b27f9115e4d0b02a11afc5e483b9e93a04a\n" }, { "commit": "ad17d41841ba1fb177fb0bf175ec0e9f5e1412b3", "tree": "e3bf8fb6a51eed07d4cd3e2d007acbb8723ed6df", "parents": [ "8851cbaeb75f5a89ec88cbf4b26d6f846bbf6411", "785d2f2116bb57418d81bb55b55a087afee11053" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Nov 04 07:51:34 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Nov 04 07:51:34 2014 +0000" }, "message": "Merge \"ART: Replace COMPILE_ASSERT with static_assert (compiler)\"" }, { "commit": "785d2f2116bb57418d81bb55b55a087afee11053", "tree": "34e7ea4f2c7473c8fe173c64451b4153fc909cd7", "parents": [ "07f09809c0575e985249450843b06f266b831fe1" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Nov 03 22:57:30 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Nov 03 23:40:41 2014 -0800" }, "message": "ART: Replace COMPILE_ASSERT with static_assert (compiler)\n\nReplace all occurrences of COMPILE_ASSERT in the compiler tree.\n\nChange-Id: Icc40a38c8bdeaaf7305ab3352a838a2cd7e7d840\n" }, { "commit": "6a3c1fcb4ba42ad4d5d142c17a3712a6ddd3866f", "tree": "9df58b57af13240a93a6da4eefcf03f70cce9ad9", "parents": [ "c6e0955737e15f7c0c3575d4e13789b3411f4993" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Oct 31 00:33:20 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Nov 03 20:01:04 2014 -0800" }, "message": "Remove -Wno-unused-parameter and -Wno-sign-promo from base cflags.\n\nFix associated errors about unused paramenters and implict sign conversions.\nFor sign conversion this was largely in the area of enums, so add ostream\noperators for the effected enums and fix tools/generate-operator-out.py.\nTidy arena allocation code and arena allocated data types, rather than fixing\nnew and delete operators.\nRemove dead code.\n\nChange-Id: I5b433e722d2f75baacfacae4d32aef4a828bfe1b\n" }, { "commit": "d8c3e3608a7b47e82186e4f8118541ef06d9eab2", "tree": "5e3e80e1fc4aa35fb829e869ef10895aadd97ec5", "parents": [ "9e878d50567f624094f3c4940ac3aedbc5eff3b9" ], "author": { "name": "Alexei Zavjalov", "email": "alexei.zavjalov@intel.com", "time": "Wed Oct 08 15:51:59 2014 +0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Thu Oct 09 10:14:58 2014 -0700" }, "message": "ART: X86: GenLongArith should handle overlapped VRs\n\nIn a case, when src and dest VRs are overlapped when we called\nGenLongArith it may cause the incorrect use of regs.\n\nThe solution is to map src to an physical reg and work with this\nreg instead of mem.\n\nRenamed BadOverlap() to PartiallyIntersects() for consistency.\n\nChange-Id: Ia3fc7f741f0a92556e1b2a1b084506662ef04c9d\nSigned-off-by: Katkov, Serguei I \u003cserguei.i.katkov@intel.com\u003e\nSigned-off-by: Alexei Zavjalov \u003calexei.zavjalov@intel.com\u003e\n" }, { "commit": "27cc09337cdff14f592f4e22fd235809ebe0d6a7", "tree": "f4736d92888a02b4115f5030cfc35b46d7b8e8d8", "parents": [ "3eae0839c28469a00030b967b998e9c8a694c1a5" ], "author": { "name": "Matteo Franchin", "email": "matteo.franchin@arm.com", "time": "Mon Sep 08 18:29:24 2014 +0100" }, "committer": { "name": "Matteo Franchin", "email": "matteo.franchin@arm.com", "time": "Fri Oct 03 11:53:02 2014 +0100" }, "message": "AArch64: oat patches should be 32-bit ints.\n\nThis makes the arm64 backend consistent with the behaviour of the code\nin oat_writer.cc and in the patchoat tool.\nIt also reduces the size of boot.oat by 1.6% (aosp_arm64-eng build).\n\nChange-Id: Ia0b96737159c08955cd7b776ee396ff578cd58f6\n" }, { "commit": "750359753444498d509a756fa9a042e9f3c432df", "tree": "4261bdcbe1fcd6a1163eda372b6ef4796731017c", "parents": [ "c70535b4f9f1ff3e3da451734bb7d9601012ccc1" ], "author": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Thu Sep 11 15:24:59 2014 -0700" }, "committer": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Mon Sep 29 17:49:59 2014 +0000" }, "message": "ART: Deprecate CompilationUnit\u0027s code_item\n\nThe code_item field is tracked in both the CompilationUnit and the MIRGraph.\nHowever, the existence of this field in CompilationUnit promotes bad practice\nbecause it creates assumption only a single code_item can be part of method.\n\nThis patch deprecates this field and updates MIRGraph methods to make it\neasy to get same information as before. Part of this is the update to\ninterface GetNumDalvikInsn which ensures to count all code_items in MIRGraph.\n\nSome dead code was also removed because it was not friendly to these updates.\n\nChange-Id: Ie979be73cc56350321506cfea58f06d688a7fe99\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n" }, { "commit": "f4da675bbc4615c5f854c81964cac9dd1153baea", "tree": "ea78bafc7ee543e11e7bd824ab40d5f5f3d82f9d", "parents": [ "f2476d524281c6d649f5deb6d1ccccc92380c1ed" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Aug 01 19:04:18 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Sep 25 18:56:34 2014 +0100" }, "message": "Implement method calls using relative BL on ARM.\n\nStore the linker patches with each CompiledMethod instead of\nkeeping them in CompilerDriver. Reorganize oat file creation\nto apply the patches as we\u0027re writing the method code. Add\nframework for platform-specific relative call patches in the\nOatWriter. Implement relative call patches for ARM.\n\nChange-Id: Ie2effb3d92b61ac8f356140eba09dc37d62290f8\n" }, { "commit": "e39c54ea575ec710d5e84277fcdcc049f8acb3c9", "tree": "407209e732961074488043f6ccba8f1d692298a6", "parents": [ "b36bba6d35e88687852b108c8d4b73b3ec2a9397" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Sep 22 14:50:02 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Sep 23 14:42:17 2014 +0100" }, "message": "Deprecate GrowableArray, use ArenaVector instead.\n\nPurge GrowableArray from Quick and Portable.\nRemove GrowableArray\u003cT\u003e::Iterator.\n\nChange-Id: I92157d3a6ea5975f295662809585b2dc15caa1c6\n" }, { "commit": "589e046c483ca0dbee6c28fb617997f43ee28b94", "tree": "347ba057be243341f5e5094071149a712121d1f7", "parents": [ "b9620f305c79914f5159cf9279a7ccd173af1186" ], "author": { "name": "Serguei Katkov", "email": "serguei.i.katkov@intel.com", "time": "Fri Sep 05 18:37:22 2014 +0700" }, "committer": { "name": "Serguei Katkov", "email": "serguei.i.katkov@intel.com", "time": "Thu Sep 11 10:46:15 2014 +0700" }, "message": "Slow path should break def tracking\n\nSlow path usually results in invocation of runtime. Runtime\nshould be ensured that all VR on stack are up to date.\nTo do this we reset def tracking system at the moment of\nadding slow path and as a result actual writes to stack\nfor all VRs will not be optimized away.\n\nThe decision is conservative to be safe however\nprobably not all runtime calls can potentially require VRs\nto be on stack. In this case we will need insert reset def\ntracking in all places where dangerous slow path is used.\n\nChange-Id: I2cb7698a12c17354060fdbb944e1da1fb922c23b\nSigned-off-by: Serguei Katkov \u003cserguei.i.katkov@intel.com\u003e\n" }, { "commit": "de0b996661351450fa4d918706c5322e001c29c9", "tree": "a74031a9577d63786e22c0965f2446072558eb72", "parents": [ "6e3604287f73fbc58d8297c0bca6bfe808524a2b" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Wed Aug 27 14:24:42 2014 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Sep 02 17:24:48 2014 -0700" }, "message": "ART: Fix read-out-of-bounds in the compiler\n\nIn case of a wide dalvik register, asking for the constant value\ncan lead to a read out of bounds.\n\nBug: 17302671\n\n(cherry picked from commit ade731854d18839823e57fb2d3d67238c5467d15)\n\nChange-Id: Ie1849cd67cc418c97cbd7a8524f027f9b66e4c96\n" }, { "commit": "8d0d03e24325463f0060abfd05dba5598044e9b1", "tree": "06e8ed7e47a4cfe108d4ed750de6a60e588b2f7a", "parents": [ "709368e616791209b02d39adb6da5e55782cb45f" ], "author": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Fri Jun 06 17:04:52 2014 -0700" }, "committer": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Tue Aug 26 18:36:46 2014 -0700" }, "message": "ART: Change temporaries to positive names\n\nChanges compiler temporaries to have positive names. The numbering now\nputs them above the code VRs (locals + ins, in that order). The patch also\nintroduces APIs to query the number of temporaries, locals and ins.\n\nThe compiler temp infrastructure suffered from several issues\nwhich are also addressed by this patch:\n-There is no longer a queue of compiler temps. This would be polluted\nwith Method* when post opts were called multiple times.\n-Sanity checks have been added to allow requesting of temps from BE\nand to prevent temps after frame is committed.\n-None of the structures holding temps can overflow because they are\nallocated to allow holding maximum temps. Thus temps can be requested\nby BE with no problem.\n-Since the queue of compiler temps is no longer maintained, it is no\nlonger possible to refer to a temp that has invalid ssa (because it\nwas requested before ssa was run).\n-The BE can now request temps after all ME allocations and it is guaranteed\nto actually receive them.\n-ME temps are now treated like normal VRs in all cases with no special\nhandling. Only the BE temps are handled specially because there are no\nreferences to them from MIRs.\n-Deprecated and removed several fields in CompilationUnit that saved\nregister information and updated callsites to call the new interface from\nMIRGraph.\n\nChange-Id: Ia8b1fec9384a1a83017800a59e5b0498dfb2698c\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\nSigned-off-by: Udayan Banerji \u003cudayan.banerji@intel.com\u003e\n" }, { "commit": "e3ea83811d47152c00abea24a9b420651a33b496", "tree": "dd3b8018176ada85d51b2f8ca46e515fbf55b50f", "parents": [ "9dcf75c80187504ec88e7ef91d64a6a68279eb9d" ], "author": { "name": "Yevgeny Rouban", "email": "yevgeny.y.rouban@intel.com", "time": "Fri Aug 08 16:29:38 2014 +0700" }, "committer": { "name": "Tong Shen", "email": "endlessroad@google.com", "time": "Fri Aug 15 15:04:12 2014 -0700" }, "message": "ART source line debug info in OAT files\n\nOAT files have source line information enough for ART runtime needs like\njump to/from interpreter and thread suspension. But this information\nis not enough for finer grained source level debugging and low-level\nprofiling (VTune or perf).\n\nThis patch adds to OAT files two additional sections:\n.debug_line - DWARF formatted Elf32 section with detailed source line\n information (mapping from native PC to Java source lines).\n\nIn addition to the debugging symbols added using the dex2oat option\n--include-debug-symbols, the source line information is added to\nthe section .debug_line.\n\nThe source line info can be read by many Elf reading tools like objdump,\nreadelf, dwarfdump, gdb, perf, VTune, ...\n\ngdb can use this debug line information in x86. In 64-bit mode\nthe information can be used if the oat file is mapped in the lower\naddress space (address has higher 32 bits zeroed). Relocation works.\n\nTesting:\n1. art/test/run-test --host --gdb [--64] 001-HelloWorld\n2. in gdb: break Main.java:19\n3. in gdb: break Runtime.java:111\n4. in gdb: run - stops at void java.lang.Runtime.\u003cinit\u003e()\n5. in gdb: backtrace - shows call stack down to main()\n6. in gdb: continue - stops at void Main.main() (only in 32-bit mode)\n7. in gdb: backtrace - shows call stack down to main()\n8. objdump -W \u003coat-file\u003e - addresses are from VMA range of .text\n section reported by objdump -h \u003cfile\u003e\n9. dwarfdump -ka \u003coat-file\u003e - no errors expected\n\nSize of aosp-x86-eng boot.oat increased by 11% from 80.5Mb to 89.2Mb\nwith two sections added .debug_line (7.2Mb) and .rel.debug (1.5Mb).\n\nChange-Id: Ib8828832686e49782a63d5529008ff4814ed9cda\nSigned-off-by: Yevgeny Rouban \u003cyevgeny.y.rouban@intel.com\u003e\n" }, { "commit": "547cdfd21ee21e4ab9ca8692d6ef47c62ee7ea52", "tree": "078d52b6025fc1e42b7343550b0dbbdad69eafac", "parents": [ "8b62dc0f993d0445401655fc274e5225498fa81c" ], "author": { "name": "Tong Shen", "email": "endlessroad@google.com", "time": "Tue Aug 05 01:54:19 2014 -0700" }, "committer": { "name": "Tong Shen", "email": "endlessroad@google.com", "time": "Tue Aug 05 11:11:33 2014 -0700" }, "message": "Emit CFI for x86 \u0026 x86_64 JNI compiler.\n\nNow for host-side x86 \u0026 x86_64 ART, we are able to get complete stacktrace with even mixed C/C++ \u0026 Java stack frames.\n\nTesting:\n1. art/test/run-test --host --gdb [--64] --no-relocate 005\n2. In gdb, run \u0027b art::Class_classForName\u0027 which is implementation of a Java native method, then \u0027r\u0027\n3. In gdb, run \u0027bt\u0027. You should see stack frames down to main()\n\nChange-Id: I2d17e9aa0f6d42d374b5362a15ea35a2fce96302\n" }, { "commit": "4fc785398707ede68f29768748b7fe5fa39dde24", "tree": "9452df749e5720aa921af79b0e8ec410ecf6c4fc", "parents": [ "4d110c25bbcc3ed4603e94968ee02db7b2c9db8c" ], "author": { "name": "Fred Shih", "email": "ffred@google.com", "time": "Wed Aug 06 16:44:22 2014 -0700" }, "committer": { "name": "Fred Shih", "email": "ffred@google.com", "time": "Wed Aug 06 16:51:17 2014 -0700" }, "message": "Fixed build breakage due to incorrect class TypeId.\n\nFixed incorrect type id being inserted in code buffer and got rid of\ninefficient pointer wrapping in LoadClassType.\n\nChange-Id: I7ee1d957ebcd816445c26199723ac50787d926d7\n" }, { "commit": "e7f82e2515f47f3c3292281312d7031a34a58ffc", "tree": "13ee86f3d650a901c7251fb1d08e1c3b0241d67c", "parents": [ "b9dbab627bdc3570d5f41cfd6de80ff3b70e1783" ], "author": { "name": "Fred Shih", "email": "ffred@google.com", "time": "Wed Aug 06 10:46:37 2014 -0700" }, "committer": { "name": "Fred Shih", "email": "ffred@google.com", "time": "Wed Aug 06 14:53:43 2014 -0700" }, "message": "Added support for patching classes from different dex files.\n\nAdded support for class patching from different dex files and moved\nScopedObjectAccess from the quick compiler to driver. Slight refactoring\nfor clarity.\n\nBug: 16656190\nChange-Id: I107fcbce75db42ca61321ea1c5d5f236680a1b3d\n" }, { "commit": "8081d2b8d7a743729557051d0294e040e61c747a", "tree": "37c2bd8616831df3a0f9f2df0932ebb517dbcd3d", "parents": [ "8f1dc7a20049ba6e2f3c7f800908bff811cdbea1" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jul 31 15:33:43 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Aug 05 09:45:24 2014 +0100" }, "message": "Create allocator adapter for using Arena in std containers.\n\nCreate ArenaAllocatorAdapter, similar to the existing\nScopedArenaAllocatorAdapter, for allocating memory for\nstandard containers via the ArenaAllocator. Add the ability\nto specify allocation kind rather than just kArenaAllocSTL\nto both adapters. Move the scoped arena allocator to the\nscoped_arena_containers.h header file.\n\nDefine template aliases for containers using the new adapter\nand change a few MIRGraph and Mir2Lir members to use them.\n\nChange-Id: I9bbc50248e0fed81729497b848cb29bf68444268\n" }, { "commit": "69dfe51b684dd9d510dbcb63295fe180f998efde", "tree": "daa2522650ca03417e4518dc8aef989ec53a6065", "parents": [ "479f131d4bd3829dd512312020808b05f5a591f1" ], "author": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Fri Jul 11 17:11:58 2014 +0000" }, "committer": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Wed Jul 16 14:58:27 2014 -0700" }, "message": "Revert \"Revert \"Revert \"Revert \"Add implicit null and stack checks for x86\"\"\"\"\n\nThis reverts commit 0025a86411145eb7cd4971f9234fc21c7b4aced1.\n\nBug: 16256184\nChange-Id: Ie0760a0c293aa3b62e2885398a8c512b7a946a73\n" }, { "commit": "ccc60264229ac96d798528d2cb7dbbdd0deca993", "tree": "998378a38ca4d510090c7b4e7832379989354680", "parents": [ "bc9127a5d451058aede5562e2b015caec618d008" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Jul 04 18:02:38 2014 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Sat Jul 12 13:33:12 2014 -0700" }, "message": "ART: Rework TargetReg(symbolic_reg, wide)\n\nMake the standard implementation in Mir2Lir and the specialized one\nin the x86 backend return a pair when wide \u003d \"true\". Introduce\nWideKind enumeration to improve code readability. Simplify generic\ncode based on this implementation.\n\nChange-Id: I670d45aa2572eedfdc77ac763e6486c83f8e26b4\n" }, { "commit": "0025a86411145eb7cd4971f9234fc21c7b4aced1", "tree": "933b8b96ea970c23a7b3ce313c7c6d46f807dadd", "parents": [ "7fb36ded9cd5b1d254b63b3091f35c1e6471b90e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jul 11 08:26:40 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jul 11 08:26:40 2014 +0000" }, "message": "Revert \"Revert \"Revert \"Add implicit null and stack checks for x86\"\"\"\n\nBroke the build.\n\nThis reverts commit 7fb36ded9cd5b1d254b63b3091f35c1e6471b90e.\n\nChange-Id: I9df0e7446ff0913a0e1276a558b2ccf6c8f4c949\n" }, { "commit": "7fb36ded9cd5b1d254b63b3091f35c1e6471b90e", "tree": "eb1e3b96efd67cc6b84a6f7e35522f33973ca8db", "parents": [ "93279da4a8475d187a0a2e75d50c88def5b4b8a5" ], "author": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Thu Jul 10 02:05:10 2014 +0000" }, "committer": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Thu Jul 10 21:24:47 2014 +0000" }, "message": "Revert \"Revert \"Add implicit null and stack checks for x86\"\"\n\nFixes x86_64 cross compile issue. Removes command line options\nand property to set implicit checks - this is hard coded now.\n\nThis reverts commit 3d14eb620716e92c21c4d2c2d11a95be53319791.\n\nChange-Id: I5404473b5aaf1a9c68b7181f5952cb174d93a90d\n" }, { "commit": "c380191f3048db2a3796d65db8e5d5a5e7b08c65", "tree": "56f7f5fc60f8445ead63cd43faf06b9e1dfda6b2", "parents": [ "cba6b1fc88fd54c35211fd49a7a7501cfcdaa170" ], "author": { "name": "Serguei Katkov", "email": "serguei.i.katkov@intel.com", "time": "Tue Jul 08 17:21:53 2014 +0700" }, "committer": { "name": "Chao-ying Fu", "email": "chao-ying.fu@intel.com", "time": "Thu Jul 10 13:31:47 2014 -0700" }, "message": "x86_64: Enable fp-reg promotion\n\nPatch introduces 4 register XMM12-15 available for promotion of\nfp virtual registers.\n\nChange-Id: I3f89ad07fc8ae98b70f550eada09be7b693ffb67\nSigned-off-by: Serguei Katkov \u003cserguei.i.katkov@intel.com\u003e\nSigned-off-by: Chao-ying Fu \u003cchao-ying.fu@intel.com\u003e\n" }, { "commit": "3d14eb620716e92c21c4d2c2d11a95be53319791", "tree": "aadce4d6bb70e549b74b537c6f75617cf533576a", "parents": [ "34e826ccc80dc1cf7c4c045de6b7f8360d504ccf" ], "author": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Thu Jul 10 01:54:57 2014 +0000" }, "committer": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Thu Jul 10 01:54:57 2014 +0000" }, "message": "Revert \"Add implicit null and stack checks for x86\"\n\nIt breaks cross compilation with x86_64.\n\nThis reverts commit 34e826ccc80dc1cf7c4c045de6b7f8360d504ccf.\n\nChange-Id: I34ba07821fc0a022fda33a7ae21850957bbec5e7\n" }, { "commit": "34e826ccc80dc1cf7c4c045de6b7f8360d504ccf", "tree": "76901cff2cddd6d30cb7a4e83ad4e0c9bb673fe1", "parents": [ "c21dc06adc8c8447561208a3fb72ccf6d0443613" ], "author": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Thu May 29 08:20:04 2014 -0700" }, "committer": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Wed Jul 09 16:19:59 2014 -0700" }, "message": "Add implicit null and stack checks for x86\n\nThis adds compiler and runtime changes for x86\nimplicit checks. 32 bit only.\n\nBoth host and target are supported.\nBy default, on the host, the implicit checks are null pointer and\nstack overflow. Suspend is implemented but not switched on.\n\nChange-Id: I88a609e98d6bf32f283eaa4e6ec8bbf8dc1df78a\n" }, { "commit": "a77ee5103532abb197f492c14a9e6fb437054e2a", "tree": "b8758c0d0a0ecd2f902a53a0fbb1b5014a153c6f", "parents": [ "3ee86bcbbc29f17b0243954a52dcda96b09411e0" ], "author": { "name": "Chao-ying Fu", "email": "chao-ying.fu@intel.com", "time": "Tue Jul 01 17:43:41 2014 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jul 03 14:44:01 2014 -0700" }, "message": "x86_64: TargetReg update for x86\n\nAlso includes changes in common code. Elimination of use of TargetReg\nwith one parameter and direct access to special target registers.\n\nChange-Id: Ied2c1f87d4d1e4345248afe74bca40487a46a371\nSigned-off-by: Serguei Katkov \u003cserguei.i.katkov@intel.com\u003e\nSigned-off-by: Chao-ying Fu \u003cchao-ying.fu@intel.com\u003e\n" }, { "commit": "b5860fb459f1ed71f39d8a87b45bee6727d79fe8", "tree": "3ac54afcb83678d3edfef855f62b79de8b3fff85", "parents": [ "555377d55c37db860583e0655f63a1dacb589921" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Sat Jun 21 15:31:01 2014 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Jul 03 00:12:07 2014 -0700" }, "message": "Register promotion support for 64-bit targets\n\nNot sufficiently tested for 64-bit targets, but should be\nfairly close.\n\nA significant amount of refactoring could stil be done, (in\nlater CLs).\n\nWith this change we are not making any changes to the vmap\nscheme. As a result, it is a requirement that if a vreg\nis promoted to both a 32-bit view and the low half of a\n64-bit view it must share the same physical register. We\nmay change this restriction later on to allow for more flexibility\nfor 32-bit Arm.\n\nFor example, if v4, v5, v4/v5 and v5/v6 are all hot enough to\npromote, we\u0027d end up with something like:\n\nv4 (as an int) -\u003e r10\nv4/v5 (as a long) -\u003e r10\nv5 (as an int) -\u003e r11\nv5/v6 (as a long) -\u003e r11\n\nFix a couple of ARM64 bugs on the way...\n\nChange-Id: I6a152b9c164d9f1a053622266e165428045362f3\n" }, { "commit": "4b537a851b686402513a7c4a4e60f5457bb8d7c1", "tree": "27cffa57d642d98c6c0d8d3e9183c5d306629977", "parents": [ "8b11544881ad6c8aeb50ba7c6a594363c2b684ec" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Jun 30 22:24:53 2014 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jul 01 09:52:40 2014 -0700" }, "message": "ART: Quick compiler: More size checks, add TargetReg variants\n\nAdd variants for TargetReg for requesting specific register usage,\ne.g., wide and ref. More register size checks.\n\nWith code adapted from https://android-review.googlesource.com/#/c/98605/.\n\nChange-Id: I852d3be509d4dcd242c7283da702a2a76357278d\n" }, { "commit": "3c12c512faf6837844d5465b23b9410889e5eb11", "tree": "8372bce9785d2a70b507916e42f3a5242340ea81", "parents": [ "fbd18f1923334f3208cfe6ba5f1d4f9eb421b063" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jun 24 18:46:29 2014 +0000" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jun 24 14:17:48 2014 -0700" }, "message": "Revert \"Revert \"ART: Split out more cases of Load/StoreRef, volatile as parameter\"\"\n\nThis reverts commit de68676b24f61a55adc0b22fe828f036a5925c41.\n\nFixes an API comment, and differentiates between inserting and appending.\n\nChange-Id: I0e9a21bb1d25766e3cbd802d8b48633ae251a6bf\n" }, { "commit": "de68676b24f61a55adc0b22fe828f036a5925c41", "tree": "c71dacfb709787b57fba2ce117fb8ba120d7b150", "parents": [ "2689fbad6b5ec1ae8f8c8791a80c6fd3cf24144d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jun 24 18:42:06 2014 +0000" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jun 24 18:42:06 2014 +0000" }, "message": "Revert \"ART: Split out more cases of Load/StoreRef, volatile as parameter\"\n\nThis reverts commit 2689fbad6b5ec1ae8f8c8791a80c6fd3cf24144d.\n\nBreaks the build.\n\nChange-Id: I9faad4e9a83b32f5f38b2ef95d6f9a33345efa33\n" }, { "commit": "2689fbad6b5ec1ae8f8c8791a80c6fd3cf24144d", "tree": "4a44acb05e5aba25418693fa43c218286e7ee76a", "parents": [ "9462a31caedefac3e04bd4aa5088e050ed188b30" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Jun 23 13:23:04 2014 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Jun 23 13:42:35 2014 -0700" }, "message": "ART: Split out more cases of Load/StoreRef, volatile as parameter\n\nSplits out more cases of ref registers being loaded or stored. For\ncode clarity, adds volatile as a flag parameter instead of a separate\nmethod.\n\nOn ARM64, continue cleanup. Add flags to print/fatal on size mismatches.\n\nChange-Id: I30ed88433a6b4ff5399aefffe44c14a5e6f4ca4e\n" }, { "commit": "8dea81ca9c0201ceaa88086b927a5838a06a3e69", "tree": "6a074462c1c13d23aa21cef3f4d2d1a7a880de32", "parents": [ "3e1e549c564045d852ace46388eb06427d63e6ca" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Jun 06 14:50:36 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Jun 12 18:25:00 2014 +0100" }, "message": "Rewrite use/def masks to support 128 bits.\n\nReduce LIR memory usage by holding masks by pointers in the\nLIR rather than directly and using pre-defined const masks\nfor the common cases, allocating very few on the arena.\n\nChange-Id: I0f6d27ef6867acd157184c8c74f9612cebfe6c16\n" }, { "commit": "85089dd28a39dd20f42ac258398b2a08668f9ef1", "tree": "1917cad5f5649a1dc3f39bb2e03a701a40afd62f", "parents": [ "cd9b4e287c20b14655d21e3f349733e80a5aaf23" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Sun May 25 15:10:52 2014 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Sun May 25 15:10:52 2014 -0700" }, "message": "Quick compiler: generalize NarrowRegLoc()\n\nSome of the RegStorage utilites (DoubleToLowSingle(),\nDoubleToHighSingle(), etc.) worked only for targets which\nwhich treat double precision registers as a pair of aliased\nsingle precision registers.\n\nThis CL elminates those utilities, and replaces them with\na new RegisterInfo utility that will search an aliased register\nset and return the member matching the required storage\nconfiguration (if it exists).\n\nChange-Id: Iff5de10f467d20a56e1a89df9fbf30d1cf63c240\n" }, { "commit": "7bf9c46e93c6f7551f2645cf9bbd1ec9f797c86c", "tree": "c3572f74e2f2b94302b54227674a1d6060a31eb8", "parents": [ "1526c30fff72b6c600b63aebe05d5c4f65c8a29b", "a51a0b0300268b605e3ad71b0e87ff394032c5e7" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 22 09:14:18 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu May 22 09:14:18 2014 +0000" }, "message": "Merge \"Method inlining across dex files in boot image.\"" }, { "commit": "a51a0b0300268b605e3ad71b0e87ff394032c5e7", "tree": "a0a7be25a285c9249f13b968de48f393f6ea8500", "parents": [ "d3236731ca6145e0723ce8aab8c6ff634ab021c2" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed May 21 12:08:39 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu May 22 09:26:41 2014 +0100" }, "message": "Method inlining across dex files in boot image.\n\nFix LoadCodeAddress() and LoadMethodAddress() to use the dex\nfile in addition to the method index to uniquely identify\nthe literal. With that fix in place, when we have both the\ndirect code and the direct method, we can safely pass the\nactual target method id instead of the method id from the\nsame dex file in the method lowering info. This was already\ndone for calls from apps into boot image (and thus there was\na bug with a tiny risk of the wrong literal being used) and\nnow we also do that for calls within the boot image. The\nlatter allows the inlining pass to inline many more methods\nthan before in the boot image.\n\nBug: 15021903\nChange-Id: Ic765ce9809b43ef07e7db32b8e3fbc9acb09147f\n" }, { "commit": "b01bf15d18f9b08d77e7a3c6e2897af0e02bf8ca", "tree": "8cafd7692046b4f8c95fb8e6a713755f9eeddeec", "parents": [ "d3236731ca6145e0723ce8aab8c6ff634ab021c2" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Tue May 13 15:59:07 2014 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed May 21 05:17:24 2014 -0700" }, "message": "64-bit temp register support.\n\nAdd a 64-bit temp register allocation path. The recent physical\nregister handling rework supports multiple views of the same\nphysical register (or, such as for Arm\u0027s float/double regs,\ndifferent parts of the same physical register).\n\nThis CL adds a 64-bit core register view for 64-bit targets. In\nshort, each core register will have a 64-bit name, and a 32-bit\nname. The different views will be kept in separate register pools,\nbut aliasing will be tracked. The core temp register allocation\nroutines will be largely identical - except for 32-bit targets,\nwhich will continue to use pairs of 32-bit core registers for holding\nlong values.\n\nChange-Id: I8f118e845eac7903ad8b6dcec1952f185023c053\n" }, { "commit": "700a402244a1a423da4f3ba8032459f4b65fa18f", "tree": "4c22fcda04d271bd55a37aff30650214af17a90c", "parents": [ "047c11adcbcbc0bcf210defdfcbada763961ffee" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon May 19 16:49:03 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon May 19 22:27:39 2014 -0700" }, "message": "Now we have a proper C++ library, use std::unique_ptr.\n\nAlso remove the Android.libcxx.mk and other bits of stlport compatibility\nmechanics.\n\nChange-Id: Icdf7188ba3c79cdf5617672c1cfd0a68ae596a61\n" }, { "commit": "d65c51a556e6649db4e18bd083c8fec37607a442", "tree": "97fcb17ae74a587c6ef756dda6f4b03db5e9950f", "parents": [ "1e97c4a4ab9f17d1394b952882d59d894b1e3c74" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Apr 29 16:55:20 2014 -0400" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri May 16 11:04:27 2014 -0700" }, "message": "ART: Add support for constant vector literals\n\nAdd in some vector instructions. Implement the ConstVector\ninstruction, which takes 4 words of data and loads it into\nan XMM register.\n\nInitially, only the ConstVector MIR opcode is implemented. Others will\nbe added after this one goes in.\n\nChange-Id: I5c79bc8b7de9030ef1c213fc8b227debc47f6337\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "e45fb9e7976c8462b94a58ad60b006b0eacec49f", "tree": "1d8139f92fb127fc931c6e5c9ca2ed2c8dc871b9", "parents": [ "410d87ff51e9432768924d2f294592818f93c244" ], "author": { "name": "Matteo Franchin", "email": "matteo.franchin@arm.com", "time": "Tue May 06 10:10:30 2014 +0100" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed May 07 14:54:16 2014 -0700" }, "message": "AArch64: Change arm64 backend to produce A64 code.\n\nThe arm backend clone is changed to produce A64 code. At the moment\nthis backend can only compile simple methods (both leaf and non-leaf).\n\nMost of the work on the assembler (assembler_arm64.cc) has been done.\nSome work on the LIR generation layer (functions such as OpRegRegImm\n\u0026 friends) is still necessary. The register allocator still needs to\nbe adapted to the A64 instruction set (it is mostly unchanged from\nthe arm backend). Offsets for helpers in gen_invoke.cc still need to\nbe changed to work on 64-bit.\n\nChange-Id: I388f99eeb832857981c7d9d5cb5b71af64a4b921\n" }, { "commit": "72d32629303f8f39362a4099481f48646aed042f", "tree": "0ff613168c3bf2e12799594c9211f9a1694119e2", "parents": [ "47ebd77a6d249403a34d242908749b7446da2a82" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue May 06 16:20:11 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue May 06 16:23:19 2014 -0700" }, "message": "Give Compiler a back reference to the driver.\n\nThe compiler driver is a single object delegating work to the compiler, rather\nthan passing it through to every Compiler call make it a member of Compiler so\nthat it maybe queried. This simplifies the Compiler API and makes the\nrelationship to CompilerDriver more explicit.\nRemove reference arguments that contravene code style.\n\nChange-Id: Iba47f2e3cbda679a7ec7588f26188d77643aa2c6\n" }, { "commit": "660188264dee3c8f3510e2e24c11816c6b60f197", "tree": "cd18ee6c9328650110f06d14905468ea320342b4", "parents": [ "2a12ad460af139a03c3e9bf5fc7886a7521b333e" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon May 05 20:47:19 2014 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon May 05 20:47:19 2014 -0700" }, "message": "ART: Use utils.h::RoundUp instead of explicit bit-fiddling\n\nChange-Id: I249a2cfeb044d3699d02e13d42b8e72518571640\n" }, { "commit": "f29a4244bbc278843237f0ae242de077e093b580", "tree": "a7364eb7915712e022cd4dcf67b18e2ecf31d7e3", "parents": [ "fac805ba18254db0cb84661dc2085763730e95e7" ], "author": { "name": "Dmitry Petrochenko", "email": "dmitry.petrochenko@intel.com", "time": "Mon May 05 20:28:47 2014 +0700" }, "committer": { "name": "Dmitry Petrochenko", "email": "dmitry.petrochenko@intel.com", "time": "Tue May 06 08:14:06 2014 +0700" }, "message": "x86_64: Fix frame size calculation for 64-bit\n\nCalculate frame size in the same way as calculated in patch\n\"64bit changes to the stack walker for the Quick ABI\"\n\nChange-Id: I8c2458f5973536a84f3fd6ad56167b5cfafa9ab4\nSigned-off-by: Dmitry Petrochenko \u003cdmitry.petrochenko@intel.com\u003e\n" }, { "commit": "091cc408e9dc87e60fb64c61e186bea568fc3d3a", "tree": "b4c19f918a083768b9d940afbb34f9fa388d4e95", "parents": [ "eafef7db77cfbe6bc05d9b07221c198bc8ceaa8a" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon Mar 31 10:14:40 2014 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon May 05 09:55:24 2014 -0700" }, "message": "Quick compiler: allocate doubles as doubles\n\nSignificant refactoring of register handling to unify usage across\nall targets \u0026 32/64 backends.\n\nReworked RegStorage encoding to allow expanded use of\nx86 xmm registers; removed vector registers as a separate\nregister type. Reworked RegisterInfo to describe aliased\nphysical registers. Eliminated quite a bit of target-specific code\nand generalized common code.\n\nUse of RegStorage instead of int for registers now propagated down\nto the NewLIRx() level. In future CLs, the NewLIRx() routines will\nbe replaced with versions that are explicit about what kind of\noperand they expect (RegStorage, displacement, etc.). The goal\nis to eventually use RegStorage all the way to the assembly phase.\n\nTBD: MIPS needs verification.\nTBD: Re-enable liveness tracking.\n\nChange-Id: I388c006d5fa9b3ea72db4e37a19ce257f2a15964\n" }, { "commit": "8194963098247be6bca9cc4a54dbfa65c73e8ccc", "tree": "547cc708e06e6541676b17066023ae6f07b2049b", "parents": [ "56a341a82ece9aa4f2a071629f3e1fd1adf988ae" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri May 02 11:53:22 2014 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri May 02 12:21:02 2014 +0100" }, "message": "Replace CountOneBits and __builtin_popcount with POPCOUNT.\n\nClean up utils.h, make some functions constexpr.\n\nChange-Id: I2399100280cbce81c3c4f5765f0680c1ddcb5883\n" }, { "commit": "ff093b31d75658c3404f9b51ee45760f346f06d9", "tree": "16a11ff5a78862defcc169b0af2901360a57ab6a", "parents": [ "b3016551e5f264264dbb633a1ddf03ac97f9c66c" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Apr 30 19:04:27 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu May 01 08:31:01 2014 -0700" }, "message": "Fix a few 64-bit compilation of 32-bit code issues.\n\nBug: 13423943\n\nChange-Id: I939389413af0a68c0d95b23cd598b7c42afa4383\n" }, { "commit": "6ffcfa04ebb2660e238742a6000f5ccebdd5df15", "tree": "e1b47200044b88458db55eb1d897bee31a018e22", "parents": [ "948740c1938860df055ddc801f20fd1707331e38" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Fri Apr 25 11:06:00 2014 -0700" }, "committer": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Tue Apr 29 13:35:24 2014 -0700" }, "message": "Rewrite suspend test check with LIRSlowPath.\n\nChange-Id: I2dc17d079655586bfc588349c7a04afc2c6879af\n" }, { "commit": "7a11ab09f93f54b1c07c0bf38dd65ed322e86bc6", "tree": "bfd392c07b08a5e0ce9ecb0c3569745935060063", "parents": [ "0f73e2ee44977b9b5cfe42f6c4c3b6a407e92368" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon Apr 28 20:02:38 2014 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Tue Apr 29 05:43:47 2014 -0700" }, "message": "Quick compiler: debugging assists\n\nA few minor assists to ease A/B debugging in the Quick\ncompiler:\n 1. To save time, the assemblers for some targets only\nupdate the object code offsets on instructions involved with\npc-relative fixups. We add code to fix up all offsets when\ndoing a verbose codegen listing.\n 2. Temp registers are normally allocated in a round-robin\nfashion. When disabling liveness tracking, we now reset the\nround-robin pool to 0 on each instruction boundary. This makes\nit easier to spot real codegen differences.\n 3. Self-register copies were previously emitted, but\nmarked as nops. Minor change to avoid generating them in the\nfirst place and reduce clutter.\n\nChange-Id: I7954bba3b9f16ee690d663be510eac7034c93723\n" }, { "commit": "125011d70aa84b3fd9052f1c90101401b0851928", "tree": "df2ed3d17bcda9444ea611db740374ca1fb17d94", "parents": [ "de981b0c9124f0b1f29e18ea6b8cb8328f561aab", "3a74d15ccc9a902874473ac9632e568b19b91b1c" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Wed Apr 23 22:02:33 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Apr 23 22:02:33 2014 +0000" }, "message": "Merge \"Delete throw launchpads.\"" }, { "commit": "695d13a82d6dd801aaa57a22a9d4b3f6db0d0fdb", "tree": "0dbee030a8c43ccc23d9efc0c80efa2d941d1ff6", "parents": [ "86e1b5e7e2bca99dd2092eab8ced977d97830873" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Sat Apr 19 13:32:20 2014 -0700" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Tue Apr 22 11:46:10 2014 -0700" }, "message": "Update load/store utilities for 64-bit backends\n\nThis CL replaces the typical use of LoadWord/StoreWord\nutilities (which, in practice, were 32-bit load/store) in\nfavor of a new set that make the size explicit. We now have:\n\n LoadWordDisp/StoreWordDisp:\n 32 or 64 depending on target. Load or store the natural\n word size. Expect this to be used infrequently - generally\n when we know we\u0027re dealing with a native pointer or flushed\n register not holding a Dalvik value (Dalvik values will flush\n to home location sizes based on Dalvik, rather than the target).\n\n Load32Disp/Store32Disp:\n Load or store 32 bits, regardless of target.\n\n Load64Disp/Store64Disp:\n Load or store 64 bits, regardless of target.\n\n LoadRefDisp:\n Load a 32-bit compressed reference, and expand it to the\n natural word size in the target register.\n\n StoreRefDisp:\n Compress a reference held in a register of the natural word\n size and store it as a 32-bit compressed reference.\n\nChange-Id: I50fcbc8684476abd9527777ee7c152c61ba41c6f\n" }, { "commit": "3a74d15ccc9a902874473ac9632e568b19b91b1c", "tree": "3024a2f6ec8ab6a2b403a889e4c58cee8e43ae27", "parents": [ "4e0d5ee57ab5f76a761cf0d7ebb50b782e3eacdc" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Mon Apr 21 15:39:44 2014 -0700" }, "committer": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Mon Apr 21 15:58:26 2014 -0700" }, "message": "Delete throw launchpads.\n\nBug: 13170824\n\nChange-Id: I9d5834f5a66f5eb00f2ac80774e8c27dea99949e\n" }, { "commit": "d6ed642458c8820e1beca72f3d7b5f0be4a4b64b", "tree": "1b6e0438f786d6eeb5566e176d71d454a6cdb9e5", "parents": [ "f9487c039efb4112616d438593a2ab02792e0304" ], "author": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Wed Apr 09 23:36:15 2014 +0000" }, "committer": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Wed Apr 09 23:36:15 2014 +0000" }, "message": "Revert \"Revert \"Revert \"Use trampolines for calls to helpers\"\"\"\n\nThis reverts commit f9487c039efb4112616d438593a2ab02792e0304.\n\nChange-Id: Id48a4aae4ecce73db468587967968a3f7618b700\n" }, { "commit": "f9487c039efb4112616d438593a2ab02792e0304", "tree": "95f88645bec774d3e8df170bd0f40e4cd0911a34", "parents": [ "b24b0e2bb128532945b31ea62715776d7751f84d" ], "author": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Tue Apr 08 23:08:12 2014 +0000" }, "committer": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Wed Apr 09 13:18:07 2014 -0700" }, "message": "Revert \"Revert \"Use trampolines for calls to helpers\"\"\n\nThis reverts commit 081f73e888b3c246cf7635db37b7f1105cf1a2ff.\n\nChange-Id: Ibd777f8ce73cf8ed6c4cb81d50bf6437ac28cb61\n\nConflicts:\n\tcompiler/dex/quick/mir_to_lir.h\n" }, { "commit": "081f73e888b3c246cf7635db37b7f1105cf1a2ff", "tree": "3ad0cab1dfa3bca814ab162cb04af125e819e623", "parents": [ "754ddad084ccb610d0cf486f6131bdc69bae5bc6" ], "author": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Mon Apr 07 18:58:07 2014 +0000" }, "committer": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Mon Apr 07 18:58:07 2014 +0000" }, "message": "Revert \"Use trampolines for calls to helpers\"\n\nThis reverts commit 754ddad084ccb610d0cf486f6131bdc69bae5bc6.\n\nChange-Id: Icd979adee1d8d781b40a5e75daf3719444cb72e8\n" }, { "commit": "754ddad084ccb610d0cf486f6131bdc69bae5bc6", "tree": "18d8314f3f6760b035c2bcda7760782ad4f0e0bf", "parents": [ "97a332b4476d5a2b4ad0650dacc6bfcff882fc57" ], "author": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Wed Feb 19 14:05:39 2014 -0800" }, "committer": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Fri Apr 04 16:07:46 2014 -0700" }, "message": "Use trampolines for calls to helpers\n\nThis is an ARM specific optimization to the compiler\nthat uses trampoline islands to make calls to runtime\nhelper functions. The intention is to reduce the size\nof the generated code (by 2 bytes per call) without\naffecting performance.\n\nBy default this is on when generating an OAT file. It is\noff when compiling to memory.\n\nTo switch this off in dex2oat, use the command line option:\n--no-helper-trampolines\n\nEnhances disassembler to print the trampoline entry on the\nBL instruction like this:\n\n0xb6a850c0: f7ffff9e bl -196 (0xb6a85000) ; pTestSuspend\n\nBug: 12607709\nChange-Id: I9202bdb7cf21252ad807bd48701f1f6ce8e3d0fe\n" }, { "commit": "6a58cb16d803c9a7b3a75ccac8be19dd9d4e520d", "tree": "c142777f40178fd9b9090cd7316be694befb3f21", "parents": [ "8549cf9d83688f7decbbea2a8de761ce29e95f3c" ], "author": { "name": "Dmitry Petrochenko", "email": "dmitry.petrochenko@intel.com", "time": "Wed Apr 02 17:27:59 2014 +0700" }, "committer": { "name": "Dmitry Petrochenko", "email": "dmitry.petrochenko@intel.com", "time": "Thu Apr 03 13:06:55 2014 +0700" }, "message": "art: Handle x86_64 architecture equal to x86\n\nThis patch forces FE/ME to treat x86_64 as x86 exactly.\nThe x86_64 logic will be revised later when assembly will be ready.\n\nChange-Id: I4a92477a6eeaa9a11fd710d35c602d8d6f88cbb6\nSigned-off-by: Dmitry Petrochenko \u003cdmitry.petrochenko@intel.com\u003e\n" }, { "commit": "f943914730db8ad2ff03d49a2cacd31885d08fd7", "tree": "885a781e5f8bd852e2c1615108ae7b17576a6567", "parents": [ "cfd5acf281b0c509f86b13d73c6a8dfa3ea9922c" ], "author": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Thu Mar 27 15:10:22 2014 -0700" }, "committer": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Mon Mar 31 18:04:08 2014 -0700" }, "message": "Implement implicit stack overflow checks\n\nThis also fixes some failing run tests due to missing\nnull pointer markers.\n\nThe implementation of the implicit stack overflow checks introduces\nthe ability to have a gap in the stack that is skipped during\nstack walk backs. This gap is protected against read/write and\nis used to trigger a SIGSEGV at function entry if the stack\nwill overflow.\n\nChange-Id: I0c3e214c8b87dc250cf886472c6d327b5d58653e\n" }, { "commit": "2700f7e1edbcd2518f4978e4cd0e05a4149f91b6", "tree": "20f7689d972a7fce485fc9388dd98ba52d3174df", "parents": [ "bc428f234ca2885d6689fce82992123479bc643e" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Fri Mar 07 09:46:20 2014 -0800" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Wed Mar 26 18:58:58 2014 -0700" }, "message": "Continuing register cleanup\n\nReady for review.\n\nContinue the process of using RegStorage rather than\nints to hold register value in the top layers of codegen.\nGiven the huge number of changes in this CL, I\u0027ve attempted\nto minimize the number of actual logic changes. With this\nCL, the use of ints for registers has largely been eliminated\nexcept in the lowest utility levels. \"Wide\" utility routines\nhave been updated to take a single RegStorage rather than\na pair of ints representing low and high registers.\n\nUpcoming CLs will be smaller and more targeted. My expectations:\n o Allocate float double registers as a single double rather than\n a pair of float single registers.\n o Refactor to push code which assumes long and double Dalvik\n values are held in a pair of register to the target dependent\n layer.\n o Clean-up of the xxx_mir.h files to reduce the amount of #defines\n for registers. May also do a register renumbering to bring all\n of our targets\u0027 register naming more consistent. Possibly\n introduce a target-independent float/non-float test at the\n RegStorage level.\n\nChange-Id: I646de7392bdec94595dd2c6f76e0f1c4331096ff\n" }, { "commit": "92cf83e001357329cbf41fa15a6e053fab6f4933", "tree": "1dc03f1fb8c3f9af4021c1b82f0c5b0baee39600", "parents": [ "a48850ba1f48066785768d2dd296448cd430d494" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Mar 18 17:59:20 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 19 08:47:01 2014 +0000" }, "message": "Run Java tests with the optimizing compiler.\n\nAlso fix a vector.reserve -\u003e vector.resize braino, and build\na GC map that dex2oat expects.\n\nChange-Id: I6acf2f90a4c32f90b79bf7709bf2e43931b98757\n" }, { "commit": "9545a446e99b22248099fe66f5f9431530c20851", "tree": "359962d0a6a50f0c73f969d5ad67305de397e8a4", "parents": [ "0d64958d157ff6a30cbbe79df14ee4c723d14754", "49161cef10a308aedada18e9aa742498d6e6c8c7" ], "author": { "name": "Jeff Hao", "email": "jeffhao@google.com", "time": "Thu Mar 13 17:55:43 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Mar 13 17:55:44 2014 +0000" }, "message": "Merge \"Allow patching between dex files in the boot classpath.\"" }, { "commit": "3bc8615332b7848dec8c2297a40f7e4d176c0efb", "tree": "5f3f0e36151f62e43beafa474fd59795673f86ae", "parents": [ "c1020433660737d466b0d726bbeb86d9a279a44a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Mar 13 14:11:28 2014 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Mar 13 15:54:41 2014 +0000" }, "message": "Use LIRSlowPath for intrinsics, improve String.indexOf().\n\nRewrite intrinsic launchpads to use the LIRSlowPath.\nImprove String.indexOf for constant chars by avoiding\nthe check for code points over 0xFFFF.\n\nChange-Id: I7fd5583214c5b4ab9c38ee36c5d6f003dd6345a8\n" }, { "commit": "49161cef10a308aedada18e9aa742498d6e6c8c7", "tree": "b5ea61ffc97dd043a00e8dd7746788d9d96b9dd0", "parents": [ "ca46e2003360b44f4c043f6da87092592bc3d6d6" ], "author": { "name": "Jeff Hao", "email": "jeffhao@google.com", "time": "Wed Mar 12 11:05:25 2014 -0700" }, "committer": { "name": "Jeff Hao", "email": "jeffhao@google.com", "time": "Wed Mar 12 18:06:51 2014 -0700" }, "message": "Allow patching between dex files in the boot classpath.\n\nChange-Id: I53f219a5382d0fcd580e96e50025fdad4fc399df\n" }, { "commit": "83cc7ae96d4176533dd0391a1591d321b0a87f4f", "tree": "6b3c607119c1dc2850810f8463dfd968c486fba4", "parents": [ "8785d615122d4abbd22db702139584e8c472f502" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Feb 12 18:02:05 2014 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Thu Mar 06 15:37:40 2014 +0000" }, "message": "Create a scoped arena allocator and use that for LVN.\n\nThis saves more than 0.5s of boot.oat compilation time\non Nexus 5.\n\nTODO: Move other stuff to the scoped allocator. This CL\nalone increases the peak memory allocation. By reusing\nthe memory for other parts of the compilation we should\nreduce this overhead.\n\nChange-Id: Ifbc00aab4f3afd0000da818dfe68b96713824a08\n" }, { "commit": "a1a7074eb8256d101f7b5d256cda26d7de6ce6ce", "tree": "51f2a2dc6fca540cc404aed3ed64b9aae74f586e", "parents": [ "093aad184b4451639951a7e012d9b55cbf8c8a07" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Mar 03 10:28:05 2014 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Mar 04 11:50:09 2014 +0000" }, "message": "Rewrite kMirOpSelect for all IF_ccZ opcodes.\n\nAlso improve special cases for ARM and add tests.\n\nChange-Id: I06f575b9c7b547dbc431dbfadf2b927151fe16b9\n" }, { "commit": "2da882315a61072664f7ce3c212307342e907207", "tree": "67d777be044f5b60e2f13ab7968b63c581904ea9", "parents": [ "762d4e5b9e777ae64c4ba581af9c84b78a5e96a6" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Feb 27 12:26:20 2014 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Mar 03 23:27:12 2014 +0000" }, "message": "Initial changes towards Generic JNI option\n\nSome initial changes that lead to an UNIMPLEMENTED. Works\nby not compiling for JNI right now and tracking native methods\nwhich have neither quick nor portable code. Uses new trampoline.\n\nChange-Id: I5448654044eb2717752fd7359f4ef8bd5c17be6e\n" }, { "commit": "be0e546730e532ef0987cd4bde2c6f5a1b14dd2a", "tree": "41aa0541ec85b8e26c5e50cc7341f506f5d52314", "parents": [ "cc261bfd336eddac18b85d4eb47f6c905d495241" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Wed Feb 26 11:24:15 2014 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Mar 03 12:55:45 2014 +0000" }, "message": "Cache field lowering info in mir_graph.\n\nChange-Id: I9f9d76e3ae6c31e88bdf3f59820d31a625da020f\n" }, { "commit": "ae9fd93c39a341e2dffe15c61cc7d9e841fa92c4", "tree": "e5f70dc307945fd510660ebde1fd259aecdf66a1", "parents": [ "9fab32265f35c808b216210a8d5bebd931279041" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Mon Feb 10 16:14:35 2014 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Sun Mar 02 11:57:10 2014 -0800" }, "message": "Tell GDB about Quick ART generated code\n\nThis is actually a lot of work. To do this, we need:\n.debug_info\n.debug_abbrev\n.debug_frame\n.debug_str\n\nThese are generated into the OAT file by OatWriter and ElfWriterQuick.\n\nSince the Quick ART runtime doesn\u0027t use dlopen to load the OAT files,\nGDB can\u0027t find this information. Use the alternate GDB JIT interface,\nwhich can be invoked at runtime. To use this interface, an ELF image\nneeds to be built in memory. Read the information from the OAT file,\nfixup the addresses to point to the real locations, add a symbol table\nto hold the .text symbol, and then let GDB know about the information,\nwhich will be read from the runtime address space.\n\nThis is quite primitive now, and could be cleaned up considerably. It\nprobably needs symbol table entries for the methods, and descriptions of\nparameters and return types.\n\nCurrently only supported for X86.\n\nThis defaults to enabled for debug builds. Added dexoat --gen-gdb-info\nand --no-gen-gdb-info flags to override.\n\nChange-Id: I4d18b2370f6dfaa00c8cc1925f10717be3bd1a62\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "2e589aa58a1372909f95e731fd6b8895f6359c3a", "tree": "6337f7e4765a6c6c1ba5d21e9f3f7c4ebe4971ee", "parents": [ "661425e1f90d4f4ed44c66f5e74f48b92a3798df" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Feb 25 17:53:53 2014 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Feb 25 19:03:17 2014 +0000" }, "message": "Encode VmapTable entries offset by 2 to reduce size.\n\nWe\u0027re using special values 0xffff and 0xfffe for an\nfp register marker and for method pointer, respectively.\nThese values were being encoded as 3 bytes each and\nthis changes their encoding to 1 byte.\n\nBug: 9437697\nChange-Id: Ic1720e898b131a5d3f6ca87d8e1ecdf76fb4160a\n" }, { "commit": "3bc01748ef1c3e43361bdf520947a9d656658bf8", "tree": "9ac4f9cfd8079f2e89c85986bb60205a6f3e7579", "parents": [ "68bb649b128cd8760732524bd7ba58b49780d9d3" ], "author": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Thu Feb 06 13:18:43 2014 -0800" }, "committer": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Thu Feb 13 14:00:16 2014 -0800" }, "message": "GenSpecialCase support for x86\n\nMoved GenSpecialCase from being ARM specific to common code to allow\nit to be used by x86 quick as well.\n\nChange-Id: I728733e8f4c4da99af6091ef77e5c76ae0fee850\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n" }, { "commit": "55d0eac918321e0525f6e6491f36a80977e0d416", "tree": "4fe2bc465d3fa74fb24b9052465e1dbabd81277e", "parents": [ "14fb1314cc8ef4c8342e5e6f3f830e4a64521623" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Feb 06 11:02:52 2014 -0800" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Mon Feb 10 12:21:49 2014 -0800" }, "message": "Support Direct Method/Type access for X86\n\nThumb generates code to optimize calls to methods within core.oat.\nImplement this for X86 as well, but take advantage of mov with 32 bit\nimmediate and call relative with 32 bit immediate.\n\nFix some incorrect return locations for long inlines.\n\nChange-Id: I1907bdfc7574f3d0aa76c7fad13dc537acdf1ed3\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "bcec6fba95ee7974d3f7b81c3c02e7eb3ca3df00", "tree": "33f74dcf8eab6577a7aa126f49f8279b7990baea", "parents": [ "f2ef56d441986bf2826d1bc635c38ced64c6b476" ], "author": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Fri Jan 17 12:52:22 2014 -0800" }, "committer": { "name": "Dave Allison", "email": "dallison@google.com", "time": "Tue Feb 04 15:18:37 2014 -0800" }, "message": "Make slow paths easier to write\n\nThis adds a class LIRSlowPath that allows for deferred compilation\nof slow paths. Using this object you can add code that will be\ninvoked out of line using a forward branch. The intention is to\nmove the slow paths out of the main flow and avoid branch-over\nconstructs that will almost always trigger. The forward branch\nto the slow path code will be predicted false and this will\nbe correct most of the time. The slow path code returns to the\ninstruction after the original branch using an unconditional branch.\n\nThis is used in the following opcodes: sput, sget, const-string,\ncheck-cast, const-class.\n\nOthers will follow.\n\nBug: 10864890\nChange-Id: I17130c5dc20d369bc6bbf50b8cf04343263e888e\n" }, { "commit": "d69835d841cb7663faaa2f1996e73e8c0b3f6d76", "tree": "84798daf417cca189c9ebd8a04ae0e6ceb4dee8b", "parents": [ "1f00671edaaa34578319d0fdaf605600ed539d41" ], "author": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon Feb 03 14:40:27 2014 -0800" }, "committer": { "name": "buzbee", "email": "buzbee@google.com", "time": "Mon Feb 03 15:43:27 2014 -0800" }, "message": "Art Compiler: fix compiler temps\n\nAOSP CL 78835 \"Enable compiler temporaries\" built on some earlier\nwork to enable the compiler to add temps in the style of Dalvik\u0027s\nvRegs during MIR optimizations. However, it missed an existing\nfixed-size array whose size depended on the number of temps allocated.\nThe allocation of this array must be delayed until after the\nnumber of compiler temps is known.\n\nThe result was array overrun, and strange failures.\n\nChange-Id: I986a3b557e2323e00ba852584de03a02931b3c78\n" }, { "commit": "616ffafa3130d0ef9cdd18c7adbf4e688026a724", "tree": "b6ef3e190072cf7bf680d5263f1d6070167fd42e", "parents": [ "f0c3718cf42e2c45859f136e05bceb224871eae6", "da7a69b3fa7bb22d087567364b7eb5a75824efd8" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Jan 31 22:15:53 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jan 31 22:15:53 2014 +0000" }, "message": "Merge \"Enable compiler temporaries\"" }, { "commit": "da7a69b3fa7bb22d087567364b7eb5a75824efd8", "tree": "17aea3b34d6059b52fab73fc206470eca5e9d305", "parents": [ "353e494a7108f382daf1782596fc0a93d92f38a4" ], "author": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Wed Jan 08 15:09:50 2014 -0800" }, "committer": { "name": "Razvan A Lupusoru", "email": "razvan.a.lupusoru@intel.com", "time": "Fri Jan 31 13:58:28 2014 -0800" }, "message": "Enable compiler temporaries\n\nCompiler temporaries are a facility for having virtual register sized space\nfor dealing with intermediate values during MIR transformations. They receive\nexplicit space in managed frames so they can have a home location in case they\nneed to be spilled. The facility also supports \"special\" temporaries which\nhave specific semantic purpose and their location in frame must be tracked.\n\nThe compiler temporaries are treated in the same way as virtual registers\nso that the MIR level transformations do not need to have special logic. However,\ngenerated code needs to know stack layout so that it can distinguish between\nhome locations.\n\nMIRGraph has received an interface for dealing with compiler temporaries. This\ninterface allows allocation of wide and non-wide virtual register temporaries.\n\nThe information about how temporaries are kept on stack has been moved to\nstack.h. This is was necessary because stack layout is dependent on where the\ntemporaries are placed.\n\nChange-Id: Iba5cf095b32feb00d3f648db112a00209c8e5f55\nSigned-off-by: Razvan A Lupusoru \u003crazvan.a.lupusoru@intel.com\u003e\n" }, { "commit": "39a548933c7d083647ccb1d508240198ffff5a5c", "tree": "fd10a2bdbb31eae70c35f16e24b8da7187157750", "parents": [ "9aeeeac4ba0b136652f213d60a5a1990a333a629", "766e9295d2c34cd1846d81610c9045b5d5093ddd" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Jan 31 19:00:56 2014 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Jan 31 19:00:56 2014 +0000" }, "message": "Merge \"Improve GenConstString, GenS{get,put} for x86\"" }, { "commit": "2730db03beee4d6687ddfb5000c33c0370fbc6eb", "tree": "a85706c800c67deda5c7b612c8010059aa7b365c", "parents": [ "c7f832061fea59fd6abd125f26c8ca1faec695a5" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Jan 27 11:15:17 2014 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jan 28 11:22:42 2014 +0000" }, "message": "Add VerfiedMethod to DexCompilationUnit.\n\nAvoid some mutex locking and map lookups.\n\nChange-Id: I8e0486af77e38dcd065569572a6b985eb57f4f63\n" } ], "next": "c7f832061fea59fd6abd125f26c8ca1faec695a5" }