)]}'
{
  "log": [
    {
      "commit": "c39dac148cce137ffd78a8e43499fba10c5c79e0",
      "tree": "9c97ff18aa9fd4c267e945948e1dbdedc598b723",
      "parents": [
        "857235b3bb21c8868dc74c854c8025ec53782b0c"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Jan 21 08:59:48 2016 -0800"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Jan 21 11:05:41 2016 -0800"
      },
      "message": "Support for x86 popcnt.\n\nChange-Id: I0fc4e745764f1749a6437a199a594f3d8ea53eef\n"
    },
    {
      "commit": "857235b3bb21c8868dc74c854c8025ec53782b0c",
      "tree": "3f5d1816a1e81908120dbcd1cdfb668cd4a8e611",
      "parents": [
        "f3e4c8a7fc306aacf772beef5269ee9a466bea4c",
        "3f67e692860d281858485d48a4f1f81b907f1444"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Thu Jan 21 16:11:17 2016 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Thu Jan 21 16:11:17 2016 +0000"
      },
      "message": "Merge \"Implemented BitCount as an intrinsic. With unit test.\""
    },
    {
      "commit": "9bdf108885a27ba05fae8501725649574d7c491b",
      "tree": "a4ddf98b6cf10b343f15164f18e7089bc54c29ca",
      "parents": [
        "a92ee11b9b0ed4033efc5982269e3c0a075315e0"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Jan 21 12:15:52 2016 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Jan 21 12:19:08 2016 +0000"
      },
      "message": "Revert \"Revert \"Write dex files to oat file early.\"\"\n\nThis reverts commit 919f5536182890d2e03f59b961acf8f7c836ff61.\n\nFix linker error (Mac build):\nReplace inline definition of art::ZipArchive::~ZipArchive()\nwith an out-of-line definition in zip_archive.cc to avoid\ndirect reference to CloseArchive() from libart-compiler due\nto inlining. Note that libart is linked against -lziparchive\nbut libart-compiler is not.\n\nChange-Id: I92620ea0200282ca7ba9b7f61a592cb6468d90d8\n"
    },
    {
      "commit": "3f67e692860d281858485d48a4f1f81b907f1444",
      "tree": "a14d3bdc1416dc3db74983d34a408a8b48cbce9c",
      "parents": [
        "6aadaef35ea52506db61e463910c2520b702ca5e"
      ],
      "author": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Fri Jan 15 14:35:12 2016 -0800"
      },
      "committer": {
        "name": "Aart Bik",
        "email": "ajcbik@google.com",
        "time": "Wed Jan 20 20:14:00 2016 -0800"
      },
      "message": "Implemented BitCount as an intrinsic. With unit test.\n\nRationale:\nRecognizing this important operation as an intrinsic has\nvarious advantages:\n(1) having the no-side-effects/no-throw allows for\n    much more GVN/LICM/BCE.\n(2) Some architectures, like x86_64, provide direct\n    support for this operation.\n\nPerformance improvements on X86_64:\nCheckersEvalBench (32-bit bitboard): 27,210KNS -\u003e 36,798KNS  \u003d  + 35%\nReversiEvalBench  (64-bit bitboard): 52,562KNS -\u003e 89,086KNS  \u003d  + 69%\n\nChange-Id: I65d549b0469b7909b12c6611cdc34a8640a5751f\n"
    },
    {
      "commit": "919f5536182890d2e03f59b961acf8f7c836ff61",
      "tree": "8e8b9c330ae9c886611c6e5ae598e21d9b3ea17a",
      "parents": [
        "625a64aad13905d8a2454bf3cc0e874487b110d5"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Jan 20 19:13:01 2016 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Jan 20 19:13:01 2016 +0000"
      },
      "message": "Revert \"Write dex files to oat file early.\"\n\nThis reverts commit 625a64aad13905d8a2454bf3cc0e874487b110d5.\n\nBreaks the Mac build:\n\nUndefined symbols for architecture i386:\n  \"_CloseArchive\", referenced from:\n      ... in oat_writer.o\nld: symbol(s) not found for architecture i386\n\nChange-Id: I21608bc51437834e1e6abde9bcbe5e7d9998197e\n"
    },
    {
      "commit": "625a64aad13905d8a2454bf3cc0e874487b110d5",
      "tree": "49035d031166ce9fe0c5dd2f4b34157100e1703f",
      "parents": [
        "e1b0f475e851072d0083faf6e07d274e9f1fe6a5"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Nov 26 14:44:16 2015 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Jan 15 12:28:06 2016 +0000"
      },
      "message": "Write dex files to oat file early.\n\nWrite dex files to oat file before we actually open and\nverify them. Instead, open and verify the copies from the\noat file and use these. This way, in the most common case\nof zipped dex files, we have mmapped dex files instead of\ninflated dex files. That reduces the number of dirty pages\nused by dex2oat.\n\nReading /proc/self/statm after we write the oat file for\na compilation of a certain large app on Nexus 5 AOSP build\nwith -j1, three attempts before and after this CL gave\n    before: 346061 189462 6269 26 0 140723 0\n            346189 189450 6269 26 0 140851 0\n            346061 189463 6269 26 0 140723 0\n    after:  346186 185808 23040 27 0 140468 0\n            346186 185819 23040 27 0 140468 0\n            346186 185822 23040 27 0 140468 0\nThese values are in pages (4KiB), so while the \"size\"\n(\u003dVmSize) is essentially unchanged, the \"resident\" (\u003dVmRSS)\nis over 14MiB less and the \"shared\" (i.e. backed by a file)\nis 65.5MiB more. That is, the amount of dirty non-pageable\nmemory used is reduced by about 80MiB.\n\nThe oat file format has changed slightly, the class offset\ntable has been moved from the OatDexFile to its own section.\nThis actually fixes the alignment of these offsets as they\ncould have been unaligned previously, yet accessed as normal\nwith significant performance impact if the kernel has to\nemulate the unaligned access (say, mips).\n\nChange-Id: I0f4799bb1f1ca28e3533156a3494f55345c3e10a\n"
    },
    {
      "commit": "8422edd7af342a955f17639ab827cf062ef8965e",
      "tree": "8687cc87bcf04f3d00f4e68fa9a758d99afbc6cb",
      "parents": [
        "f50d7ea29eda80fd405de7f665ea15eafde3dff5",
        "bb9863af3a98622e650de78fb235ab484b50eb1f"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Thu Jan 14 13:09:10 2016 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Thu Jan 14 13:09:10 2016 +0000"
      },
      "message": "Merge \"MIPS32: don\u0027t use R2+ instructions (mthc1, mfhc1) on MIPS32R1 or with 32-bit FPUs.\""
    },
    {
      "commit": "bb9863af3a98622e650de78fb235ab484b50eb1f",
      "tree": "3df79ba309964d56867d23e497322f2a5f3bbeb8",
      "parents": [
        "08d3ab591d98fce33b7ab552a10cec04aaff6ce1"
      ],
      "author": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Mon Jan 11 15:51:16 2016 -0800"
      },
      "committer": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Wed Jan 13 22:47:21 2016 -0800"
      },
      "message": "MIPS32: don\u0027t use R2+ instructions (mthc1, mfhc1) on MIPS32R1 or\nwith 32-bit FPUs.\n\nChange-Id: If66932fb39cdd5946f6c05c82036191ad405a877\n"
    },
    {
      "commit": "baf60b7cceb3968ae36540e2f7f92cec3805f6ed",
      "tree": "97170e2b5ad9439e4d94fb1d86c5b1382ddba0be",
      "parents": [
        "08d3ab591d98fce33b7ab552a10cec04aaff6ce1"
      ],
      "author": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Tue Dec 22 15:15:03 2015 -0800"
      },
      "committer": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Wed Jan 13 17:43:42 2016 -0800"
      },
      "message": "MIPS: Improve conversion between ints and floats.\n\nChange-Id: I767fe9623cc14e8480c31e305725eb5221cac282\n"
    },
    {
      "commit": "3da15f8b1097905e06a59149c3a4a9658cbb7d5e",
      "tree": "1c572d200ee0382b33d33e038b5b228b16c198c0",
      "parents": [
        "a21489e7fa07722d340f69a12921cd7aa9ee4a17",
        "ac6ac10a0801fa6eb95e0ab0c72b2ed562210b34"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Jan 12 12:19:19 2016 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Tue Jan 12 12:19:19 2016 +0000"
      },
      "message": "Merge \"Optimizing/ARM: Fix CmpConstant().\""
    },
    {
      "commit": "a21489e7fa07722d340f69a12921cd7aa9ee4a17",
      "tree": "64c69317176c0ebf83cadb38eff81d6a03327290",
      "parents": [
        "93616c6326b3b2a77ce7a702868e1dcbb69b2651",
        "ef9230b63c66fc17304d45851c3482a25858ab6f"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Jan 12 12:19:03 2016 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Tue Jan 12 12:19:03 2016 +0000"
      },
      "message": "Merge \"Clean up SwapSpace.\""
    },
    {
      "commit": "5f332cbd0cf70edb80d4493a25ac3dabbc69b053",
      "tree": "24667353f97e9d349d1cbcf7e447728ffad68d73",
      "parents": [
        "b7371a5517f78f61759f7e6124f2d957d974d9cd",
        "5c7aed3b9844e240cf785e5885524ac133a04396"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Jan 04 12:21:15 2016 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Mon Jan 04 12:21:15 2016 +0000"
      },
      "message": "Merge \"MIPS32: improvements in code generation (mostly 64-bit ALU ops)\""
    },
    {
      "commit": "6ce017304099d1df97ffa016ce0efce79c67f344",
      "tree": "6c8265acb94f17e78371191809fe67d8101c2c4e",
      "parents": [
        "e38e4b467bdcca1bf5f8b80adc66d3064fa9cf45"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Dec 30 14:10:13 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Dec 30 14:22:11 2015 +0000"
      },
      "message": "On x64, cmpl can never take a int64 immediate.\n\nFix a wrong type widening in x64 code generator and add\nCHECKs in the assembler.\n\nChange-Id: Id35f5d47c6cf78ed07e73ab783db09712d3c437f\n"
    },
    {
      "commit": "ef9230b63c66fc17304d45851c3482a25858ab6f",
      "tree": "07cb45567cbbf3be2b2fe2462d685f1f7c5a5f76",
      "parents": [
        "e74927c0cded59b6687020c6480205d4488a69fc"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Oct 06 13:51:55 2015 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Dec 23 11:57:24 2015 +0000"
      },
      "message": "Clean up SwapSpace.\n\nChange-Id: I14f371b153b83e3cc70b7938fb8be80d99b12b3e\n"
    },
    {
      "commit": "ac6ac10a0801fa6eb95e0ab0c72b2ed562210b34",
      "tree": "3758a1903dbdd273c35d4bae4ee0e820857946c0",
      "parents": [
        "1201804d1813d7db0accead9721d67c40b3de564"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Dec 17 12:14:00 2015 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Dec 22 11:51:33 2015 +0000"
      },
      "message": "Optimizing/ARM: Fix CmpConstant().\n\nCMN updates flags based on addition of its operands.\nDo not confuse the \"N\" suffix with bitwise inversion\nperformed by MVN.\n\nAlso add more special cases analogous to AddConstant()\nand use CmpConstant() more in code generator.\n\nChange-Id: I0d4571770a3f0fdf162e97d4bde56814098e7246\n"
    },
    {
      "commit": "299a93993fb8f3efbf0465cf674d80c3bcfdc66c",
      "tree": "1ba8d1cd2a34091317af08cbbe5cfa3fa52e549f",
      "parents": [
        "fae1db92d8433d0f75258c190bcf2c940731f036"
      ],
      "author": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Tue Dec 08 16:08:02 2015 -0800"
      },
      "committer": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Thu Dec 17 14:14:26 2015 -0800"
      },
      "message": "MIPS64: Fuse long and FP compare \u0026 condition in Optimizing.\n\nBug: 25559148\n\nChange-Id: I2d14ac75460a76848c71c08cffff6d7a18f5f580\n"
    },
    {
      "commit": "0ac7a8e505e14e65ff989c483a40348a3d4b6a86",
      "tree": "293b68b2b751bde83e25d2e005acdfa9b992268b",
      "parents": [
        "ff6ab45547a629b1e237a1bf4b8530a5c99377e5",
        "f5c09c3ed5bca4c34d8476dd9ed2714106fafbcf"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Dec 17 15:14:59 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Thu Dec 17 15:14:59 2015 +0000"
      },
      "message": "Merge \"Optimizing/ARM: Fix AddConstant() to adhere to set_cc.\""
    },
    {
      "commit": "f5c09c3ed5bca4c34d8476dd9ed2714106fafbcf",
      "tree": "6521df348c2fd8d692bb751ed8dffdf70c8f6051",
      "parents": [
        "7f3b38cc23b638ab84ac01a94e90f0456da3b688"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Dec 17 12:08:08 2015 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Dec 17 15:13:39 2015 +0000"
      },
      "message": "Optimizing/ARM: Fix AddConstant() to adhere to set_cc.\n\nAnd improve it to use shorter code sequences.\n\nBug: 26121945\n\nChange-Id: Ia4f1688652c195a7ca19af36d919388a550e2841\n"
    },
    {
      "commit": "5c7aed3b9844e240cf785e5885524ac133a04396",
      "tree": "acc868d1478f0410fda4d0f6de3c60755aa6680e",
      "parents": [
        "1c70f18dce7705ff70147ddebf65a97f66df8d5c"
      ],
      "author": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Wed Nov 25 19:41:54 2015 -0800"
      },
      "committer": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Wed Dec 16 15:33:30 2015 -0800"
      },
      "message": "MIPS32: improvements in code generation (mostly 64-bit ALU ops)\n\nSpecifically:\n- Use the delay slot in InvokeRuntime() for direct entry points\n- Use kNoOutputOverlap wherever possible\n- Improve and/or/xor/add/sub with 64-bit integer constants\n- Improve 64-bit shifts by a constant amount on R2+\n- More efficient load/store of 64-bit constants (especially, 0 \u0026 +0.0)\n\nChange-Id: I86d2217c8b5b8e2a9371effc2ce38b9eec62782b\n"
    },
    {
      "commit": "cd7b0ee296b0462961c63e51d99c9c323e2690df",
      "tree": "57a9071635389e58a8912d98b99d7e114c1efcc6",
      "parents": [
        "0bbc1727c446ee5f4cc3c28e68127164ef379594"
      ],
      "author": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Thu Dec 03 16:46:38 2015 -0800"
      },
      "committer": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Tue Dec 15 14:29:48 2015 -0800"
      },
      "message": "MIPS32: Fuse long and FP compare \u0026 condition in Optimizing.\n\nThis also does a minor clean-up in the assembler and\nits test.\n\nBug: 25559148\nChange-Id: I9bad3c500b592a09013b56745f70752eb284a842\n"
    },
    {
      "commit": "6d0aefdc1f536e093305e29770cf749acb3247e2",
      "tree": "74964d04d6bb0b7a3210b8e414516375cb3fb189",
      "parents": [
        "6247556fb980c5122fc2dd5c431c2b2c0281606d",
        "7e99e054d023af878d6632bc8c8ba07357ded294"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Dec 10 10:54:24 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Thu Dec 10 10:54:24 2015 +0000"
      },
      "message": "Merge \"MIPS32: Improve integer division by constants\""
    },
    {
      "commit": "e0d25b156ef12b23afa2a6493ae703ec82e23475",
      "tree": "06924f7e4b7f14db21fe41ec03a6b95eec29efeb",
      "parents": [
        "763fd2d3d131898cad6295a19ae9a30e22ce5f2a",
        "88b2b80aed15bb1f931cddd40e44ca525ef10018"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Dec 08 16:15:24 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Tue Dec 08 16:15:24 2015 +0000"
      },
      "message": "Merge \"Allow initializing runtime with parsed options.\""
    },
    {
      "commit": "88b2b80aed15bb1f931cddd40e44ca525ef10018",
      "tree": "04b2f9d27863cd469dae8050335f197496f24ff2",
      "parents": [
        "cf6bd55863ded11e0533966657871aca444505a5"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Dec 04 14:19:04 2015 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Dec 07 12:38:21 2015 +0000"
      },
      "message": "Allow initializing runtime with parsed options.\n\nNeeded by upcoming refactoring of dex2oat to allow\nearly writing of dex files to the oat file.\n\nChange-Id: Ia13c26132846801522f181f51f64035d625e8416\n"
    },
    {
      "commit": "5bde68ff34aeb84a1fc84734bcd31471d9a9717c",
      "tree": "ec3e56c3853a785ddb0310c8c13f6bd2ccaed818",
      "parents": [
        "fdacff89f5b5c276254beb5643fda5df16ba7dd3",
        "e16ce5a52da4fcbb8c6b5d1ec696863fcf113409"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Sat Dec 05 02:08:06 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Sat Dec 05 02:08:06 2015 +0000"
      },
      "message": "Merge \"MIPS32: Bit rotation intrinsics\""
    },
    {
      "commit": "e15f6e2d262c53ae616b70024a743604f21b7c42",
      "tree": "965d3d6b52bd4c2563215347c2cfc12bbfffb09d",
      "parents": [
        "bf0e73604f836e3b8f7d6481e83110c3426350b6",
        "e384547851a9d9e5d89ae5bb4c16bfd7d93cc12e"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Sat Dec 05 02:02:13 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Sat Dec 05 02:02:13 2015 +0000"
      },
      "message": "Merge \"MIPS32: int java.lang.*.numberOfLeadingZeros\""
    },
    {
      "commit": "eddbfb74ae5de6b42be9f47da386cd9507eb3e53",
      "tree": "fd10450987d8c314421e3c057ab1c162f4e57f5f",
      "parents": [
        "099f2713ce4ed284c94239cc22d3a8c8d9cfe868",
        "70014c8af8d3a20c2987c308788bc86671bc39e9"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Fri Dec 04 16:28:11 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Fri Dec 04 16:28:11 2015 +0000"
      },
      "message": "Merge \"MIPS32: java.lang.*.reverse\""
    },
    {
      "commit": "b4536b7de576b20c74c612406c5d3132998075ef",
      "tree": "5265c07b51b4d79b2fd64c63d9b78d38b7601a8f",
      "parents": [
        "883ef45b5d5a2e4005914c7b339881900976b6e7"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Nov 24 13:45:23 2015 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Dec 01 11:38:03 2015 +0000"
      },
      "message": "Optimizing/ARM: Implement kDexCachePcRelative dispatch.\n\nChange-Id: I0fe2da50a30a3f62bec8ea01688dd1fec84b1831\n"
    },
    {
      "commit": "e16ce5a52da4fcbb8c6b5d1ec696863fcf113409",
      "tree": "89730bfb9928ff70391f57ac42377be20e9e5bba",
      "parents": [
        "8682960da00c013f8955985b8e9bb6c55b3f3bac"
      ],
      "author": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Wed Nov 18 12:30:20 2015 -0800"
      },
      "committer": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Mon Nov 30 17:28:28 2015 -0800"
      },
      "message": "MIPS32: Bit rotation intrinsics\n\n- int java.lang.Integer.rotateLeft(int i, int distance)\n- int java.lang.Integer.rotateRight(int i, int distance)\n- long java.lang.Long.rotateLeft(long i, int distance)\n- long java.lang.Long.rotateRight(long i, int distance)\n\nChange-Id: I7620ee12562c0dd55476a1d54e225c5e624cfb5b\n"
    },
    {
      "commit": "e384547851a9d9e5d89ae5bb4c16bfd7d93cc12e",
      "tree": "41ba461c62b6a89253b59117a68beae05df5006f",
      "parents": [
        "70014c8af8d3a20c2987c308788bc86671bc39e9"
      ],
      "author": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Wed Nov 18 12:27:15 2015 -0800"
      },
      "committer": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Mon Nov 30 17:27:36 2015 -0800"
      },
      "message": "MIPS32: int java.lang.*.numberOfLeadingZeros\n\n- int java.lang.Integer.numberOfLeadingZeros(int)\n- int java.lang.Long.numberOfLeadingZeros(long)\n\nChange-Id: Icaf746cb807863f944ff4ebb5da6e6b2846eac58\n"
    },
    {
      "commit": "70014c8af8d3a20c2987c308788bc86671bc39e9",
      "tree": "bff8dd184ff7d753ee77802b973ac91fc8bff86b",
      "parents": [
        "1850cb43dbddbc655a6f990a7d475587fa9d6659"
      ],
      "author": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Wed Nov 18 12:26:08 2015 -0800"
      },
      "committer": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Mon Nov 30 15:04:51 2015 -0800"
      },
      "message": "MIPS32: java.lang.*.reverse\n\n- int java.lang.Integer.reverse(int)\n- long java.lang.Long.reverse(long)\n\nChange-Id: I18d0f784b9e4bffdc1bda3604f4ed7d3c57b8d68\n"
    },
    {
      "commit": "7e99e054d023af878d6632bc8c8ba07357ded294",
      "tree": "2c2615326f71612631c3488e0eea7e5e5636fc91",
      "parents": [
        "883ef45b5d5a2e4005914c7b339881900976b6e7"
      ],
      "author": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Tue Nov 24 19:28:01 2015 -0800"
      },
      "committer": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Tue Nov 24 19:28:01 2015 -0800"
      },
      "message": "MIPS32: Improve integer division by constants\n\nChange-Id: I2d1e84e84bdf8d3007cde7c51611ec893a0e9527\n"
    },
    {
      "commit": "51a354c747c8a76a4716a49a1f70bfd975d63787",
      "tree": "37b82929ccc42f4b1b70b94baf64dbd9fd8b4c15",
      "parents": [
        "7f8275549fd503f82ac63d65800afacab85af09d",
        "a0e87b0a97fadd54540ec7e8331b61bebd82d378"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Tue Nov 24 10:34:22 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Tue Nov 24 10:34:22 2015 +0000"
      },
      "message": "Merge \"MIPS64: Support short and long branches\""
    },
    {
      "commit": "f180af0fc0d0bd981dd6356848df2ba237e1a227",
      "tree": "bea248023c5823bbb28a1864655e3afce9226400",
      "parents": [
        "97cd5bb34ca97e7e87a030b2e1acec004fd26275",
        "f9d741e32c6f1629ce70eefc68d3363fa1cfd696"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Nov 23 11:20:35 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Mon Nov 23 11:20:35 2015 +0000"
      },
      "message": "Merge \"Optimizing/ARM: Improve long shifts by 1.\""
    },
    {
      "commit": "97cd5bb34ca97e7e87a030b2e1acec004fd26275",
      "tree": "f32f550f026709bba83d2585d3a121eb5e01a131",
      "parents": [
        "dde8b8694954c0268eb12a7ccbddf07d9de262fd",
        "6fd0ffe8da212723a3ac0256ce350b5872cc61d4"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Nov 23 10:15:01 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Mon Nov 23 10:15:01 2015 +0000"
      },
      "message": "Merge \"Optimizing/Thumb2: Improve load/store for large offsets.\""
    },
    {
      "commit": "a0e87b0a97fadd54540ec7e8331b61bebd82d378",
      "tree": "c1027e65fd859cf59f295ff3a5630404e3724db3",
      "parents": [
        "d83b9042d67f2a7d5ca5a1f63819c97940033336"
      ],
      "author": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Thu Sep 24 22:57:20 2015 -0700"
      },
      "committer": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Sat Nov 21 22:18:50 2015 -0800"
      },
      "message": "MIPS64: Support short and long branches\n\nChange-Id: I618c960bd211048166d9fde78d4106bd3ca42b3a\n"
    },
    {
      "commit": "e3dbda2d7c6a9bb0ca9a38f049457382247ed639",
      "tree": "d3063bdd9901aa73c6d51f230566a833b534db8d",
      "parents": [
        "bfc9d5103b7764a6863d5bd944afeb6a7e520468",
        "3f8bf65f36e14650bb6eb6876a42d9344a9d64d9"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Fri Nov 20 21:27:59 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Fri Nov 20 21:27:59 2015 +0000"
      },
      "message": "Merge \"MIPS32: Miscellaneous bit manipulations routines:\""
    },
    {
      "commit": "f9d741e32c6f1629ce70eefc68d3363fa1cfd696",
      "tree": "409005e5b1d01d2830c20421f8466125e110d6af",
      "parents": [
        "beb709a2607a00b5df33f0235f22ccdd876cee22"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Nov 20 15:08:11 2015 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Nov 20 16:18:39 2015 +0000"
      },
      "message": "Optimizing/ARM: Improve long shifts by 1.\n\nImplement long\n    Shl(x,1) as LSLS+ADC,\n    Shr(x,1) as ASR+RRX and\n    UShr(x,1) as LSR+RRX.\n\nRemove the simplification substituting Shl(x,1) with\nADD(x,x) as it interferes with some other optimizations\ninstead of helping them. And since it didn\u0027t help 64-bit\narchitectures anyway, codegen is the correct place for it.\nThis is now implemented for ARM and x86, so only mips32 can\nbe improved.\n\nChange-Id: Idd14f23292198b2260189e1497ca5411b21743b3\n"
    },
    {
      "commit": "6fd0ffe8da212723a3ac0256ce350b5872cc61d4",
      "tree": "122c89d874460662d3feba523cb9f2553fb78bd3",
      "parents": [
        "beb709a2607a00b5df33f0235f22ccdd876cee22"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Nov 19 21:13:52 2015 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Nov 20 11:55:49 2015 +0000"
      },
      "message": "Optimizing/Thumb2: Improve load/store for large offsets.\n\nThis reduces the boot.oat size on Nexus 5 by 568KiB (0.8%).\n\nAlso change 32-bit ADD/SUB immediate to use the recommended\nencoding T3 when both T3 and T4 are available.\n\nChange-Id: I174382bda2b22da70560b947f5536acf8c1814a9\n"
    },
    {
      "commit": "3f8bf65f36e14650bb6eb6876a42d9344a9d64d9",
      "tree": "2cca6628f091f02775519b6610d1cd176ea1327b",
      "parents": [
        "f66f05ddfceaa8a2f613d3ed8316a21c95e1fbca"
      ],
      "author": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Wed Oct 28 10:08:56 2015 -0700"
      },
      "committer": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Wed Nov 18 12:24:59 2015 -0800"
      },
      "message": "MIPS32: Miscellaneous bit manipulations routines:\n\n- short java.lang.Short.reverseBytes(short)\n- int java.lang.Integer.reverseBytes(int)\n- long java.lang.Long.reverseBytes(long)\n- float java.lang.Float.intBitsToFloat(int)\n- double java.lang.Double.longBitsToDouble(long)\n- int java.lang.Float.floatToRawIntBits(float)\n- long java.lang.Double.doubleToRawLongBits(double)\n\nChange-Id: Id9803349d465c28756820e90e2cbe633f3f40a44\n"
    },
    {
      "commit": "2264f624e41acf09b17c3961bd52966e43f2b58f",
      "tree": "b946c5ffdca5399408fc0769edb12762980087b8",
      "parents": [
        "4202a2ff49d77eda813052d091675bf53c46cb0f",
        "5c75ffad3aaf9d62ea3ac4cf2c0a2fd699368f83"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Sat Nov 07 14:15:46 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Sat Nov 07 14:15:46 2015 +0000"
      },
      "message": "Merge \"MIPS64: small improvements in code generation\""
    },
    {
      "commit": "5c75ffad3aaf9d62ea3ac4cf2c0a2fd699368f83",
      "tree": "15da165b06f99c55849e5431d8b405c2014883dc",
      "parents": [
        "b203aad7a0db904efa8429d48b53e56583f61ec2"
      ],
      "author": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Thu Sep 24 14:41:59 2015 -0700"
      },
      "committer": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Fri Nov 06 13:13:47 2015 -0800"
      },
      "message": "MIPS64: small improvements in code generation\n\nSpecifically:\n- More efficient load/store of constant 0 (and +0.0)\n- Improved swapping of floats/doubles in registers\n- Use kNoOutputOverlap wherever possible\n- More efficient 64-bit integer comparison with 0\n- More efficient load of integer constants of the form (2**n)-1\n\nChange-Id: Ic2914d8865aa6616b9a0b21b3cc173d4477eb8c7\n"
    },
    {
      "commit": "c857c746707dfd45d74b75cb7fa84484ca68cc2a",
      "tree": "0c223c9cb4999ffe9b04b3e264f5fea4c91d949a",
      "parents": [
        "b203aad7a0db904efa8429d48b53e56583f61ec2"
      ],
      "author": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Wed Sep 23 15:12:39 2015 -0700"
      },
      "committer": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Fri Nov 06 13:03:43 2015 -0800"
      },
      "message": "MIPS64: Improve integer division by constants\n\nThis also removes some unused instructions and instructions not\navailable on MIPS64R6.\n\nChange-Id: I44bfe12c60344312c88c45e97b6b07dcd5bdc630\n"
    },
    {
      "commit": "10ef6941648aad04d54527d4a7a6070bf7065e88",
      "tree": "50fe6b50a3020ec7d25fbd5e4393db1c04452ce7",
      "parents": [
        "c74e69f831608964f89ac7a641fbcc09156eefaa"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Oct 22 15:25:54 2015 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Nov 04 14:54:23 2015 +0000"
      },
      "message": "Delay emitting CFI PC adjustments until after Thumb2/Mips fixup.\n\nOn Mips also take into account out-of-order CFI data emitted\nfrom EmitBranches().\n\nChange-Id: I03b0b0b4c2b1ea31a02699ef5fa1c55aa42c23c3\n"
    },
    {
      "commit": "c74e69f831608964f89ac7a641fbcc09156eefaa",
      "tree": "284112345185cd3ef21feaeaa6060606cfbbbda8",
      "parents": [
        "564420bc5b37572d45067fd71ed64d818ef3030d",
        "7cffc3b0004d32faffc552c0a59286f369b21504"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Fri Oct 30 18:17:00 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Fri Oct 30 18:17:00 2015 +0000"
      },
      "message": "Merge \"ART: Arm32 packed-switch jump tables\""
    },
    {
      "commit": "7cffc3b0004d32faffc552c0a59286f369b21504",
      "tree": "e3838b8ba2a782ed91ef8faa381362b7a686a32a",
      "parents": [
        "9e1b56f0e77aa5b6c72374b86d0cef58484ddcaa"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Mon Oct 19 21:31:53 2015 -0700"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Fri Oct 30 11:15:26 2015 -0700"
      },
      "message": "ART: Arm32 packed-switch jump tables\n\nAdd jump table support to the thumb2 assembler. Jump tables are\na collection of labels for the case targets, and an anchor label\ndenoting the position of the jump.\n\nUse the jump table support to implement packed-switch support for\narm32.\n\nAdd tests for BindTrackedLabel and JumpTable to the thumb2 assembler\ntest.\n\nBug: 24092914\nChange-Id: I5c84f193dfebf9e07f48678efc8bd151bb1410dd\n"
    },
    {
      "commit": "9f51f26b815fb955a3b91df86d54acd3f41480e4",
      "tree": "a22b5526f9c7f077c042b10416d1155df08fe748",
      "parents": [
        "13f6af0f9c8af1fce34e9610ad9d30d4d0434478"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Fri Oct 30 09:21:37 2015 -0400"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Fri Oct 30 09:21:37 2015 -0400"
      },
      "message": "X86: Add support for ucomis[sd] reg/memory form\n\nAllow an Address as the second operand.\n\nChange-Id: I4940829e2e4bfe0cddef3808265fdb638ac07b7e\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "35831e8bfa1c0944d4c978d99c4c5b9577945170",
      "tree": "a347ecaf4265a1713c86d528392e162d5edfaebc",
      "parents": [
        "171b12e8060f63cf900ffc43d6db35125f6b8c83"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Sep 11 11:59:18 2015 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Oct 27 15:13:37 2015 +0000"
      },
      "message": "Reduce memory used by CompiledMethods.\n\nUse LengthPrefixedArray\u003c\u003es instead of SwapVector\u003c\u003es to store\nCompiledMethod data and get rid of the unnecessary members\nof CompiledMethod to reduce dex2oat memory usage. Refactor\nthe deduplication from CompilerDriver to a new class.\n\nUse HashSet\u003c\u003e instead of std::set\u003c\u003e for the DedupeSet\u003c\u003e to\nfurther decrease the memory usage and improve performance.\n\nThis reduces the dex2oat memory usage when compiling boot\nimage on Nexus 5 (with Optimizing, -j1) by ~6.75MiB (5%).\nThis also reduces the compile time by ~2.2% (~1.6% dex2oat\ntime; with Optimizing, without -j).\n\nChange-Id: I974f1f5e58350de2bf487a2bca3907fa05fb80ea\n"
    },
    {
      "commit": "e5d80f83ae53792bc1eebd4e33e4e99f7c031b0c",
      "tree": "cc21ac068a5d02349c5b1aaa8c7f61ae777f6cea",
      "parents": [
        "a815f17cc82f4f238d8bdec1bd5b70fec720541e"
      ],
      "author": {
        "name": "Mathieu Chartier",
        "email": "mathieuc@google.com",
        "time": "Thu Oct 15 17:47:48 2015 -0700"
      },
      "committer": {
        "name": "Mathieu Chartier",
        "email": "mathieuc@google.com",
        "time": "Fri Oct 23 11:21:11 2015 -0700"
      },
      "message": "Move ArenaBitVector into the runtime\n\nMotivation is using arenas in the verifier.\n\nBug: 10921004\nChange-Id: I3c7ed369194b2309a47b12a621e897e0f2f65fcf\n"
    },
    {
      "commit": "98a73e14554301ccd6d05f8a893b59b1d8b5eaeb",
      "tree": "b7bb13c49b3827d6e1d2f6401b3e6b64a0b69e9d",
      "parents": [
        "b1f10f51bf6b7fb48cca83471862150ceb74fd92"
      ],
      "author": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Mon Oct 19 14:17:16 2015 -0700"
      },
      "committer": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Tue Oct 20 10:55:52 2015 -0700"
      },
      "message": "MIPS64: Add tests for rotation, and shift instructions\n\nChange-Id: I5611cb5c638c6be193739cbe859cb4ff4074a5fa\n"
    },
    {
      "commit": "9aebff2f19b605bff864308be51b604b7191163e",
      "tree": "78a49ebd0052617c3bd7d0bc17ec0b9d3fd206a0",
      "parents": [
        "a5903e622c0c11c1513a62e128a26d3cefd16c6f"
      ],
      "author": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Tue Sep 22 17:54:15 2015 -0700"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Mon Oct 19 08:14:04 2015 -0700"
      },
      "message": "MIPS64: Add intrinsic support for bit rotation\n\n- int java.lang.Integer.rotateRight(int i, int distance)\n- int java.lang.Long.rotateRight(long i, int distance)\n\nAssembler tests for new MIPS instructions will be provided in a\nseparate patch.\n\nChange-Id: I6dd4786e2d5f674bf56ff3d5afd321bb1bef589e\n"
    },
    {
      "commit": "c4daa0a06cf0b7c1e7b0440fb7e9a06b018b52ff",
      "tree": "99bcea01770e8fed2ec41cd0f7f86a92a81db303",
      "parents": [
        "4b0ef9c9246435da48203e9f273717d81a1ffe2a",
        "5141763acd9ca2ddb2ee6bcc742d6d2a2aebd7df"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Fri Oct 16 22:17:56 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Fri Oct 16 22:17:56 2015 +0000"
      },
      "message": "Merge \"MIPS64: Additional assember tests:\""
    },
    {
      "commit": "4b8f1ecd3aa5a29ec1463ff88fee9db365f257dc",
      "tree": "d113f8a5c6b61c078256cf15c7cbb9f7c8de0390",
      "parents": [
        "114873103db3d4d6e0da42ca02bad1ea8826443b"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Wed Aug 26 18:34:03 2015 +0100"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Thu Oct 15 12:22:39 2015 -0700"
      },
      "message": "Use ATTRIBUTE_UNUSED more.\n\nUse it in lieu of UNUSED(), which had some incorrect uses.\n\nChange-Id: If247dce58b72056f6eea84968e7196f0b5bef4da\n"
    },
    {
      "commit": "943e89e4000189473d1e82e1e395875ea9452431",
      "tree": "57c352acb5cb11b056e301e5615f59c56802c870",
      "parents": [
        "392835deba1c62fd8858333db55ea2b5e6f53ceb",
        "805b3b56c6eb542298db33e0181f135dc9fed3d9"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Oct 14 17:21:56 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Wed Oct 14 17:21:56 2015 +0000"
      },
      "message": "Merge \"X86 jump tables for PackedSwitch\""
    },
    {
      "commit": "392835deba1c62fd8858333db55ea2b5e6f53ceb",
      "tree": "b58656f612addadebd4ae1294e9281073e423247",
      "parents": [
        "644044333f5f6d7ba7e327619ac0d0ce4e2609d3",
        "9c86b485bc6169eadf846dd5f7cdf0958fe1eb23"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Oct 14 17:19:09 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Wed Oct 14 17:19:09 2015 +0000"
      },
      "message": "Merge \"X86_64 jump tables for PackedSwitch\""
    },
    {
      "commit": "805b3b56c6eb542298db33e0181f135dc9fed3d9",
      "tree": "664d3ca2039805aa326c9e5e02dfae703ba7e634",
      "parents": [
        "df3456007702b0dea01ffd1adfa74244857712af"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Fri Sep 18 14:10:29 2015 -0400"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Wed Oct 14 09:54:31 2015 -0400"
      },
      "message": "X86 jump tables for PackedSwitch\n\nImplement X86PackedSwitch using a jump table of offsets to blocks. The\nX86PackedSwitch version just adds an input to address the constant area.\n\nChange-Id: Id2752a1ee79222493040c6fd0e59aee9a544b76a\nBug: 21119474\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "9c86b485bc6169eadf846dd5f7cdf0958fe1eb23",
      "tree": "83196e6888b6fca881bfb63bb0e007453a2821ed",
      "parents": [
        "df3456007702b0dea01ffd1adfa74244857712af"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Fri Sep 18 13:36:07 2015 -0400"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Wed Oct 14 08:50:07 2015 -0400"
      },
      "message": "X86_64 jump tables for PackedSwitch\n\nImplement PackedSwitch using a jump table of offsets to blocks.\n\nBug: 24092914\nBug: 21119474\nChange-Id: I83430086c03ef728d30d79b4022607e9245ef98f\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "644044333f5f6d7ba7e327619ac0d0ce4e2609d3",
      "tree": "9adfec0dc75c7a6acce2ea53cf1348d264c40759",
      "parents": [
        "045a95cf3cb91fd72b5982c67757175f1091cc7d",
        "d2b4ca2d02c86b1ce1826fd2b35ce6c9c58c1ff1"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Oct 14 11:34:02 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Wed Oct 14 11:34:02 2015 +0000"
      },
      "message": "Merge \"Improve Thumb2 bitwise operations.\""
    },
    {
      "commit": "d2b4ca2d02c86b1ce1826fd2b35ce6c9c58c1ff1",
      "tree": "dab4cdfacd3e7cb529f3b0de931c8a173039571f",
      "parents": [
        "fb11bab9bc96ff05dcb12f43abf58df256b7c7aa"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Sep 14 15:13:26 2015 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Oct 14 12:20:59 2015 +0100"
      },
      "message": "Improve Thumb2 bitwise operations.\n\nAllow embedding constants in AND, ORR, EOR. Add ORN to\nassembler, use BIC and ORN for AND and ORR when needed.\n\nChange-Id: I24d69ecc7ce6992b9c5eb7a313ff47a942de9661\n"
    },
    {
      "commit": "0ccb383d2fa7f9929830a816c7fe159b09ddb92d",
      "tree": "180a184a9d834b82a2bd04f7a30154617e87d37a",
      "parents": [
        "d17bd22d45587a0b2b8646346be6ffde2ab66bd0"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Oct 14 11:44:23 2015 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Oct 14 11:44:23 2015 +0100"
      },
      "message": "Fix braino in arm assembler.\n\nMethod is pure virtual. Caught by clang.\n\nChange-Id: I061666ec919702fa7c30e9a98161cad56a9c864d\n"
    },
    {
      "commit": "26a896aab0b20f7f92e441c2db6f742197379ed0",
      "tree": "848ab1155df6bf829bca234e972bfb44c5413e00",
      "parents": [
        "e9c1f1df05995fd1a47dcb680ccdbf01af9a2651",
        "5bd05a5c9492189ec28edaf6396d6a39ddf03367"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Oct 14 09:01:21 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Wed Oct 14 09:01:21 2015 +0000"
      },
      "message": "Merge \"Implement System.arraycopy intrinsic for arm.\""
    },
    {
      "commit": "5bd05a5c9492189ec28edaf6396d6a39ddf03367",
      "tree": "186488cafe4d815ab834097e91c75f2c20009e2b",
      "parents": [
        "439ffb8d4fa25b4ac7518a3bd5cbc3f3769ead48"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Oct 13 09:48:30 2015 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Oct 13 17:29:19 2015 +0100"
      },
      "message": "Implement System.arraycopy intrinsic for arm.\n\nChange-Id: I58ae1af5103e281fe59fbe022b718d6d8f293a5e\n"
    },
    {
      "commit": "e3c4fcfa81a100b5f6c0dbf58bd084d0938c1558",
      "tree": "5cf5fcf3d950d84b649e3556595c494e6ace586c",
      "parents": [
        "b30c3b2332c60261d54a3741f49f6c6461b23ea4",
        "8c434dcc78d497e18590461700894d1c3e96013d"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Oct 13 07:54:16 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Tue Oct 13 07:54:16 2015 +0000"
      },
      "message": "Merge \"MIPS: Assemblers changes needed for optimizing compiler\""
    },
    {
      "commit": "ec7802a102d49ab5c17495118d4fe0bcc7287beb",
      "tree": "08649609604b9c96bc48ca071c48b0af5abb1a3f",
      "parents": [
        "b2e436ffcda1d7a87e7bf9133d8ed878388c73c2"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Oct 01 20:57:57 2015 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Oct 08 11:10:18 2015 +0100"
      },
      "message": "Add DCHECKs to ArenaVector and ScopedArenaVector.\n\nImplement dchecked_vector\u003c\u003e template that DCHECK()s element\naccess and insert()/emplace()/erase() positions. Change the\nArenaVector\u003c\u003e and ScopedArenaVector\u003c\u003e aliases to use the new\ntemplate instead of std::vector\u003c\u003e. Remove DCHECK()s that\nhave now become unnecessary from the Optimizing compiler.\n\nChange-Id: Ib8506bd30d223f68f52bd4476c76d9991acacadc\n"
    },
    {
      "commit": "7532401fbb3602cc6831b5f9a809c0e88d1daa83",
      "tree": "f6300733d5bcac9f2882374254a55df8c8d1b42f",
      "parents": [
        "8c812b71552a8a1b2bf06e430d355b12b7084807"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Tue Oct 06 18:59:08 2015 -0700"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Wed Oct 07 09:26:30 2015 -0700"
      },
      "message": "ART: Change asm test logging\n\nAdapt the output a bit to log the exact shell command, and change\nhow the output is logged and what is logged. Should get more info\non failure.\n\nChange-Id: Iacf58d27d6e1cf01e2fcd5835c4e0f8b5a820501\n"
    },
    {
      "commit": "5141763acd9ca2ddb2ee6bcc742d6d2a2aebd7df",
      "tree": "06d19a307944ab61506628514d7bb6f8c95ce14e",
      "parents": [
        "bcb71a2ce5bcb516f76fc9fe838b61b0c48e1210"
      ],
      "author": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Fri Oct 02 13:24:25 2015 -0700"
      },
      "committer": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Tue Oct 06 10:39:18 2015 -0700"
      },
      "message": "MIPS64: Additional assember tests:\n\n- MOV.fmt       - NEG.fmt       - CVT.D.fmt     - CVT.S.fmt\n- JALR          - SLL           - SRL           - SRA\n- DSLL          - DSRA          - DSRL          - DSLL32\n- DSRL32        - DSRA32\n\nChange-Id: Ib15ac72128805a9bca707211359191e32d95d5d7\n"
    },
    {
      "commit": "f3e070675f0a80de8a876689f70eb075d2b42947",
      "tree": "7daa9ea7a9cb67fbe6efb71a30d361476003a9f6",
      "parents": [
        "bcb71a2ce5bcb516f76fc9fe838b61b0c48e1210"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Tue Oct 06 09:05:10 2015 -0700"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Tue Oct 06 09:24:25 2015 -0700"
      },
      "message": "ART: Add more error logging to assembler tests\n\nAdd error logging so we can figure out when something goes wrong\non the build servers.\n\nChange-Id: Idf9bc1d0e19846059d1dc78510be6333179cd758\n"
    },
    {
      "commit": "8c434dcc78d497e18590461700894d1c3e96013d",
      "tree": "6fc88cc839c0415aa90a1bbff25e93a09705d19b",
      "parents": [
        "35ef974da353b13938fb0f3272c03070ad728431"
      ],
      "author": {
        "name": "Goran Jakovljevic",
        "email": "Goran.Jakovljevic@imgtec.com",
        "time": "Wed Aug 26 14:39:44 2015 +0200"
      },
      "committer": {
        "name": "Goran Jakovljevic",
        "email": "Goran.Jakovljevic@imgtec.com",
        "time": "Tue Oct 06 16:34:25 2015 +0200"
      },
      "message": "MIPS: Assemblers changes needed for optimizing compiler\n\nAlso add assembler tests for MIPS32.\n\nChange-Id: I3ab1fba7f3b06eb3b5058861946d675494a30775\n"
    },
    {
      "commit": "dbce0d738e9d7956d2bd73e932a0fdd28f2229b4",
      "tree": "336a92e522c4f20386f65f2a34534f982cf28089",
      "parents": [
        "002117f95896ffa5db74bee808ae61e876b6e8b0"
      ],
      "author": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Thu Sep 17 13:34:00 2015 -0700"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Mon Oct 05 18:12:30 2015 -0700"
      },
      "message": "MIPS64r6 Assembler Tests\n\nAssembler tests for:\n\n- SQRT.fmt    - ABS.fmt     - ROUND.L.fmt - ROUND.W.fmt\n- CEIL.L.fmt  - CEIL.W.fmt  - FLOOR.L.fmt - FLOOR.W.fmt\n- SEL.fmt     - RINT.fmt    - CLASS.fmt   - MIN.fmt\n- MAX.fmt     - cvt.d.l     - BITSWAP     - DBITSWAP\n- DSBH        - DSHD        - WSBH        - ROTR\n- SELEQZ      - SELNEZ      - CLZ         - CLO\n- DCLZ        - DCLO        - SC          - SCD\n- LL          - LLD\n\nThese are the assembler instructions which were added to support\nintrinsic functions on MIPS64. Tests for additional assembler\ninstructions will follow.\n\nSupport added to the testing infrastructure for:\n\n- Assembler instructions which use three registers; previously\n  instructions were limited to one, or two, registers.\n- Immediate values which have their sizes specified by the number of\n  bits required to store them rather than the number of bytes, in both\n  signed and unsigned versions.\n\nChange-Id: I38c07dcbf2539825b25bed13aac05a26fa594b0b\n"
    },
    {
      "commit": "145008296e80b8ac5affa4fb9bc20e411bf0bd92",
      "tree": "5e605ad90d097c015f0355acf9d846b1ce90e916",
      "parents": [
        "5df7f784407e963280c4fc2bca18b17834b0f268"
      ],
      "author": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Thu Oct 01 11:35:18 2015 -0700"
      },
      "committer": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Thu Oct 01 11:41:25 2015 -0700"
      },
      "message": "MIPS64: Code cleanup.\n\n1. Add comment to explain logic for GenMinMax in intrinsics code.\n2. Declare enumerated type for class.s/class.d mask values.\n3. Change intrinsics code to use the enumerated values described in\n   item 2.\n4. Change \"CLASS_MASK\" to \"kFPLeaveUnchanged\" to match ART coding\n   standards.\n\nChange-Id: Ib1fe4b01515595b46e5f101e0082bb9bbcf0c688\n"
    },
    {
      "commit": "225b6464a58ebe11c156144653f11a1c6607f4eb",
      "tree": "3f1c6067c3841c892edaa1a60a61af9c559cb4e4",
      "parents": [
        "6a9984e62c08bcd78c8e49dd40b1f0f9d53513b7"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Sep 28 12:17:40 2015 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Sep 29 10:49:35 2015 +0100"
      },
      "message": "Optimizing: Tag arena allocations in code generators.\n\nAnd completely remove the deprecated GrowableArray.\n\nReplace GrowableArray with ArenaVector in code generators\nand related classes and tag arena allocations.\n\nLabel arrays use direct allocations from ArenaAllocator\nbecause Label is non-copyable and non-movable and as such\ncannot be really held in a container. The GrowableArray\nnever actually constructed them, instead relying on the\nzero-initialized storage from the arena allocator to be\ncorrect. We now actually construct the labels.\n\nAlso avoid StackMapStream::ComputeDexRegisterMapSize() being\npassed null references, even though unused.\n\nChange-Id: I26a46fdd406b23a3969300a67739d55528df8bf4\n"
    },
    {
      "commit": "211c2119dc8932bdb264fae858adba6c0541ce3c",
      "tree": "95dd0a75f9bd6745cf7bee4686dd612e353b5301",
      "parents": [
        "0aeb7599bcd7073a5c849f413fb7a9611f5944eb"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Sep 24 16:52:33 2015 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Sep 25 12:28:37 2015 +0100"
      },
      "message": "Optimizing: Rewrite DCE\u0027s MarkReachableBlocks().\n\nReplace a recursive implementation with a loop using a work\nlist to avoid stack overflow that we would presumably hit\nfor 702-LargeBranchOffset in host debug build with -O0, once\nthe DCE block elimination is enabled for methods containing\ntry-catch.\n\nBug: 24133462\nChange-Id: I41288ba368722bcb5d68259c7c147552c8928099\n"
    },
    {
      "commit": "7bfd7ee880785ef383f6434eb4eb35fcaac5ad5a",
      "tree": "42b5d6ea600edac939677ee8e021d91ac12da1c0",
      "parents": [
        "819a9c5638b6d6b579c89fe36df96acc1f378182",
        "46fe0650be6a69f63b54c0967194350c6a145557"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Sep 18 13:51:30 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Fri Sep 18 13:51:30 2015 +0000"
      },
      "message": "Merge \"Fix x64\u0027s cmpw.\""
    },
    {
      "commit": "46fe0650be6a69f63b54c0967194350c6a145557",
      "tree": "951c08c8993ad0da72dd96a651617a00a00d102e",
      "parents": [
        "46aa836b632b5f01e8b4c8e5d8eed2199e8f35d0"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Sep 18 14:36:49 2015 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Sep 18 14:47:38 2015 +0100"
      },
      "message": "Fix x64\u0027s cmpw.\n\nChange-Id: If700f2994990864c8b34aa52eb7a767153a1f917\n"
    },
    {
      "commit": "85b62f23fc6dfffe2ddd3ddfa74611666c9ff41d",
      "tree": "c916b01b1608558a7d8c9d100274c4c6b6706386",
      "parents": [
        "6766eae2d91e894b4ceab9f29cc983900e7bc0c7"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Wed Sep 09 13:15:38 2015 -0700"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Thu Sep 17 14:41:52 2015 -0700"
      },
      "message": "ART: Refactor intrinsics slow-paths\n\nRefactor slow paths so that there is a default implementation for\ncommon cases (only arm64 with vixl is special). Write a generic\nintrinsic slow-path that can be reused for the specific architectures.\nMove helper functions into CodeGenerator so that they are accessible.\n\nChange-Id: Ibd788dce432601c6a9f7e6f13eab31f28dcb8550\n"
    },
    {
      "commit": "e295be4a95d7861f6ec179edf6565f58cad747cc",
      "tree": "a994a7f270e8dd81e3bb1a704c4ee5f6ea98aa7c",
      "parents": [
        "9ea4a93674b42f213334bb83d1982db11091b96a",
        "2fadd7bb67abf5bc3c5370f9508cfb5959d6e536"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Wed Sep 16 04:21:39 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Wed Sep 16 04:21:39 2015 +0000"
      },
      "message": "Merge \"Additional MIPS64 instructions needed by intrinsics code.\""
    },
    {
      "commit": "bcee092d7b0cbb7181d428115ad98d25ce844061",
      "tree": "dab00e7f7dc19b002948020a8c2cbde665203c0e",
      "parents": [
        "b505997b2176bd29a108cb6c33d06d4ef29ba001"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Tue Sep 15 21:45:01 2015 -0400"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Tue Sep 15 21:45:01 2015 -0400"
      },
      "message": "Add X86 bsf and rotate instructions\n\nThese are for use in new intrinsics.  Bsf (Bit Scan Forward) is used in\n{Long,Integer}NumberOfTrailingZeros and the rotates are used in\n{Long,Integer}Rotate{Left,Right}.\n\nChange-Id: Icb599d7e1eec4e4ea9e5b4f0b1654c7b8d4de678\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "0600cdc1d283190f86a3b84b7f5374c1af62112b",
      "tree": "2e09fc067eac743318901d4ffd14a7d54ad5e7d0",
      "parents": [
        "8f5d2d84efb90e7220dd42c7aa104dbc19c52f4e"
      ],
      "author": {
        "name": "Pirama Arumuga Nainar",
        "email": "pirama@google.com",
        "time": "Mon Sep 14 11:00:16 2015 -0700"
      },
      "committer": {
        "name": "Pirama Arumuga Nainar",
        "email": "pirama@google.com",
        "time": "Mon Sep 14 11:00:16 2015 -0700"
      },
      "message": "Remove unnecessary std::move from test_dex_file_builder\n\nThis stops Clang from warning about -Wpessimizing-move.\n\nChange-Id: Id40acf1c398c615faf6486ef700df6975a5f013f\n"
    },
    {
      "commit": "619552b8007c157ca494f1b6355c0a388456b5b1",
      "tree": "42d2917b3b3e81bfd14120d0209e99e9f3b420ff",
      "parents": [
        "1d76bfe710629a4f18bb79a9188f6eb4d9b2e4f4",
        "9ee23f4273efed8d6378f6ad8e63c65e30a17139"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Sep 11 13:20:10 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Fri Sep 11 13:20:10 2015 +0000"
      },
      "message": "Merge \"ARM/ARM64: Intrinsics - numberOfTrailingZeros, rotateLeft, rotateRight\""
    },
    {
      "commit": "9ee23f4273efed8d6378f6ad8e63c65e30a17139",
      "tree": "3b1bfb8a6260a57ccb2f025fcdc457464714701e",
      "parents": [
        "62ba40149be3d1c65e4db1f455822a585149d32f"
      ],
      "author": {
        "name": "Scott Wakeling",
        "email": "scott.wakeling@linaro.org",
        "time": "Thu Jul 23 10:44:35 2015 +0100"
      },
      "committer": {
        "name": "Scott Wakeling",
        "email": "scott.wakeling@linaro.org",
        "time": "Fri Sep 11 09:51:58 2015 +0100"
      },
      "message": "ARM/ARM64: Intrinsics - numberOfTrailingZeros, rotateLeft, rotateRight\n\nChange-Id: I2a07c279756ee804fb7c129416bdc4a3962e93ed\n"
    },
    {
      "commit": "2fadd7bb67abf5bc3c5370f9508cfb5959d6e536",
      "tree": "efdfc90c1cdb4b688c0cdf6c2cf2cfe7b8121d1c",
      "parents": [
        "010c7fd437932e0132fc4b44de6274480573ff30"
      ],
      "author": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Fri Aug 14 14:56:10 2015 -0700"
      },
      "committer": {
        "name": "Chris Larsen",
        "email": "chris.larsen@imgtec.com",
        "time": "Thu Sep 10 10:59:11 2015 -0700"
      },
      "message": "Additional MIPS64 instructions needed by intrinsics code.\n\nChange-Id: If2a48300aac7a10dadf485d1765fb5bdeed975fe\n"
    },
    {
      "commit": "0616ae081e648f4b9b64b33e2624a943c5fce977",
      "tree": "20db99d802277cce68f88eda918ae7646383ff14",
      "parents": [
        "e6576390f957c82c2aede438834d028066757368"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Fri Apr 17 12:49:27 2015 -0400"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Tue Sep 08 17:01:05 2015 -0400"
      },
      "message": "[optimizing] Add support for x86 constant area\n\nUse the Quick trick of finding the address of the method by calling the\nnext instruction and popping the return address into a register.  This\ntrick is used because of the lack of PC-relative addressing in 32 bit\nmode on the X86.\n\nAdd a HX86ComputeBaseMethodAddress instruction to trigger generation\nof the method address, which is referenced by instructions needing\naccess to the constant area.\n\nAdd a HX86LoadFromConstantTable instruction that takes a\nHX86ComputeBaseMethodAddress and a HConstant that will be used to load\nthe value when needed.\n\nChange Add/Sub/Mul/Div to detect a HX86LoadFromConstantTable right hand\nside, and generate code that directly references the constant area.\nOther uses will be added later.\n\nChange the inputs to HReturn and HInvoke(s), replacing the FP constants\nwith HX86LoadFromConstantTable instead.  This allows values to be\nloaded from the constant area into the right location.\n\nPort the X86_64 assembler constant area handling to the X86.\n\nUse the new per-backend optimization framework to do this conversion.\n\nChange-Id: I6d235a72238262e4f9ec0f3c88319a187f865932\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "449b10922daacc880374d7862dbb5977c7657f6d",
      "tree": "55711f732177bd72acda44b02461215d27ca55d9",
      "parents": [
        "815d1c868ad7ccba8526ac3a457e2094b609912e"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Sep 08 12:16:45 2015 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Sep 08 14:00:28 2015 +0100"
      },
      "message": "ART: Clean up Thumb2Assembler\u0027s AddConstant().\n\nChange-Id: I6a4c32d1bba79879e5514059df6336dc331246c1\n"
    },
    {
      "commit": "7a4ba9958b2d523fee0a11fc32c8bc259bd0e12a",
      "tree": "70cac41e7a9e5a8263bc92cb4c8751961d255c52",
      "parents": [
        "957fb8930766ae422568e7b1b816159a9e9bc18c",
        "305ff2d5481f7f53147d92f5e632949542803ecd"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Sep 04 13:32:47 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Fri Sep 04 13:32:47 2015 +0000"
      },
      "message": "Merge \"ART: Abort if malloc() fails in SwapAllocator::allocate().\""
    },
    {
      "commit": "305ff2d5481f7f53147d92f5e632949542803ecd",
      "tree": "3387af62c8c4ad867a6bc213e177b1110a0f8471",
      "parents": [
        "68ffda887e35f35e978f2f607b7a91e44a5e1969"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Sep 04 11:10:40 2015 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Sep 04 11:10:40 2015 +0100"
      },
      "message": "ART: Abort if malloc() fails in SwapAllocator::allocate().\n\nChange-Id: I084da8d376b0a86fc551b87d77ce9c74e60359bf\n"
    },
    {
      "commit": "05792b98980741111b4d0a24d68cff2a8e070a3a",
      "tree": "bad79a387bcbdaefc87c07b388099960ca9caff3",
      "parents": [
        "c26b4512a01d46756683a4f5e186a0b7f397f251"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Aug 03 11:56:49 2015 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Sep 03 17:30:57 2015 +0100"
      },
      "message": "ART: Move DexCache arrays to native.\n\nThis CL has a companion CL in libcore/\n    https://android-review.googlesource.com/162985\n\nChange-Id: Icbc9e20ad1b565e603195b12714762bb446515fa\n"
    },
    {
      "commit": "46637e6ad75751fa1db283aee160342dc7e2fd0f",
      "tree": "0211c79512e5f876194963d1734140d9d023e79c",
      "parents": [
        "d36fcc612036009d609795ad0b5b07a7aa980692",
        "73cf0fb75de2a449ce4fe329b5f1fb42eef1372f"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Sep 01 10:58:32 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Tue Sep 01 10:58:32 2015 +0000"
      },
      "message": "Merge \"ART: Add 16-bit Thumb2 ROR, NEGS and CMP for high registers.\""
    },
    {
      "commit": "73cf0fb75de2a449ce4fe329b5f1fb42eef1372f",
      "tree": "d5b0957414c355254babfcd1a797ce87a0eb85a2",
      "parents": [
        "9ee5d6cdc14ac94b64ea1961bf221bad48746929"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Jul 30 15:07:22 2015 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Sep 01 10:10:37 2015 +0100"
      },
      "message": "ART: Add 16-bit Thumb2 ROR, NEGS and CMP for high registers.\n\nAlso clean up the usage of set_cc flag. Define a SetCc\nenumeration that specifies whether to set or keep condition\ncodes or whether we don\u0027t care and a 16-bit instruction\nshould be selected if one exists.\n\nThis reduces the size of Nexus 5 boot.oat by 44KiB (when\ncompiled with Optimizing which is not the default yet).\n\nChange-Id: I047072dc197ea678bf2019c01bcb28943fa9b604\n"
    },
    {
      "commit": "75d4e58decf3f0be8814039df57456368e4d5475",
      "tree": "3b9f3e164a95d3d30b1ee394ff2c4996563df70c",
      "parents": [
        "4dce334b93596327433ba65c98d08960514d942f",
        "73f455ecb76d063846a82735eb80596ceee8cee3"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Aug 27 16:51:17 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Thu Aug 27 16:51:17 2015 +0000"
      },
      "message": "Merge \"X86: Assembler support for near labels\""
    },
    {
      "commit": "574d75597013cb12a961c0d4365d1618d8ef6977",
      "tree": "23f43c5fd308d4c3aa142ccd3f2045e907fd7542",
      "parents": [
        "9ee5d6cdc14ac94b64ea1961bf221bad48746929",
        "23f02f31a8368d256d45b441384432c6bece064a"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Wed Aug 26 15:23:17 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Wed Aug 26 15:23:17 2015 +0000"
      },
      "message": "Merge \"Minor changes to art::arm::Thumb2Assembler::StoreToOffset.\""
    },
    {
      "commit": "73f455ecb76d063846a82735eb80596ceee8cee3",
      "tree": "8cbf4d0b94a2d75980481b4542c021da4477373b",
      "parents": [
        "9dc601eb65da0cd5f53172699dacd6e5dd38ab44"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Fri Aug 21 09:30:05 2015 -0400"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Wed Aug 26 11:18:40 2015 -0400"
      },
      "message": "X86: Assembler support for near labels\n\nThe optimizing compiler uses 32 bit relative jumps for all forward\njumps, just in case the offset is too large to fit in one byte.  Some of\nthe generated code knows that the jumps will in fact fit.\n\nAdd a \u0027NearLabel\u0027 class to the x86 and x86_64 assemblers.  This will be\nused to generate known short forward branches.\n\nAdd jecxz/jrcxz instructions, which only handle a short offset.  They\nwill be used for intrinsics.\n\nAdd tests for the new instructions and NearLabel.\n\nChange-Id: I11177f36394d35d63b32364b0e6289ee6d97de46\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "23f02f31a8368d256d45b441384432c6bece064a",
      "tree": "74c140eb78a6a628e36f04df631d49d97592a529",
      "parents": [
        "6bd6a830f24033830a910f88928b400a7ed28418"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Tue Aug 25 18:23:20 2015 +0100"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Tue Aug 25 18:23:20 2015 +0100"
      },
      "message": "Minor changes to art::arm::Thumb2Assembler::StoreToOffset.\n\n- Use CHECK instead of DCHECK for consistency reasons.\n- Adjust documentation.\n- Stylistic changes.\n\nChange-Id: Ibc8261a0eb5a8b4d62edc1df0d5fb378e5021c22\n"
    },
    {
      "commit": "ff73498a5539d87424a964265e43765e788aec44",
      "tree": "3f8a525ef91d2f12e4b2a71c04fc8147a12c12bd",
      "parents": [
        "9dc601eb65da0cd5f53172699dacd6e5dd38ab44"
      ],
      "author": {
        "name": "Goran Jakovljevic",
        "email": "Goran.Jakovljevic@imgtec.com",
        "time": "Mon Aug 24 12:58:55 2015 +0000"
      },
      "committer": {
        "name": "Goran Jakovljevic",
        "email": "Goran.Jakovljevic@imgtec.com",
        "time": "Tue Aug 25 17:17:22 2015 +0200"
      },
      "message": "Revert \"Revert \"[MIPS] Use hard float calling convention for managed code\"\"\n\nThis reverts commit 7fee84c087e0f903e7d43bef180df047db1c8051.\n\nFixed issue with temporary registers on Mips32r6.\n\nChange-Id: I93018927e6a6036cff2d55e6cda66d3212a4316b\n"
    },
    {
      "commit": "7fee84c087e0f903e7d43bef180df047db1c8051",
      "tree": "c35065aeef23f857563eacd82e55ae47d8ceb67c",
      "parents": [
        "a29449dcf57c57fe0876f51367985477317cc557"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Aug 21 18:39:26 2015 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Aug 21 18:39:26 2015 +0000"
      },
      "message": "Revert \"[MIPS] Use hard float calling convention for managed code\"\n\nMipsMir2Lir::LockCallTemps() is broken for secondary architecture on aosp_mips64-eng.\n\nThis reverts commit a29449dcf57c57fe0876f51367985477317cc557.\n\nChange-Id: I480ea7569d73aea7894fc0a6dd804b1135286a37\n"
    },
    {
      "commit": "a29449dcf57c57fe0876f51367985477317cc557",
      "tree": "3b077e6f286bfdb48f211e0d0672ff301c5b7006",
      "parents": [
        "28de0f652e32e112edab0e5e7dc779943ae488d5"
      ],
      "author": {
        "name": "Goran Jakovljevic",
        "email": "Goran.Jakovljevic@imgtec.com",
        "time": "Wed Jul 22 11:08:57 2015 +0200"
      },
      "committer": {
        "name": "Goran Jakovljevic",
        "email": "Goran.Jakovljevic@imgtec.com",
        "time": "Fri Aug 21 14:40:30 2015 +0200"
      },
      "message": "[MIPS] Use hard float calling convention for managed code\n\nNote that this isn\u0027t o32 ABI. Same set of registers is used for\narguments ($a0-$a3 and $f12-$f15), but we don\u0027t skip registers\nand fp arguments are never passed via core registers.\n\nChange-Id: Ifb883ff6e15758b539137898b49ac2f8ee075f49\n"
    },
    {
      "commit": "f71ad9ede9ae322a897e8fe407208dc35c5dee65",
      "tree": "5dee2185faeebe5f4107fec6835f1013b4e7548d",
      "parents": [
        "add6cfac914f48136e71a05f72123154d7d2d44b",
        "50fa993d67f8a20322c27c1a77e7efcf826531fc"
      ],
      "author": {
        "name": "Alex Light",
        "email": "allight@google.com",
        "time": "Tue Aug 18 21:43:44 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Tue Aug 18 21:43:44 2015 +0000"
      },
      "message": "Merge \"Svelter libart-compiler\""
    },
    {
      "commit": "50fa993d67f8a20322c27c1a77e7efcf826531fc",
      "tree": "76d6b73a9d8a8ef2709aef6c01778af6a0d4ada1",
      "parents": [
        "4500fcbe682d666a24c2e8f6e0cb90cfb35d3fa3"
      ],
      "author": {
        "name": "Alex Light",
        "email": "allight@google.com",
        "time": "Mon Aug 10 15:30:07 2015 -0700"
      },
      "committer": {
        "name": "Alex Light",
        "email": "allight@google.com",
        "time": "Tue Aug 18 11:21:05 2015 -0700"
      },
      "message": "Svelter libart-compiler\n\nAdded new environment variable ART_{TARGET,HOST}_CODEGEN_ARCHS which\nmay be set to \u0027all\u0027, \u0027svelte\u0027 or a space separated list of architectures.\n\nWhen compiled with ART_{TARGET,HOST}_CODEGEN_ARCHS\u003d\u0027all\u0027 (the default\nvalue) dex2oat will be able to generate output for all supported\narchitectures.\n\nWhen compiled with ART_TARGET_CODEGEN_ARCHS\u003d\u0027svelte\u0027\nonly the architectures of the TARGET will be included. When\nART_HOST_CODEGEN_ARCHS\u003d\u0027svelte\u0027 all architectures the target includes\nand the host architectures will be included on the host dex2oat.\n\nIf a list of architectures is given only those will be included.\n\nChange-Id: I87f4ad0131ab1b37544d8799e947ce4733b6daec\n"
    },
    {
      "commit": "8ae3ffb29489a127f2a6242c33845dac8d50e508",
      "tree": "cb5cc72e4a699a8ef6b044d530539c13b02604b7",
      "parents": [
        "f67ab129d868b8355a8403a9627f96ac1e41a796"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Wed Aug 12 21:16:41 2015 -0400"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Fri Aug 14 12:58:40 2015 -0400"
      },
      "message": "Add \u0027bsr\u0027 instruction to x86 and x86_64\n\nAdd support for \u0027bsr\u0027 instruction.  Add tests.\n\nChange-Id: I1cd8b30d7f3f5ee7fbeef8124cc6a31bf8ce59d5\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "b9c4bbee9364a9351376fd1fec9604e7c84778d8",
      "tree": "2e0fb139b709cb0bb10f4a15067c9b302eeb0dce",
      "parents": [
        "1cad8c7c63b600a3da83bf05fb645e08ac8fafc0"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Wed Jul 01 14:26:52 2015 -0400"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Fri Aug 14 11:07:57 2015 -0400"
      },
      "message": "Add rep movsw to x86 and x86_64 instructions.\n\nAdd \u0027REP MOVSW\u0027 as a supported instruction for x86 32 and 64 bit.\n\nAdded tests.\n\nChange-Id: I1c615ac1e7fa46c48983c90f791b92be0375c8b8\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "3887c468d731420e929e6ad3acf190d5431e94fc",
      "tree": "67dacb849e722e33e118b97714a48e467c06cbd5",
      "parents": [
        "6a5037eb3340e4c981fd7de3ff45167ee5b7fc82"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Wed Aug 12 18:15:42 2015 +0100"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Wed Aug 12 18:15:42 2015 +0100"
      },
      "message": "Remove unnecessary `explicit` qualifiers on constructors.\n\nChange-Id: Id12e392ad50f66a6e2251a68662b7959315dc567\n"
    },
    {
      "commit": "cfa410b0ea561318f74a76c5323f0f6cd8eaaa50",
      "tree": "80d989b8b26e3fd1afc232c5ecb9a0919823d15b",
      "parents": [
        "1a5625be743a4a84329930ac1c7e96425e24ca8d"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Mon May 25 16:02:44 2015 -0400"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Tue Aug 11 10:32:47 2015 -0400"
      },
      "message": "[optimizing] More x86_64 code improvements\n\nUse the constant area some more, use 32-bit immediates in movq\ninstructions when possible, and other small tweaks.\n\nRemove the commented out code for Math.Abs(float/double) as it would\nfail for baseline compiler due to the output being the same as the\ninput.\n\nChange-Id: Ifa39f1865b94cec2e1c0a99af3066a645e9d3618\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    }
  ],
  "next": "fe092ab1e3cfc106216aa5518393a55786f9ab0b"
}