)]}'
{
  "log": [
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      "tree": "a0a488040883c14cc6cbec3186654137459d44ff",
      "parents": [
        "8ec0e20347e13592539a8c0786b1db1735149800"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Fri Jun 19 14:47:01 2015 +0100"
      },
      "committer": {
        "name": "David Brazdil",
        "email": "dbrazdil@google.com",
        "time": "Mon Jun 22 11:57:36 2015 +0100"
      },
      "message": "Opt compiler: Add disassembly to the \u0027.cfg\u0027 output.\n\nThis is automatically added to the \u0027.cfg\u0027 output when using the usual\n`--dump-cfg` option.\n\nChange-Id: I864bfc3a8299c042e72e451cc7730ad8271e4deb\n"
    },
    {
      "commit": "ef20f71e16f035a39a329c8524d7e59ca6a11f04",
      "tree": "a2892ae08f22ccf46baa4c77cea61f32bd07242d",
      "parents": [
        "864a2d955aa85ab989c86d7f1eeacbe0b11f8b0f"
      ],
      "author": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Tue Jun 09 10:29:30 2015 +0100"
      },
      "committer": {
        "name": "Alexandre Rames",
        "email": "alexandre.rames@linaro.org",
        "time": "Wed Jun 10 10:19:57 2015 +0100"
      },
      "message": "Add boilerplate code for architecture-specific HInstructions.\n\nChange-Id: I2723cd96e5f03012c840863dd38d7b2168117db8\n"
    },
    {
      "commit": "69aa60163989c33a008115205d39732a76ecc1dc",
      "tree": "058392dc104a8e7b3594a548239dca2d3ec06cce",
      "parents": [
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      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Jun 09 10:34:25 2015 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Jun 09 16:01:49 2015 +0100"
      },
      "message": "Revert \"Revert \"Pass current method to HNewInstance and HNewArray.\"\"\n\nProblem exposed by this change was fixed in:\nhttps://android-review.googlesource.com/#/c/154031/\n\nThis reverts commit 7b0e353b49ac3f464c662f20e20e240f0231afff.\n\nChange-Id: I680c13dc9db9ba223ab11c7af255222860b4e6d2\n"
    },
    {
      "commit": "7b0e353b49ac3f464c662f20e20e240f0231afff",
      "tree": "b5c936df891b08521176065ccaddb1f9e27c9f46",
      "parents": [
        "e21aa42e1341d34250742abafdd83311ad9fa737"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Jun 09 09:25:50 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Jun 09 09:25:50 2015 +0000"
      },
      "message": "Revert \"Pass current method to HNewInstance and HNewArray.\"\n\n082-inline-execute fails on x86.\n\nThis reverts commit e21aa42e1341d34250742abafdd83311ad9fa737.\n\nChange-Id: Ib3fd25faee2e0128001e40d3d51a74f959bc4449\n"
    },
    {
      "commit": "e21aa42e1341d34250742abafdd83311ad9fa737",
      "tree": "d2c9f8530e59876588d32f04b4effc25ebc0fa89",
      "parents": [
        "c47908e8c32fd58bc4dc75998a80f706954db1dc"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Jun 08 15:35:07 2015 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Jun 08 15:36:27 2015 +0100"
      },
      "message": "Pass current method to HNewInstance and HNewArray.\n\nAlso remove unsed CodeGenerator::LoadCurrentMethod.\n\nChange-Id: I4b8d3f2a30b8e2c76b6b329a72555483c993cb73\n"
    },
    {
      "commit": "38207af82afb6f99c687f64b15601ed20d82220a",
      "tree": "f9360949b92e5b6b01c5828c03ac67d01adffe1d",
      "parents": [
        "6a0d5e7fe6dc0c9d3dd941ab991203f2d5d1c354"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Jun 01 15:46:22 2015 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 04 14:39:06 2015 +0100"
      },
      "message": "Use HCurrentMethod in HInvokeStaticOrDirect.\n\nChange-Id: I0d15244b6b44c8b10079398c55da5071a3e3af66\n"
    },
    {
      "commit": "fd88f16100cceafbfde1b4f095f17e89444d6fa8",
      "tree": "fdb6d0520ca419acef9e953e74dcbd7d908bc4dd",
      "parents": [
        "1aebdae18678403bdac078cbbe1f7dd4243c44f3"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jun 03 11:23:52 2015 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jun 03 11:23:52 2015 +0100"
      },
      "message": "Factorize code for common LocationSummary of HInvoke.\n\nThis is one step forward, we could factorize more, but\nI wanted to get this out of the way first.\n\nChange-Id: I6ae411a737eebaecb64974f47af507ce0cfbae85\n"
    },
    {
      "commit": "e401d146407d61eeb99f8d6176b2ac13c4df1e33",
      "tree": "17927f9bfe7d2041b5942c89832d55f9dedb24c5",
      "parents": [
        "2006b7b9b8e32722bd0d640c62549d8a0ac624b6"
      ],
      "author": {
        "name": "Mathieu Chartier",
        "email": "mathieuc@google.com",
        "time": "Wed Apr 22 13:56:20 2015 -0700"
      },
      "committer": {
        "name": "Mathieu Chartier",
        "email": "mathieuc@google.com",
        "time": "Fri May 29 18:45:49 2015 -0700"
      },
      "message": "Move mirror::ArtMethod to native\n\nOptimizing + quick tests are passing, devices boot.\n\nTODO: Test and fix bugs in mips64.\n\nSaves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS.\nSome of the savings are from removal of virtual methods and direct\nmethods object arrays.\n\nBug: 19264997\nChange-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d\n"
    },
    {
      "commit": "07276db28d654594e0e86e9e467cad393f752e6e",
      "tree": "6450e07d64045f0c0949b3423501316b672641c7",
      "parents": [
        "17f1bc531ea2f8c1a6fac3def13dee1b901949dd"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon May 18 14:22:09 2015 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon May 18 19:15:52 2015 +0100"
      },
      "message": "Don\u0027t do a null test in MarkGCCard if the value cannot be null.\n\nChange-Id: I45687f6d3505178e2fc3689eac9cb6ab1b2c1e29\n"
    },
    {
      "commit": "7394569c9252b277710b2d7d3fc35fb0dd48fc4b",
      "tree": "9ce2241c95d93e873c45416a2d17e2c4084d220b",
      "parents": [
        "8a30bf23bcb1ad8d4ed9060ddbb27edbfd57a897"
      ],
      "author": {
        "name": "Mark P Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Wed Apr 29 14:56:17 2015 +0000"
      },
      "committer": {
        "name": "Mark P Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Mon May 04 14:14:32 2015 +0000"
      },
      "message": "Revert \"Revert \"Revert \"Revert \"[optimizing] Improve x86 shifts\"\"\"\"\n\nThis reverts commit 2a7a1d7808f003bea908023ebd11eb442d2fca39.\n\nFix the problem that a long long \u003e\u003e 63 got the wrong answer.  The\nproblem was that a shr was used instead of a sar.\n\nChange-Id: I0327f79c718016ddec9272a605fc50ec15ec4566\n"
    },
    {
      "commit": "2d27c8e338af7262dbd4aaa66127bb8fa1758b86",
      "tree": "e01e0bc57359df0bdf00c3da694c5403fb7fc9e6",
      "parents": [
        "3adfc4bbe6c42d574bd2069d8e38a13d5ad98ccf"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Tue Apr 28 15:48:45 2015 +0100"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Wed Apr 29 14:09:17 2015 +0100"
      },
      "message": "Refactor InvokeDexCallingConventionVisitor in Optimizing.\n\nChange-Id: I7ede0f59d5109644887bf5d39201d4e1bf043f34\n"
    },
    {
      "commit": "4bb014fd8e0aa45b012d56bc4813f18fa295d2b0",
      "tree": "ba5fa5beef6e2c4a91ec5bbe7b0ed81b168b4958",
      "parents": [
        "d677de20906067061f262bdd434536a02e7f0dd0",
        "232ade0b9401404ad4b61b1003551b58b96195a8"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Tue Apr 21 16:09:29 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Tue Apr 21 16:09:30 2015 +0000"
      },
      "message": "Merge \"Revert \"Revert \"Optimizing: Fix long-to-fp conversion on x86.\"\"\""
    },
    {
      "commit": "232ade0b9401404ad4b61b1003551b58b96195a8",
      "tree": "54fe7cc37674246dead84f883a4c8be2123e7d26",
      "parents": [
        "2e0f89b1b61685f7c322a4c6ec3e3b4839e76d64"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Mon Apr 20 15:14:36 2015 +0100"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Mon Apr 20 15:53:12 2015 +0100"
      },
      "message": "Revert \"Revert \"Optimizing: Fix long-to-fp conversion on x86.\"\"\n\nThis reverts commit 386ce406f150645158d6067c4e0a36565aefc44f.\n\nBug: 20413424\nChange-Id: I6e93ff132907f2653f1ae12d6676ff2298f62ca1\n"
    },
    {
      "commit": "ad4450e5c3ffaa9566216cc6fafbf5c11186c467",
      "tree": "eecf36e8e9d8112e765ad8840eb2d27f8d0415ab",
      "parents": [
        "f8bdd9f3a002970e4b8fdcf6fe6730116f1626c3"
      ],
      "author": {
        "name": "Zheng Xu",
        "email": "zheng.xu@arm.com",
        "time": "Fri Apr 17 18:48:56 2015 +0800"
      },
      "committer": {
        "name": "Zheng Xu",
        "email": "zheng.xu@arm.com",
        "time": "Fri Apr 17 18:54:08 2015 +0800"
      },
      "message": "Opt compiler: Implement parallel move resolver without using swap.\n\nThe algorithm of ParallelMoveResolverNoSwap() is almost the same with\nParallelMoveResolverWithSwap(), except the way we resolve the circular\ndependency. NoSwap() uses additional scratch register to resolve the\ncircular dependency. For example, (0-\u003e1) (1-\u003e2) (2-\u003e0) will be performed\nas (2-\u003escratch) (1-\u003e2) (0-\u003e1) (scratch-\u003e0).\n\nOn architectures without swap register support, NoSwap() can reduce the\nnumber of moves from 3x(N-1) to (N+1) when there is circular dependency\nwith N moves.\n\nAnd also, NoSwap() algorithm does not depend on architecture register\nlayout information, which means it can support register pairs on arm32\nand X/W, D/S registers on arm64 without additional modification.\n\nChange-Id: Idf56bd5469bb78c0e339e43ab16387428a082318\n"
    },
    {
      "commit": "669d8a1edbb2a78e08731a9cd6d8e815b0ec49db",
      "tree": "240d26edb4af28ccd7fa65a9fecc39f718d3d603",
      "parents": [
        "ee2da343bb2a54d9d77e29226e0317ccc913c8c1",
        "e14590bdfed24df30e6b7545fc819ba03ff8bba1"
      ],
      "author": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Thu Apr 16 09:40:38 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Thu Apr 16 09:40:39 2015 +0000"
      },
      "message": "Merge \"Revert \"[optimizing] Improve x86 parallel moves/swaps\"\""
    },
    {
      "commit": "e14590bdfed24df30e6b7545fc819ba03ff8bba1",
      "tree": "1fe89a424c91dae7adc07ebd620dce8297a0854e",
      "parents": [
        "a5c19ce8d200d68a528f2ce0ebff989106c4a933"
      ],
      "author": {
        "name": "Guillaume Sanchez",
        "email": "guillaumesa@google.com",
        "time": "Wed Apr 15 18:57:27 2015 +0000"
      },
      "committer": {
        "name": "Guillaume Sanchez",
        "email": "guillaumesa@google.com",
        "time": "Wed Apr 15 18:57:27 2015 +0000"
      },
      "message": "Revert \"[optimizing] Improve x86 parallel moves/swaps\"\n\nThis reverts commit a5c19ce8d200d68a528f2ce0ebff989106c4a933.\n\nThis commit introduces a performance regression on CaffeineLogic of 30%.\n\nChange-Id: I917e206e249d44e1748537bc1b2d31054ea4959d\n"
    },
    {
      "commit": "e4e88d7b37c977b4c755485174a54c04aa3de951",
      "tree": "b25d5be5b8e7320d05f42da549c11cc82d7dbc51",
      "parents": [
        "6cfece6336c86017694758bbc0dc68b62c02de86",
        "386ce406f150645158d6067c4e0a36565aefc44f"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Apr 13 12:53:56 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Mon Apr 13 12:53:57 2015 +0000"
      },
      "message": "Merge \"Revert \"Optimizing: Fix long-to-fp conversion on x86.\"\""
    },
    {
      "commit": "386ce406f150645158d6067c4e0a36565aefc44f",
      "tree": "e350441be38017d6e7555d9e13ca8b975d61451d",
      "parents": [
        "2d45b4df3838d9c0e5a213305ccd1d7009e01437"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Apr 13 12:53:37 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Apr 13 12:53:37 2015 +0000"
      },
      "message": "Revert \"Optimizing: Fix long-to-fp conversion on x86.\"\n\nTest fails on arm.\n\nThis reverts commit 2d45b4df3838d9c0e5a213305ccd1d7009e01437.\n\nChange-Id: Id2864917b52f7ffba459680303a2d15b34f16a4e\n"
    },
    {
      "commit": "6cfece6336c86017694758bbc0dc68b62c02de86",
      "tree": "c0cc90f4167aed365c0ebfddd99fec31c473efc2",
      "parents": [
        "095d209342420563becfec6676b46a6c6b839107",
        "2d45b4df3838d9c0e5a213305ccd1d7009e01437"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Mon Apr 13 11:33:08 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Mon Apr 13 11:33:09 2015 +0000"
      },
      "message": "Merge \"Optimizing: Fix long-to-fp conversion on x86.\""
    },
    {
      "commit": "2d45b4df3838d9c0e5a213305ccd1d7009e01437",
      "tree": "b3893899a540ba9f4c8cd70e69536d0239a9d3ef",
      "parents": [
        "1576be32be4a99a1cffdaaf209a3cd67e8b2f88a"
      ],
      "author": {
        "name": "Serguei Katkov",
        "email": "serguei.i.katkov@intel.com",
        "time": "Tue Apr 07 17:04:50 2015 +0600"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Mon Apr 13 11:30:02 2015 +0000"
      },
      "message": "Optimizing: Fix long-to-fp conversion on x86.\n\nlong-to-fp conversion implemented using SSE loses the precision.\nThe test is included. CL uses FPU to provide the correct result.\n\nChange-Id: I8eaf3c46819a8cb52642a7e7d7c4e3e0edbc88db\nSigned-off-by: Serguei Katkov \u003cserguei.i.katkov@intel.com\u003e\n"
    },
    {
      "commit": "1b743777e6b6cec3387b0ee347b6a8a03779c345",
      "tree": "036c42dbf10d8c75de1326e16406a12191c704ce",
      "parents": [
        "cf69f8163d700be29a1732e7e229101c67a51803",
        "f9aac1e9f442c2486cd54f045d43e15791601205"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Apr 10 21:40:59 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Fri Apr 10 21:41:00 2015 +0000"
      },
      "message": "Merge \"Revert \"[optimizing] Improve x86 shifts\"\""
    },
    {
      "commit": "f9aac1e9f442c2486cd54f045d43e15791601205",
      "tree": "2f3aa65a881020beeb6f4b3313b3366733bbf3f5",
      "parents": [
        "222fcf96c9b73bbb739012575e7e413caf9348ec"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Fri Apr 10 18:12:48 2015 +0000"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Fri Apr 10 18:12:48 2015 +0000"
      },
      "message": "Revert \"[optimizing] Improve x86 shifts\"\n\nThis reverts commit 222fcf96c9b73bbb739012575e7e413caf9348ec.\n\nReverting this CL as it is breaking a few tests (see http://build.chromium.org/p/client.art/builders/host-x86/builds/3251/steps/test%20optimizing/logs/stdio).  Will investigate ASAP.\n\nChange-Id: Iddd8363e83a24aa49fbdf0f0c9dc12e63b4848de\n"
    },
    {
      "commit": "27ef3177fb164b5e1a3b8a6fd43d25f3074e586d",
      "tree": "3717202ea300f60f6df3aa29922b98579b7958d5",
      "parents": [
        "47317b430ee4f0094e58df45b557fe754b29b63b",
        "b19930c5cba3cf662dce5ee057fcc9829b4cbb9c"
      ],
      "author": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Fri Apr 10 16:15:07 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Fri Apr 10 16:15:07 2015 +0000"
      },
      "message": "Merge \"Follow up of \"div/rem on x86 and x86_64\", to tidy up the code a little.\""
    },
    {
      "commit": "a5c19ce8d200d68a528f2ce0ebff989106c4a933",
      "tree": "4638a8d8e5b1562ec5ed05967490fec1ef7f0d17",
      "parents": [
        "6d80318c382a3490ab605b46fa7cb22c5e823fec"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Wed Apr 01 12:51:05 2015 -0400"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Fri Apr 10 12:08:31 2015 -0400"
      },
      "message": "[optimizing] Improve x86 parallel moves/swaps\n\nAdd a new constructor to ScratchRegisterScope that will supply a\nregister if there is a free one, but not spill to force one.  Use this\nto generated alternate code that doesn\u0027t use a temporary, as the\nspill/restore of a register generates extra instructions that aren\u0027t\nnecessary on x86.\n\nHere is the benefit for a 32 bit memory-to-memory exchange with no\nfree registers:\n\u003c        50    \t       push eax\n\u003c        53    \t       push ebx\n\u003c  8B44244C    \t       mov eax, [esp + 76]\n\u003c  8B5C246C    \t       mov ebx, [esp + 108]\n\u003c  8944246C    \t       mov [esp + 108], eax\n\u003c  895C244C    \t       mov [esp + 76], ebx\n\u003c        5B    \t       pop ebx\n\u003c        58    \t       pop eax\n---\n\u003e  FF742444    \t       push [esp + 68]\n\u003e  FF742468    \t       push [esp + 104]\n\u003e  8F44244C    \t       pop [esp + 72]\n\u003e  8F442468    \t       pop [esp + 100]\n\nAvoid using xchg instruction, as it is slow on smaller processors.\n\nChange-Id: Id29ee3abd998577baaee552d55d23e60ae0c7871\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "222fcf96c9b73bbb739012575e7e413caf9348ec",
      "tree": "e0441bc484cc8f441685de49c931a030730a3701",
      "parents": [
        "fcfea6324b2913621d5cb642d4315f22c4901368"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Mon Mar 30 14:13:30 2015 -0400"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Fri Apr 10 09:33:52 2015 -0400"
      },
      "message": "[optimizing] Improve x86 shifts\n\nSupport memory operands for integer shifts.  Generate better code for\nlong shifts by constants.\n\nChange-Id: Icc92fa1b59cc280d4894af6f054e19b01977d5ce\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "b19930c5cba3cf662dce5ee057fcc9829b4cbb9c",
      "tree": "c226f8fffc4522b273072c516507083e2a77c505",
      "parents": [
        "0f88e87085b7cf6544dadff3f555773966a6853e"
      ],
      "author": {
        "name": "Guillaume Sanchez",
        "email": "guillaumesa@google.com",
        "time": "Thu Apr 09 21:12:15 2015 +0100"
      },
      "committer": {
        "name": "Guillaume Sanchez",
        "email": "guillaumesa@google.com",
        "time": "Fri Apr 10 10:28:02 2015 +0100"
      },
      "message": "Follow up of \"div/rem on x86 and x86_64\", to tidy up the code a little.\n\nChange-Id: Ibf39cbc8ac1d773599d70be2cb1e941674b60f1d\n"
    },
    {
      "commit": "96159860fc6c4bf68a51a8a57941971f122685d6",
      "tree": "ef2465ab2d84b9076ab57ad239333910f68abd2b",
      "parents": [
        "0c51da5db821493bcef4617ccab04ea367ecc444",
        "0f88e87085b7cf6544dadff3f555773966a6853e"
      ],
      "author": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Thu Apr 09 12:46:58 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Thu Apr 09 12:46:59 2015 +0000"
      },
      "message": "Merge \"Speedup div/rem by constants on x86 and x86_64\""
    },
    {
      "commit": "0f88e87085b7cf6544dadff3f555773966a6853e",
      "tree": "ea0ae17c712b995e258f1f749a1b8cd98b1fa34b",
      "parents": [
        "c4bd0e6a7f4839ea99222f06979cc2369cb9bf10"
      ],
      "author": {
        "name": "Guillaume Sanchez",
        "email": "guillaumesa@google.com",
        "time": "Mon Mar 30 17:55:45 2015 +0100"
      },
      "committer": {
        "name": "Guillaume Sanchez",
        "email": "guillaumesa@google.com",
        "time": "Thu Apr 09 12:24:10 2015 +0100"
      },
      "message": "Speedup div/rem by constants on x86 and x86_64\n\nThis is done using the algorithms in Hacker\u0027s Delight chapter 10.\n\nChange-Id: I7bacefe10067569769ed31a1f7834f796fb41119\n"
    },
    {
      "commit": "97597c9be7f4eb5263a80e7de4684dbfa1427e9a",
      "tree": "690dc04c72690a056aa84ac0206f96e5f513b3c2",
      "parents": [
        "7775d2c1e48c0bb0880f720f3dfbd4b4d0de7c6e",
        "fb8d279bc011b31d0765dc7ca59afea324fd0d0c"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Thu Apr 02 23:10:46 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Thu Apr 02 23:10:46 2015 +0000"
      },
      "message": "Merge \"[optimizing] Implement x86/x86_64 math intrinsics\""
    },
    {
      "commit": "d43b3ac88cd46b8815890188c9c2b9a3f1564648",
      "tree": "6c599c3f40d57e92786bd7f41c0541d9eaa2643b",
      "parents": [
        "a109632b240f3c9355ca95500f6f48e4478e3c51"
      ],
      "author": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Wed Apr 01 14:03:04 2015 -0700"
      },
      "committer": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Wed Apr 01 14:05:13 2015 -0700"
      },
      "message": "Revert \"Revert \"Deoptimization-based bce.\"\"\n\nThis reverts commit 0ba627337274ccfb8c9cb9bf23fffb1e1b9d1430.\n\nChange-Id: I1ca10d15bbb49897a0cf541ab160431ec180a006\n"
    },
    {
      "commit": "fb8d279bc011b31d0765dc7ca59afea324fd0d0c",
      "tree": "01b21964ce0516bda835faa15b260ac290714fe0",
      "parents": [
        "dcff612c3a6e1427749771c4559f198fa480f709"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Tue Mar 31 22:16:59 2015 -0400"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Wed Apr 01 08:45:38 2015 -0400"
      },
      "message": "[optimizing] Implement x86/x86_64 math intrinsics\n\nImplement floor/ceil/round/RoundFloat on x86 and x86_64.\nImplement RoundDouble on x86_64.\n\nAdd support for roundss and roundsd on both architectures.  Support them\nin the disassembler as well.\n\nAdd the instruction set features for x86, as the \u0027round\u0027 instruction is\nonly supported if SSE4.1 is supported.\n\nFix the tests to handle the addition of passing the instruction set\nfeatures to x86 and x86_64.\n\nAdd assembler tests for roundsd and roundss to x86_64 assembler tests.\n\nChange-Id: I9742d5930befb0bbc23f3d6c83ce0183ed9fe04f\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "d75948ac93a4a317feaf136cae78823071234ba5",
      "tree": "7593fb8c1ba2b67decdaa967b6348501f58d8b9d",
      "parents": [
        "b3665e3dfdd23cc7a2f17a0b53bb16205bf4151f"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Mar 27 09:53:16 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Mar 27 12:01:40 2015 +0000"
      },
      "message": "Intrinsify String.compareTo.\n\nChange-Id: Ia540df98755ac493fe61bd63f0bd94f6d97fbb57\n"
    },
    {
      "commit": "09ed1a3125849ec6ac07cb886e3c502e1dcfada2",
      "tree": "d86be714298806cfcd6a16be674573369474e8f7",
      "parents": [
        "03910065cd025ecb07781b85c2240be69c202d75"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Wed Mar 25 08:30:06 2015 -0400"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Thu Mar 26 21:28:33 2015 -0400"
      },
      "message": "[optimizing] Implement X86 intrinsic support\n\nImplement the supported intrinsics for X86.\n\nEnhance the graph visualizer to print \u003cU\u003e for unallocated locations, to\nallow calling the graph dumper from within register allocation for\ndebugging purposes.\n\nChange-Id: I3b0319eb70a9a4ea228f67065b4c52d13a1ae775\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "0ba627337274ccfb8c9cb9bf23fffb1e1b9d1430",
      "tree": "0e1d0813c1d8d1c7239a900c1653296975713df0",
      "parents": [
        "e295e6ec5beaea31be5d7d3c996cd8cfa2053129"
      ],
      "author": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Tue Mar 24 02:39:46 2015 +0000"
      },
      "committer": {
        "name": "Andreas Gampe",
        "email": "agampe@google.com",
        "time": "Tue Mar 24 02:39:46 2015 +0000"
      },
      "message": "Revert \"Deoptimization-based bce.\"\n\nThis breaks compiling the core image:\n\n Error after BCE: art::SSAChecker: Instruction 219 in block 1 does not dominate use 221 in block 1.\n\nThis reverts commit e295e6ec5beaea31be5d7d3c996cd8cfa2053129.\n\nChange-Id: Ieeb48797d451836ed506ccb940872f1443942e4e\n"
    },
    {
      "commit": "e295e6ec5beaea31be5d7d3c996cd8cfa2053129",
      "tree": "4d8a657d23d511743ce35bee596544d7f652efdb",
      "parents": [
        "d24ba2c44c76a2b2dd13aafe8f7981c15be31a98"
      ],
      "author": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Sat Mar 07 06:37:59 2015 -0800"
      },
      "committer": {
        "name": "Mingyao Yang",
        "email": "mingyao@google.com",
        "time": "Mon Mar 23 16:39:37 2015 -0700"
      },
      "message": "Deoptimization-based bce.\n\nA mechanism is introduced that a runtime method can be called\nfrom code compiled with optimizing compiler to deoptimize into\ninterpreter. This can be used to establish invariants in the managed code\nIf the invariant does not hold at runtime, we will deoptimize and continue\nexecution in the interpreter. This allows to optimize the managed code as\nif the invariant was proven during compile time. However, the exception\nwill be thrown according to the semantics demanded by the spec.\n\nThe invariant and optimization included in this patch are based on the\nlength of an array. Given a set of array accesses with constant indices\n{c1, ..., cn}, we can optimize away all bounds checks iff all 0 \u003c\u003d min(ci) and\nmax(ci) \u003c array-length. The first can be proven statically. The second can be\nestablished with a deoptimization-based invariant. This replaces n bounds\nchecks with one invariant check (plus slow-path code).\n\nChange-Id: I8c6e34b56c85d25b91074832d13dba1db0a81569\n"
    },
    {
      "commit": "234d69d075d1608f80adb647f7935077b62b6376",
      "tree": "f6b68ff38722dc91bd0de2387609ee0ce950e0ce",
      "parents": [
        "31df246d330c45f5691e226d176d0c59450f8435"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Mar 09 10:28:50 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Mar 11 14:23:38 2015 +0000"
      },
      "message": "Revert \"Revert \"[optimizing] Enable x86 long support.\"\"\n\nThis reverts commit 154552e666347d41d95d7619c6ee56249ff4feca.\n\nChange-Id: Idc726551c249a888b7ff5fde8508ae50e81b2e13\n"
    },
    {
      "commit": "154552e666347d41d95d7619c6ee56249ff4feca",
      "tree": "b8bdb820be33317f23ef1d3e43d13b2b6bfb3ba5",
      "parents": [
        "b4ba354cf8d22b261205494875cc014f18587b50"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Mar 06 16:10:14 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Mar 06 16:10:14 2015 +0000"
      },
      "message": "Revert \"[optimizing] Enable x86 long support.\"\n\nFew libcore failures.\n\nThis reverts commit b4ba354cf8d22b261205494875cc014f18587b50.\n\nChange-Id: I4a28d853e730dff9b69aec9555505803cf2fcd63\n"
    },
    {
      "commit": "b4ba354cf8d22b261205494875cc014f18587b50",
      "tree": "b6ce1e89f56f4d5adf238188df5b02fd7e2c23ac",
      "parents": [
        "af8db2ea18135588b267fe9a0b2f7af734b906cc"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Mar 05 11:28:58 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Mar 06 11:37:33 2015 +0000"
      },
      "message": "[optimizing] Enable x86 long support.\n\nChange-Id: I9006972a65a1f191c45691104a960366747f9d16\n"
    },
    {
      "commit": "dc23d8318db08cb42e20f1d16dbc416798951a8b",
      "tree": "e7a883bb3263ccb971898df98bc58700604c1d1d",
      "parents": [
        "e5f5953e744060fde3b4489cea4d934d529e3e32"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Feb 16 11:15:43 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Feb 18 09:53:32 2015 +0000"
      },
      "message": "Avoid generating jmp +0.\n\nWhen a block branches to a non-following block, but blocks\nin-between do branch to it, we can avoid doing the branch.\n\nChange-Id: I9b343f662a4efc718cd4b58168f93162a24e1219\n"
    },
    {
      "commit": "c9ff6b112d25657128f9a7251e253b1382b0f1b9",
      "tree": "dd43d2c53a7d4470c63e21e02b46d07b2ed046c5",
      "parents": [
        "0d5917fedc6f62715759c24f14810733c409ebff",
        "7c8d009552545e6f1fd6036721e4e42e3fd14697"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jan 29 11:05:48 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Thu Jan 29 11:05:49 2015 +0000"
      },
      "message": "Merge \"[optimizing compiler] Support x86 hard float ABI\""
    },
    {
      "commit": "1cf95287364948689f6a1a320567acd7728e94a3",
      "tree": "70a8b60c768894d635cf63b0a480baa5073d2bed",
      "parents": [
        "4a50662eeaa0b1a26be66e7584fb765151dabc59"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Dec 12 19:22:03 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jan 29 10:52:14 2015 +0000"
      },
      "message": "Small optimization for recursive calls: avoid dex cache.\n\nChange-Id: I044757a2f06e535cdc1480c4fc8182b89635baf6\n"
    },
    {
      "commit": "7c8d009552545e6f1fd6036721e4e42e3fd14697",
      "tree": "f7290aba6a1dcb008af1388f582d422fe1c07ff6",
      "parents": [
        "763abfd0d803f8169e97d3da944043c2464aac0a"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Mon Jan 26 11:21:33 2015 -0500"
      },
      "committer": {
        "name": "Mark P Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Wed Jan 28 00:48:50 2015 +0000"
      },
      "message": "[optimizing compiler] Support x86 hard float ABI\n\nAdd support for the new ABI passing FP parameters in XMM0-XMM3.  This\nallows us to optimize for x86 methods that don\u0027t use \u0027long\u0027.\n\nChange-Id: Ic79a24767173451e7d7095ccc2a00b307593a868\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "966c3ae95d3c699ee9fbdbccc1acdaaf02325faf",
      "tree": "7a9bd5dbfb8b02f8bb7e3387876be0c1f7844063",
      "parents": [
        "85ed6bdd890c08f50c205d7f0604b5a35603b13e"
      ],
      "author": {
        "name": "Mark P Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Tue Jan 27 15:45:27 2015 +0000"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Tue Jan 27 17:00:21 2015 -0500"
      },
      "message": "Revert \"Revert \"ART: Implement X86 hard float (Quick/JNI/Baseline)\"\"\n\nThis reverts commit 949c91fb91f40a4a80b2b492913cf8541008975e.\n\nThis time, don\u0027t clobber EBX before saving it.\n\nRedo some of the macros to make register usage explicit.\n\nChange-Id: I8db8662877cd006816e16a28f42444ab7c36bfef\n"
    },
    {
      "commit": "949c91fb91f40a4a80b2b492913cf8541008975e",
      "tree": "45c840d1d6fd0ab71d96cb6c61931f468b3a0adf",
      "parents": [
        "aeb47bb12420e65b4b5f61164e6396ea93734a0a"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Jan 27 10:48:44 2015 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Jan 27 13:41:29 2015 +0000"
      },
      "message": "Revert \"ART: Implement X86 hard float (Quick/JNI/Baseline)\"\n\nAnd the 3 Mac build fixes. Fix conflicts in context_x86.* .\n\nThis reverts commits\n  3d2c8e74c27efee58e24ec31441124f3f21384b9 ,\n  34eda1dd66b92a361797c63d57fa19e83c08a1b4 ,\n  f601d1954348b71186fa160a0ae6a1f4f1c5aee6 ,\n  bc503348a1da573488503cc2819c9e30807bea31 .\n\nBug: 19150481\nChange-Id: I6650ee30a7d261159380fe2119e14379e4dc9970\n"
    },
    {
      "commit": "3d2c8e74c27efee58e24ec31441124f3f21384b9",
      "tree": "416a60f70414b026395e3660edeee5e1cb10b6f7",
      "parents": [
        "d834380c94af85b498560f3b5feae21ef7fab1ed"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Tue Jan 13 17:32:55 2015 -0500"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Fri Jan 23 12:53:45 2015 -0500"
      },
      "message": "ART: Implement X86 hard float (Quick/JNI/Baseline)\n\nUse XMM0-XMM3 as parameter registers for float/double on X86.  X86_64\nalready uses XMM0-XMM7 for parameters.\n\nChange the \u0027hidden\u0027 argument register from XMM0 to XMM7 to avoid a\nconflict.\n\nAdd support for FPR save/restore in runtime/arch/x86.\n\nMinimal support for Optimizing baseline compiler.\n\nBump the version in runtime/oat.h because this is an ABI change.\n\nChange-Id: Ia6fe150e8488b9e582b0178c0dda65fc81d5a8ba\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "d97dc40d186aec46bfd318b6a2026a98241d7e9c",
      "tree": "5cf0257eda25e2722a1adafb9de22690c06a56d8",
      "parents": [
        "c698b78a17043d8898deb817098181595fbe734e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jan 22 13:50:01 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jan 23 09:20:42 2015 +0000"
      },
      "message": "Support callee save floating point registers on x64.\n\n- Share the computation of core_spill_mask and fpu_spill_mask\n  between backends.\n- Remove explicit stack overflow check support: we need to adjust\n  them and since they are not tested, they will easily bitrot.\n\nChange-Id: I0b619b8de4e1bdb169ea1ae7c6ede8df0d65837a\n"
    },
    {
      "commit": "988939683c26c0b1c8808fc206add6337319509a",
      "tree": "876e94428276547a29c27ccf17509a42dfe7cda1",
      "parents": [
        "59add47cabce3735ccd470cd3b5dac8b112e09ab"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 21 12:32:32 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 21 18:50:25 2015 +0000"
      },
      "message": "Enable core callee-save on x64.\n\nWill work on other architectures and FP support in other CLs.\n\nChange-Id: I8cef0343eedc7202d206f5217fdf0349035f0e4d\n"
    },
    {
      "commit": "24f2dfae084b2382c053f5d688fd6bb26cb8a328",
      "tree": "74cfabf632f13c04729081051e34f68d002c91d4",
      "parents": [
        "93edf73a5fecd526920fbd870068fa592376ac8a"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Wed Jan 14 19:51:45 2015 -0500"
      },
      "committer": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Wed Jan 21 11:00:55 2015 +0000"
      },
      "message": "[optimizing compiler] Implement inline x86 FP \u0027%\u0027\n\nReplace the calls to fmod/fmodf by inline code as is done in the Quick\ncompiler.\n\nRemove the quick fmod/fmodf runtime entries, as they are no longer in\nuse.\n\n64 bit code generator Move() routine needed to be enhanced to handle\nconstants, as Location::Any() allows them to be generated.\n\nChange-Id: I6b6a42f6faeed4b0b3c940453e487daf5b25d184\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "cd6dffedf1bd8e6dfb3fb0c933551f9a90f7de3f",
      "tree": "0d83e9fdf65bded684d6e836078f253e63b7e11f",
      "parents": [
        "12c03ac7575db242a6f35739bb459e8277115da4"
      ],
      "author": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Thu Jan 08 17:35:35 2015 +0000"
      },
      "committer": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Fri Jan 16 17:27:03 2015 +0000"
      },
      "message": "Add implicit null checks for the optimizing compiler\n\n- for backends: arm, arm64, x86, x86_64\n- fixed parameter passing for CodeGenerator\n- 003-omnibus-opcodes test verifies that NullPointerExceptions work as\nexpected\n\nChange-Id: I1b302acd353342504716c9169a80706cf3aba2c8\n"
    },
    {
      "commit": "f85a9ca9859ad843dc03d3a2b600afbaf2e9bbdd",
      "tree": "a802042fa7a3a8cb820916d558e630596daaa9b4",
      "parents": [
        "8fccea249b1a6f1469eeea42c2b2cca06ce1c70d"
      ],
      "author": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Tue Jan 13 09:20:58 2015 -0500"
      },
      "committer": {
        "name": "Mark Mendell",
        "email": "mark.p.mendell@intel.com",
        "time": "Thu Jan 15 11:21:37 2015 -0500"
      },
      "message": "[optimizing compiler] Compute live spill size\n\nThe current stack frame calculation assumes that each live register to\nbe saved/restored has the word size of the machine.  This fails for X86,\nwhere a double in an XMM register takes up 8 bytes.  Change the\ncalculation to keep track of the number of core registers and number of\nfp registers to handle this distinction.\n\nThis is slightly pessimal, as the registers may not be active at the\nsame time, but the only way to handle this would be to allocate both\nclasses of registers simultaneously, or remember all the active\nintervals, matching them up and compute the size of each safepoint\ninterval.\n\nChange-Id: If7860aa319b625c214775347728cdf49a56946eb\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    },
    {
      "commit": "840e5461a85f8908f51e7f6cd562a9129ff0e7ce",
      "tree": "ea8b4cbc5a0e3dea96fefcd9247e6c06b17ac518",
      "parents": [
        "893e8881e31180721512c1b9e5ffacb03aad2e45"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 07 16:01:24 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jan 08 13:57:51 2015 +0000"
      },
      "message": "Implement double and float support for arm in register allocator.\n\nThe basic approach is:\n- An instruction that needs two registers gets two intervals.\n- When allocating the low part, we also allocate the high part.\n- When splitting a low (or high) interval, we also split the high\n  (or low) equivalent.\n- Allocation follows the (S/D register) requirement that low\n  registers are always even and the high equivalent is low + 1.\n\nChange-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797\n"
    },
    {
      "commit": "52c489645b6e9ae33623f1ec24143cde5444906e",
      "tree": "a39667aa354645bd42a7a061d08ca82df3004143",
      "parents": [
        "193c7a94822f765b0b6b0cecd54c9f08dfd26425"
      ],
      "author": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Tue Dec 16 17:02:57 2014 +0000"
      },
      "committer": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Fri Dec 19 09:58:27 2014 +0000"
      },
      "message": "[optimizing compiler] Add support for volatile\n\n- for backends: arm, x86, x86_64\n- added necessary instructions to assemblies\n- clean up code gen for field set/get\n- fixed InstructionDataEquals for some instructions\n- fixed comments in compiler_enums\n\n* 003-opcode test verifies basic volatile functionality\n\nChange-Id: I144393efa312dfb2c332cb84056b00edffee338a\n"
    },
    {
      "commit": "9aec02fc5df5518c16f1e5a9b6cb198a192db973",
      "tree": "fe924b37f395af1bb50f55ee6c87c66b727f00af",
      "parents": [
        "20032e512c003a8f42735c4e1eca19c1472bb95e"
      ],
      "author": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Tue Nov 18 23:06:35 2014 +0000"
      },
      "committer": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Mon Nov 24 16:06:55 2014 +0000"
      },
      "message": "[optimizing compiler] Add shifts\n\nAdded SHL, SHR, USHR for arm, x86, x86_64.\n\nChange-Id: I971f594e270179457e6958acf1401ff7630df07e\n"
    },
    {
      "commit": "86a8d7afc7f00ff0f5ea7b8aaf4d50514250a4e6",
      "tree": "3db61320369973e463f67927a8983d7eb0d9f860",
      "parents": [
        "255a5bde2f0014dc86a564555106a4291c0867b4"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 19 08:47:18 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 19 08:47:18 2014 +0000"
      },
      "message": "Consistently use k{InstructionSet}WordSize.\n\nThese constants were defined prior to k{InstructionSet}PointerSize. So\nuse them consistently in optimizing as a first step. We can discuss\nwhether we should remove them in a second step.\n\nChange-Id: If129de1a3bb8b65f8d9c816a8ad466815fb202e6\n"
    },
    {
      "commit": "bacfec30ee9f2f6fdfd190f11b105b609938efca",
      "tree": "1fb08fa38b27627ab59a54895ef098b43bb70ce1",
      "parents": [
        "ff5298ff1640b730ee62c90ca78fc96b7ee82ec4"
      ],
      "author": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Fri Nov 14 15:54:36 2014 +0000"
      },
      "committer": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Mon Nov 17 11:19:35 2014 +0000"
      },
      "message": "[optimizing compiler] Add REM_INT, REM_LONG\n\n- for arm, x86, x86_64\n- minor cleanup/fix in div tests\n\nChange-Id: I240874010206a5a9b3aaffbc81a885b94c248f93\n"
    },
    {
      "commit": "a3279c80b4f92e0cc96902cf069c09424ed94ed0",
      "tree": "2d566e00a4976fe72c54663192715f919d3fa1dd",
      "parents": [
        "a1af1b59256820dde25ec21581e9e64f698e182f",
        "f0e3937b87453234d0d7970b8712082062709b8d"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Nov 13 09:58:56 2014 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Thu Nov 13 09:58:57 2014 +0000"
      },
      "message": "Merge \"Do a parallel move in BoundsCheckSlowPath.\""
    },
    {
      "commit": "f0e3937b87453234d0d7970b8712082062709b8d",
      "tree": "e552c1173ee90fea1d2ba11cc08878efe65ba0be",
      "parents": [
        "59321e0e10ea09694efecf6154704e2743b9bffd"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 12 17:50:07 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 12 17:55:24 2014 +0000"
      },
      "message": "Do a parallel move in BoundsCheckSlowPath.\n\nThe two locations of the index and length could overlap,\nso we need a parallel move. Also factorize the code for\ndoing a parallel move based on two locations.\n\nChange-Id: Iee8b3459e2eed6704d45e9a564fb2cd050741ea4\n"
    },
    {
      "commit": "9574c4b5f5ef039d694ac12c97e25ca02eca83c0",
      "tree": "2ad3cb7ffaf3579b9ca2a7bb0d7d7e99b3c758b6",
      "parents": [
        "59321e0e10ea09694efecf6154704e2743b9bffd"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 12 13:19:37 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 12 13:55:36 2014 +0000"
      },
      "message": "Implement and/or/xor in optimizing.\n\nChange-Id: I7cf6da1fd334a7177a5580931b8f174dd40b7cec\n"
    },
    {
      "commit": "de58ab2c03ff8112b07ab827c8fa38f670dfc656",
      "tree": "c872bfbcad1e90845008140bbddcc43e56dc19d2",
      "parents": [
        "3ed86e4e98dfe1b05c9a03aa2aee42c145a018c3"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Nov 05 12:46:03 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Nov 06 16:49:52 2014 +0000"
      },
      "message": "Implement try/catch/throw in optimizing.\n\n- We currently don\u0027t run optimizations in the presence of a try/catch.\n- We therefore implement Quick\u0027s mapping table.\n- Also fix a missing null check on array-length.\n\nChange-Id: I6917dfcb868e75c1cf6eff32b7cbb60b6cfbd68f\n"
    },
    {
      "commit": "424f676379f2f872acd1478672022f19f3240fc1",
      "tree": "bdd8fbb9c2401465d9a0536e94dec74acc8b4f3b",
      "parents": [
        "793d1023785f81eb8e29a3eb67fec17d7ee7dcbe"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Nov 03 14:51:25 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Nov 04 11:23:08 2014 +0000"
      },
      "message": "Implement CONST_CLASS in optimizing compiler.\n\nChange-Id: Ia8c8dfbef87cb2f7893bfb6e178466154eec9efd\n"
    },
    {
      "commit": "19a19cffd197a28ae4c9c3e59eff6352fd392241",
      "tree": "265b971afd0e33afc8986317aea2f5a6fe817aec",
      "parents": [
        "7c049c1f34220b0dc1a7f68f3b30f388bae7bdb9"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Oct 22 16:07:05 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Oct 29 13:01:48 2014 +0000"
      },
      "message": "Add support for static fields in optimizing compiler.\n\nChange-Id: Id2f010589e2bd6faf42c05bb33abf6816ebe9fa9\n"
    },
    {
      "commit": "102cbed1e52b7c5f09458b44903fe97bb3e14d5f",
      "tree": "cb0a433c8f284021298c8a0c4dd0da97ca9d198a",
      "parents": [
        "07f5c5edb7ef24ac35364e6ef9a8107a44e6564e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Oct 15 18:31:05 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Oct 21 16:03:51 2014 +0100"
      },
      "message": "Implement register allocator for floating point registers.\n\nAlso:\n- Fix misuses of emitting the rex prefix in the x86_64 assembler.\n- Fix movaps code generation in the x86_64 assembler.\n\nChange-Id: Ib6dcf6e7c4a9c43368cfc46b02ba50f69ae69cbe\n"
    },
    {
      "commit": "34bacdf7eb46c0ffbf24ba7aa14a904bc9176fb2",
      "tree": "e8ed8e40c5f7896a9ac01bf7dcc2e56f40cfc804",
      "parents": [
        "7f758228f7904d2f65f06bfbd2b8ecbb8e8c6a9d"
      ],
      "author": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Tue Oct 07 20:23:36 2014 +0100"
      },
      "committer": {
        "name": "Calin Juravle",
        "email": "calin@google.com",
        "time": "Fri Oct 17 11:46:45 2014 +0100"
      },
      "message": "Add multiplication for integral types\n\nThis also fixes an issue where we could allocate a pair register even if\none of its parts was already blocked.\n\nChange-Id: I4869175933409add2a56f1ccfb369c3d3dd3cb01\n"
    },
    {
      "commit": "92a73aef279be78e3c2b04db1713076183933436",
      "tree": "e73b214fb7d740588f5d065b2e4ff3eb8c527e34",
      "parents": [
        "5c5efc253507eb43265997c9afcd778f72b6cef4"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Oct 16 11:12:52 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Oct 16 15:17:44 2014 +0100"
      },
      "message": "Don\u0027t use assembler classes in code_generator.h.\n\nThe arm64 backend uses its own assembler and does not share\nthe same classes as the other backends. To avoid conflicts\nor unnecessary mappings, just don\u0027t use those classes in the\nshared part of the code generator.\n\nChange-Id: I9e5fa40c1021d2e83a4ef14c52cd1ccd03f2f73d\n"
    },
    {
      "commit": "71175b7f19a4f6cf9cc264feafd820dbafa371fb",
      "tree": "5370e7c7c9f7d1edf148a00548cb1334d5118f8d",
      "parents": [
        "b76c5495c4879fcfa0866b1490031a3123baf9ee"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Oct 09 22:13:55 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Oct 10 11:36:03 2014 +0000"
      },
      "message": "Cleanup baseline register allocator.\n\n- Use three arrays for blocking regsters instead of\n  one and computing offsets in that array.]\n- Don\u0027t pass blocked_registers_ to methods, just use the field.\n\nChange-Id: Ib698564c31127c59b5a64c80f4262394b8394dc6\n"
    },
    {
      "commit": "360231a056e796c36ffe62348507e904dc9efb9b",
      "tree": "a62ff73c11eaa6694649c98e4c2d872e89149b0c",
      "parents": [
        "2072c465cfff077da257bdf14f1f1b2690c946c8"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Oct 08 21:07:48 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Oct 09 15:21:57 2014 +0100"
      },
      "message": "Fix code generation of materialized conditions.\n\nMove the logic for knowing if a condition needs to be materialized\nin an optimization pass (so that the information does not change\nas a side effect of another optimization).\n\nAlso clean-up arm and x86_64 codegen:\n- arm: ldr and str are for power-users when a constant is\n  in play. We should use LoadFromOffset and StoreToOffset.\n- x86_64: fix misuses of movq instead of movl.\n\nChange-Id: I01a03b91803624be2281a344a13ad5efbf4f3ef3\n"
    },
    {
      "commit": "56b9ee6fe1d6880c5fca0e7feb28b25a1ded2e2f",
      "tree": "34e5163967f59a98e64f2c89489ed7b76334b48a",
      "parents": [
        "a3c4d72210de174552f47b2d117b1946f274af1e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Oct 09 11:47:51 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Oct 09 14:42:13 2014 +0100"
      },
      "message": "Stop converting from Location to ManagedRegister.\n\nNow the source of truth is the Location object that knows\nwhich register (core, pair, fpu) it needs to refer to.\n\nChange-Id: I62401343d7479ecfb24b5ed161ec7829cda5a0b1\n"
    },
    {
      "commit": "7fb49da8ec62e8a10ed9419ade9f32c6b1174687",
      "tree": "8b1bec67452b84809cecd5645543e1f885ccbd44",
      "parents": [
        "4a1b4679cda2f0d2893b8e3f910c21231849291c"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Oct 06 09:12:41 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Oct 07 20:19:47 2014 +0100"
      },
      "message": "Add support for floats and doubles.\n\n- Follows Quick conventions.\n- Currently only works with baseline register allocator.\n\nChange-Id: Ie4b8e298f4f5e1cd82364da83e4344d4fc3621a3\n"
    },
    {
      "commit": "3c04974a90b0e03f4b509010bff49f0b2a3da57f",
      "tree": "52649104e3e80272c3774793350f4d9f260ae732",
      "parents": [
        "c0d36abb12cdbb9469039c1dc153a586bd984015"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Sep 24 18:10:46 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Sep 25 12:23:40 2014 +0100"
      },
      "message": "Optimize suspend checks in optimizing compiler.\n\n- Remove the ones added during graph build (they were added\n  for the baseline code generator).\n- Emit them at loop back edges after phi moves, so that the test\n  can directly jump to the loop header.\n- Fix x86 and x86_64 suspend check by using cmpw instead of cmpl.\n\nChange-Id: I6fad5795a55705d86c9e1cb85bf5d63dadfafa2a\n"
    },
    {
      "commit": "3bca0df855f0e575c6ee020ed016999fc8f14122",
      "tree": "15e15c8290ad314c29ca608f51d89d4db68fd9ba",
      "parents": [
        "d41491adb23764f28a80cbb7f2bd7af6491cd892"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Sep 19 11:01:00 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Sep 23 13:57:30 2014 +0100"
      },
      "message": "Support for saving and restoring live registers in a slow path.\n\nAnd use it in suspend check slow paths.\n\nChange-Id: I79caf28f334c145a36180c79a6e2fceae3990c31\n"
    },
    {
      "commit": "e982f0b8e809cece6f460fa2d8df25873aa69de4",
      "tree": "df729d47439f7243b498dd4503a5f7aa41a4818b",
      "parents": [
        "f031724abf4f215e1627ff837f87cad5d7a25165"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Aug 13 02:11:24 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Sep 17 09:53:50 2014 +0100"
      },
      "message": "Implement invoke virtual in optimizing compiler.\n\nAlso refactor 004 tests to make them work with both Quick and\nOptimizing.\n\nChange-Id: I87e275cb0ae0258fc3bb32b612140000b1d2adf8\n"
    },
    {
      "commit": "3c7bb98698f77af10372cf31824d3bb115d9bf0f",
      "tree": "1cd4cc18babfbb16ab908f23929fa88d7678f06b",
      "parents": [
        "98cc1e552c2ccbe5d51bc81d49e79119280f5416"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jul 23 16:04:16 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Jul 28 15:44:28 2014 +0100"
      },
      "message": "Implement array get and array put in optimizing.\n\nAlso fix a couple of assembler/disassembler issues.\n\nChange-Id: I705c8572988c1a9c4df3172b304678529636d5f6\n"
    },
    {
      "commit": "f12feb8e0e857f2832545b3f28d31bad5a9d3903",
      "tree": "0a7320caf995441ea4577875abaf731fc37dd0a9",
      "parents": [
        "ebb6b5c90857f390db5a4f840bbe67b3a59a22d8"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jul 17 18:32:41 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Jul 22 16:07:59 2014 +0100"
      },
      "message": "Stack overflow checks and NPE checks for optimizing.\n\nChange-Id: I59e97448bf29778769b79b51ee4ea43f43493d96\n"
    },
    {
      "commit": "96f89a290eb67d7bf4b1636798fa28df14309cc7",
      "tree": "ca2b484a18107f8253aa7774cde304586a31bc60",
      "parents": [
        "4436e926aa8e64ac7e4c4afb81f2a59b2477045a"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jul 11 10:57:49 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Jul 21 09:54:20 2014 +0100"
      },
      "message": "Add assembly operations with constants in optimizing compiler.\n\nChange-Id: I5bcc35ab50d4457186effef5592a75d7f4e5b65f\n"
    },
    {
      "commit": "ab032bc1ff57831106fdac6a91a136293609401f",
      "tree": "5891daefe635283443a255a811ab6a3f3b8a62cd",
      "parents": [
        "635561b86ac03f5562bdb779baa6db12f31b3cae"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Jul 15 12:55:21 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Jul 15 12:58:29 2014 +0100"
      },
      "message": "Fix a braino in the stack layout.\n\nAlso do some refactoring to have this code be just in CodeGenerator.\n\nChange-Id: I88de109889138af8d60027973c12a64bee813cb7\n"
    },
    {
      "commit": "e50383288a75244255d3ecedcc79ffe9caf774cb",
      "tree": "8858489463a57c7b50f7db4d972abec21302b7a7",
      "parents": [
        "cf90ba7ebe00346651f3b7ce1e5b1f785f7caabd"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jul 04 09:41:32 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Jul 14 10:06:11 2014 +0100"
      },
      "message": "Support fields in optimizing compiler.\n\n- Required support for temporaries, to be only used by baseline compiler.\n- Also fixed a few invalid assumptions around locations and instructions\n  that don\u0027t need materialization. These instructions should not have an Out.\n\nChange-Id: Idc4a30dd95dd18015137300d36bec55fc024cf62\n"
    },
    {
      "commit": "412f10cfed002ab617c78f2621d68446ca4dd8bd",
      "tree": "bbd9dddd0436da566365ada5deb1840e315e1b11",
      "parents": [
        "d6ab04646d8eec6f24b200f8649f3d942d9ad17e"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 19 10:00:34 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jul 02 16:00:32 2014 +0100"
      },
      "message": "Support longs in the register allocator for x86_64.\n\nChange-Id: I7fb6dfb761bc5cf9e5705682032855a0a70ca867\n"
    },
    {
      "commit": "86dbb9a12119273039ce272b41c809fa548b37b6",
      "tree": "a4626e21ae16a9a5e133ea3e5e95b58d2ea4d8e5",
      "parents": [
        "c936622863a50bdda9b10062515dfc02a8c8b652"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jun 04 11:12:39 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jun 12 10:02:06 2014 +0100"
      },
      "message": "Final CL to enable register allocation on x86.\n\nThis CL implements:\n1) Resolution after allocation: connecting the locations\n   allocated to an interval within a block and between blocks.\n2) Handling of fixed registers: some instructions require\n   inputs/output to be at a specific location, and the allocator\n   needs to deal with them in a special way.\n3) ParallelMoveResolver::EmitNativeCode for x86.\n\nChange-Id: I0da6bd7eb66877987148b87c3be6a983b4e3f858\n"
    },
    {
      "commit": "a7062e05e6048c7f817d784a5b94e3122e25b1ec",
      "tree": "a5d6b64ae6d5352f761fc2547bda863281adbe40",
      "parents": [
        "8b5b1e5593ffa77c393e4172b71a3d5a821d2ed8"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu May 22 12:50:17 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon May 26 11:31:38 2014 +0100"
      },
      "message": "Add a linear scan register allocator to the optimizing compiler.\n\nThis is a \"by-the-book\" implementation. It currently only deals\nwith allocating registers, with no hint optimizations.\n\nThe changes remaining to make it functional are:\n- Allocate spill slots.\n- Resolution and placements of Move instructions.\n- Connect it to the code generator.\n\nChange-Id: Ie0b2f6ba1b98da85425be721ce4afecd6b4012a4\n"
    },
    {
      "commit": "a7aca370a7d62ca04a1e24423d90e8020d6f1a58",
      "tree": "65d501b0f9711abddbea1a9d06623baafa4ae2b3",
      "parents": [
        "5dee5df89aa2cefef6c886d5b9b642cc6f1c595b"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Apr 28 17:47:12 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Apr 29 10:55:30 2014 +0100"
      },
      "message": "Setup policies for register allocation.\n\nChange-Id: I857e77530fca3e2fb872fc142a916af1b48400dc\n"
    },
    {
      "commit": "a747a392fb5f88d2ecc4c6021edf9f1f6615ba16",
      "tree": "fc5f08b127f3cf6bfb933504070109d46a455bb9",
      "parents": [
        "c2b2bbf1bbdf6273298b79d6006611593ed9f3a0"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Apr 17 14:56:23 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Apr 17 15:16:00 2014 +0100"
      },
      "message": "Code cleanup in preparation for x64 backend.\n\n- Use InvokeDexCallingConventionVisitor for setting\n  up HParameterValues\n- Use kVregSize instead of kX86WordSize when dealing with\n  virtual registers.\n\nChange-Id: Ia520223010194c70a3ff0ed659077f55cec4e7d8\n"
    },
    {
      "commit": "01bc96d007b67fdb7fe349232a83e4b354ce3d08",
      "tree": "1ed36c2d7c0fb204e6f276bd9853153d9350ad1d",
      "parents": [
        "2be6fc74bce10ac68d3d1b39a5019f520ad170ea"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Apr 11 17:43:50 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Apr 16 14:21:12 2014 +0100"
      },
      "message": "Long support in optimizing compiler.\n\n- Add stack locations to the Location class.\n- Change logic of parameter passing/setup by setting the\n  location of such instructions the ones for the calling\n  convention.\n\nChange-Id: I4730ad58732813dcb9c238f44f55dfc0baa18799\n"
    },
    {
      "commit": "707c809f661554713edfacf338365adca8dfd3a3",
      "tree": "21aaa53a3beb7d73fb2af9ab55bee7a538254fcb",
      "parents": [
        "7efad5d3a806a15166109837439f2e149031feef"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Apr 04 10:50:14 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Apr 04 10:50:14 2014 +0100"
      },
      "message": "Use target-specific word instead of runtime word.\n\nChange-Id: Ia11dc3cc520a1a5c7bd017013e5699af9570ce91\n"
    },
    {
      "commit": "4a34a428c6a2588e0857ef6baf88f1b73ce65958",
      "tree": "a9f025c17752a175c4e6a203c01e935cb438efb1",
      "parents": [
        "8549cf9d83688f7decbbea2a8de761ce29e95f3c"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Apr 03 10:38:37 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Apr 03 17:09:22 2014 +0100"
      },
      "message": "Support passing arguments to invoke-static* instructions.\n\n- Stop using the frame pointer for accessing locals.\n- Stop emulating a stack when doing code generation. Instead,\n  rely on dex register model, where instructions only reference\n  registers.\n\nChange-Id: Id51bd7d33ac430cb87a53c9f4b0c864eeb1006f9\n"
    },
    {
      "commit": "8ccc3f5d06fd217cdaabd37e743adab2031d3720",
      "tree": "ec8c904baafb4d9b9bfd582245e2d780bcdfaade",
      "parents": [
        "ad174d1b54bf2fa477bec71a0ca93595f54b8fe9"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Mar 19 10:34:11 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Mar 31 09:44:40 2014 +0100"
      },
      "message": "Add support for invoke-static in optimizing compiler.\n\nSupport is limited to calls without parameters and returning\nvoid. For simplicity, we currently follow the Quick ABI.\n\nChange-Id: I54805161141b7eac5959f1cae0dc138dd0b2e8a5\n"
    },
    {
      "commit": "787c3076635cf117eb646c5a89a9014b2072fb44",
      "tree": "3c9c6c6d56e3900cf2255a5d1ade008ec6a40681",
      "parents": [
        "b9d50a9829b795932eac4cc50a99b4ce80b0ecb4"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Mar 17 10:20:19 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Mar 18 11:20:20 2014 +0000"
      },
      "message": "Plug new optimizing compiler in compilation pipeline.\n\nAlso rename accessors to ART\u0027s conventions.\n\nChange-Id: I344807055b98aa4b27215704ec362191464acecc\n"
    },
    {
      "commit": "bab4ed7057799a4fadc6283108ab56f389d117d4",
      "tree": "ea1bf495458fd9f7a3ffbed0ea4e1dda5a0b8184",
      "parents": [
        "37d4c1db4d705f5a28001f65afdd68d0527948d8"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Mar 11 17:53:17 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Mar 13 09:23:12 2014 +0000"
      },
      "message": "More code generation for the optimizing compiler.\n\n- Add HReturn instruction\n- Generate code for locals/if/return\n- Setup infrastructure for register allocation. Currently\n  emulate a stack.\n\nChange-Id: Ib28c2dba80f6c526177ed9a7b09c0689ac8122fb\n"
    },
    {
      "commit": "d4dd255db1d110ceb5551f6d95ff31fb57420994",
      "tree": "93c9dfff8d16f2b9675c35477cc4bcd8ea3f630c",
      "parents": [
        "b565506a63e75dac4a8bb9dd54dabf5259e5b95f"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Feb 28 10:23:58 2014 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue Mar 04 16:19:11 2014 +0000"
      },
      "message": "Add codegen support to the optimizing compiler.\n\nChange-Id: I9aae76908ff1d6e64fb71a6718fc1426b67a5c28\n"
    }
  ]
}