)]}'
{
  "log": [
    {
      "commit": "8e3acdd132aef1391676a5db2696804900aacd8e",
      "tree": "df23f2cf3d5927f9b189bee1e386c80981db6bae",
      "parents": [
        "fbde4dd1cb6db729e3f3ee5bdae0cdd824d73054"
      ],
      "author": {
        "name": "Serguei Katkov",
        "email": "serguei.i.katkov@intel.com",
        "time": "Tue Jul 15 12:01:00 2014 +0700"
      },
      "committer": {
        "name": "Serguei Katkov",
        "email": "serguei.i.katkov@intel.com",
        "time": "Fri Jul 18 13:59:18 2014 +0700"
      },
      "message": "x86_64: Fix GenDalvikArgsRange for 64-bit ref\n\n32-bit virtual register can be in 64-bit solo register.\nSo we should not compute the size of virtual register\nbasing on size of phyical register.\n\nChange-Id: I4e11be13df8469be63808d0ce9d1ca6f80bef483\nSigned-off-by: Serguei Katkov \u003cserguei.i.katkov@intel.com\u003e\n"
    },
    {
      "commit": "b6564c19c5e14a3caa3f8da423b0da510fda7026",
      "tree": "a9eb05b2a008dd36c43ee590d2e0fb84742dc3f1",
      "parents": [
        "1528b02c4d5241e785bb680f13de70c355e67429"
      ],
      "author": {
        "name": "Chao-ying Fu",
        "email": "chao-ying.fu@intel.com",
        "time": "Tue Jun 24 13:24:36 2014 -0700"
      },
      "committer": {
        "name": "Chao-ying Fu",
        "email": "chao-ying.fu@intel.com",
        "time": "Tue Jun 24 13:41:24 2014 -0700"
      },
      "message": "x86_64: Fix wide argument increment\n\nThis patch fixes to always increment the index for a wide argument,\nand fixes the index upper bound.\nOtherwise, the mapping may be incorrect.\n\nChange-Id: I0116d8fd0a0a5c1270a23129c73a9e3651132977\nSigned-off-by: Chao-ying Fu \u003cchao-ying.fu@intel.com\u003e\nSigned-off-by: Serguei Katkov \u003cserguei.i.katkov@intel.com\u003e\n"
    },
    {
      "commit": "58994cdb00b323339bd83828eddc53976048006f",
      "tree": "a1ec67c5b04cf99439619bf972a58b6d46dd2823",
      "parents": [
        "9529d6273777ee297a8aa7513e8172775f0496df"
      ],
      "author": {
        "name": "Dmitry Petrochenko",
        "email": "dmitry.petrochenko@intel.com",
        "time": "Sat May 17 01:02:18 2014 +0700"
      },
      "committer": {
        "name": "Dmitry Petrochenko",
        "email": "dmitry.petrochenko@intel.com",
        "time": "Sat Jun 07 01:28:05 2014 +0000"
      },
      "message": "x86_64: Hard Float ABI support in QCG\n\nThis patch shows our efforts on resolving the ART limitations:\n - passing \"float\"/\"double\" arguments via FPR\n - passing \"long\" arguments via single GPR, not pair\n - passing more than 3 agruments via GPR.\n\nWork done:\n - Extended SpecialTargetRegister enum with kARG4, kARG5, fARG4..fARG7.\n - Created initial LoadArgRegs/GenDalvikX/FlushIns version in X86Mir2Lir.\n - Unlimited number of long/double/float arguments support\n - Refactored (v2)\n\nChange-Id: I5deadd320b4341d5b2f50ba6fa4a98031abc3902\nSigned-off-by: Serguei Katkov \u003cserguei.i.katkov@intel.com\u003e\nSigned-off-by: Dmitry Petrochenko \u003cdmitry.petrochenko@intel.com\u003e\nSigned-off-by: Chao-ying Fu \u003cchao-ying.fu@intel.com\u003e\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n"
    }
  ]
}