)]}' { "log": [ { "commit": "a556e6ba500ba54d1ca90d6a947dd962d9c287c7", "tree": "f9e747c6218ca741c7b0783a9d10dedf22dd36b3", "parents": [ "b0ddceb337f614dc2600d19b82fb4a6596aa7d4c" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@mips.com", "time": "Wed Dec 13 12:09:42 2017 +0100" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@mips.com", "time": "Wed Jan 03 17:40:01 2018 +0100" }, "message": "MIPS: InstructionCodeGeneratorMIPS*::DivRemByPowerOfTwo()\n\nReplace [d]sll+[d]srl with [d]ins on R2+.\n\nChange-Id: I7587e46c47c8ce413d81a5c6c29d91e32a14d855\n" }, { "commit": "72aba71d00dd0c420a6ff196066e9378339d46d8", "tree": "ebe2840351820f536b11f1c0f4628205cd6c1251", "parents": [ "3b7ce4ecc6994ea73022c1c4d2df7a3f4fc7471c" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@mips.com", "time": "Mon Oct 30 15:47:20 2017 +0100" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@mips.com", "time": "Wed Nov 08 10:12:18 2017 +0100" }, "message": "MIPS: Add asub_s/u.df\n\nThese instructions are needed for implementing Sum-of-Abs-Differences\nvisitor.\n\nTest: mma test-art-host-gtest\nChange-Id: Ie708f30a450b0558215f59f21bb49b68c852f247\n" }, { "commit": "3309c01e55821f693e3b9cec0ef24969edf2528f", "tree": "cacb4a3775166297b1c9bb9e6236ab901ad725d4", "parents": [ "24276374dcaf95bfc52be2b8193eb4e337de62e4" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Fri Oct 13 14:34:32 2017 +0200" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Thu Oct 19 11:24:55 2017 +0200" }, "message": "MIPS: Introduce a few MSA instructions\n\nThese instructions are needed for SIMD reduction.\nAlso added assembler tests for each instruction.\n\nTest: mma test-art-host-gtest\n\nChange-Id: I0f02618a14b4cbcc3b81ce51dd2586fa4cdbfd18\n" }, { "commit": "0cab65610a6a984a94ef4c3f232fe0273e78d95b", "tree": "669fa607f4cd9ad8eef9223bb124fb72265a06b3", "parents": [ "2e53f8f69f8c4175085e337445ec42aa045a2f7f" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Jul 25 15:19:36 2017 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Sun Jul 30 20:09:26 2017 -0700" }, "message": "MIPS: Eliminate hard-coded offsets in branches\n\nThe bulk of the change is in the assemblers and their\ntests.\n\nThe main goal is to introduce \"bare\" branches to labels\n(as opposed to the existing bare branches with relative\noffsets, whose direct use we want to eliminate).\nThese branches\u0027 delay/forbidden slots are filled\nmanually and these branches do not promote to long (the\nbranch target must be within reach of the individual\nbranch instruction).\n\nThe secondary goal is to add more branch tests (mainly\nfor bare vs non-bare branches and a few extra) and\nrefactor and reorganize the branch test code a bit.\n\nThe third goal is to improve idiom recognition in the\ndisassembler, including branch idioms and a few others.\n\nFurther details:\n- introduce bare branches (R2 and R6) to labels, making\n R2 branches available for use on R6\n- make use of the above in the code generators\n- align beqz/bnez with their GNU assembler encoding to\n simplify and shorten the test code\n- update the CFI test because of the above\n- add trivial tests for bare and non-bare branches\n (addressing existing debt as well)\n- add MIPS32R6 tests for long beqc/beqzc/bc (debt)\n- add MIPS64R6 long beqzc test (debt)\n- group branch tests together\n- group constant/literal/address-loading tests together\n- make the disassembler recognize:\n - b/beqz/bnez (beq/bne with $zero reg)\n - nal (bltzal with $zero reg)\n - bal/bgezal (bal \u003d bgezal with $zero reg)\n - move (or with $zero reg)\n - li (ori/addiu with $zero reg)\n - dli (daddiu with $zero reg)\n- disassemble 16-bit immediate operands (in andi, ori,\n xori, li, dli) as signed or unsigned as appropriate\n- drop unused instructions (bltzl, bltzall, addi) from\n the disassembler as there are no plans to use them\n\nTest: test-art-host-gtest\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-gtest\nTest: testrunner.py --target --optimizing\nTest: same tests as above on CI20\nTest: booted MIPS32R2 in QEMU\n\nChange-Id: I62b74a6c00ce0651528114806ba24a59ba564a73\n" }, { "commit": "b3d79e430a4c0a447121890514cdee48e4675df4", "tree": "ebc0f5fc16d5caf009f59550407abadbc40415ff", "parents": [ "03ce1df8f9b1b8d207fc685fd084b96697a50182" ], "author": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Tue Jul 25 11:20:52 2017 +0200" }, "committer": { "name": "Lena Djokic", "email": "Lena.Djokic@imgtec.com", "time": "Tue Jul 25 14:27:30 2017 +0200" }, "message": "MIPS: Add maddv/msubv MSA instructions\n\nAdded maddv.df, msubv.df, fmadd.df and fmsub.df MSA instructions\nin assembler, disassembler and tests.\n\nThese instructions are needed for multiplyaccumulate support in\nART Vectorizer.\n\nTest: mma test-art-host-gtest\n\nChange-Id: Idef7faaeed47f1fef83fa58676ce664afe24ffe8\n" }, { "commit": "43e99b099a8ca71eda14d8009fd38cb0d441b694", "tree": "627382bd12b0321c54aa7d06fa5092313b7634c3", "parents": [ "6375a04cae864416499865453fecd2b50706b3b2" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Jun 28 10:53:58 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Mon Jul 10 17:37:08 2017 +0200" }, "message": "MIPS: Print register names instead of register numbers in disassembler\n\nTest: ./testrunner.py --optimizing --target on CI20 and in QEMU\nTest: mma test-art-host-gtest\n\nChange-Id: I1fc375ae34ee8fd994192705c45d8f30a35dfc56\n" }, { "commit": "658263ec2fdc7758dd73c41cdcf0babcdef1e48d", "tree": "493f3cb75d9d856aaade47dd2d008756f9e488a5", "parents": [ "11d72c608e0565fabcf6b2d6c13fbc85c560a608" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Jun 07 09:35:53 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Jun 07 09:41:42 2017 +0200" }, "message": "MIPS64: Add min/max MSA instructions\n\nAdded min_s.df, max_s.df, min_u.df, max_u.df, fmin.df and fmax.df MSA\ninstructions in assembler, disassembler and tests.\n\nThese instructions are needed for min/max support in ART Vectorizer.\n\nTest: mma test-art-host-gtest\nChange-Id: I4e8dd18ca501ac09d938a49388e4a43116660ec9\n" }, { "commit": "3837011236058617292bee831708449e5100c08c", "tree": "1f9d72542f9309017433f3a1fe13a5a2dac4e000", "parents": [ "7e4f71f9014c5dc573b4dbbf7faefc4c72d5f55d" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed May 10 14:30:28 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu May 11 10:35:34 2017 +0200" }, "message": "MIPS64: Add ilvr.df MSA instructions\n\nThese instructions are needed for compressed string support\nin ART Vectorizer.\n\nTest: mma test-art-host-gtest\nChange-Id: I269473bb8bcce5aba72201380bb71860e5498d73\n" }, { "commit": "80248d7ba4e952f0e0110c036b48963080ef9470", "tree": "887cbde7b310371d8ecba019cec0b2a1000e520a", "parents": [ "6d3c61d8c6d2f96dec8345263c948fae3caa4e1a" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Apr 20 11:55:47 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Apr 21 16:11:50 2017 +0200" }, "message": "MIPS64: Add add_a.df, ave_s/u.df and aver_s/u.df MSA instructions\n\nThese instructions are needed for implementing VecAbs and\nVecHalvingAdd visitors.\n\nTest: mma test-art-host-gtest\n\nChange-Id: Idaec03ea32bbeaba9cb7476dd0f740aa4d9cfa70\n" }, { "commit": "3f44403fb5b6c9c6176339ab5888e97d0b617746", "tree": "765e3d3968b48fa5236177905fa57c5b60e57653", "parents": [ "bb75449355575a4b1ae72147b80cc7b225092149" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Mar 31 14:38:20 2017 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Mar 31 14:38:55 2017 +0200" }, "message": "MIPS64: Add ldi.df MSA instruction\n\nAlso fixes RepeatTemplatedRegisterImmBits template.\n\nTest: mma test-art-host-gtest\n\nChange-Id: Ib23f8a65ba924623f8c3a2d75d4ec4491d18feb0\n" }, { "commit": "5a9e51d39ed3d1015f20b3d12b35747612cca40e", "tree": "17d4d1e616d5a516dc8187f165fc68ee97ada185", "parents": [ "8f2b925473cfdc7650cef407102957befe0c6bb5" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Mar 16 16:11:43 2017 +0000" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Mar 17 11:17:49 2017 +0100" }, "message": "Revert \"Revert \"Introduce a number of MSA instructions for MIPS64\"\"\n\nThis reverts commit 219bf253e5158c4f3438e70864b8bf7235c1e193.\n\nFixed memory leak in assembler_mips64_test.cc.\n\nTest: mma valgrind-test-art-host-gtest-assembler_mips64_test64\n\nChange-Id: I238833fd4555623c2716432fc67eab7696f1e28e\n" }, { "commit": "219bf253e5158c4f3438e70864b8bf7235c1e193", "tree": "0ba845434b3b5679ee62b099c42ad455b4dcc37d", "parents": [ "dcabc8b740bf3066d59348ffdf21c164d2b27cb4" ], "author": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 15 20:37:50 2017 +0000" }, "committer": { "name": "Aart Bik", "email": "ajcbik@google.com", "time": "Wed Mar 15 20:37:50 2017 +0000" }, "message": "Revert \"Introduce a number of MSA instructions for MIPS64\"\n\nThis reverts commit dcabc8b740bf3066d59348ffdf21c164d2b27cb4.\n\n\nReason:\nFAILING TESTS\nvalgrind-test-art-host-gtest-assembler_mips64_test32\nninja: build stopped: subcommand failed.\n19:36:36 ninja failed with: exit status 1\nmake: *** [run_soong_ui] Error 1\n\nChange-Id: If658375528d2a0f34bb6b22b6565fab1d863b3f5\n" }, { "commit": "dcabc8b740bf3066d59348ffdf21c164d2b27cb4", "tree": "1b16fe71dc17f5e3fad5e1f6a865141b5d22da6b", "parents": [ "96cc0a004b5685d8a3fea3cee3105fbbff73437f" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Fri Mar 10 11:53:48 2017 +0100" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Tue Mar 14 17:21:19 2017 +0100" }, "message": "Introduce a number of MSA instructions for MIPS64\n\nAdded a number of MSA (The MIPS SIMD Architecture) instructions.\nAdded assembler tests for each instruction.\nMade necessary changes in disassembler for these instructions.\n\nTest: mma test-art-host-gtest\n\nChange-Id: I380f02c6ae5424a96ad999037153228acb07a108\n" }, { "commit": "66e3919bc42ddca40302ce5ee32e3ade248dd2b6", "tree": "3800e8499317efc4b5bca06e483b2bcbd9da8d9d", "parents": [ "6a14c622700e088173ba909799c1e1785aeb4b34", "e36605910cb13da1440fb9d7a8293842a9209c97" ], "author": { "name": "Treehugger Robot", "email": "treehugger-gerrit@google.com", "time": "Tue Jan 03 11:13:50 2017 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Jan 03 11:13:51 2017 +0000" }, "message": "Merge \"MIPS64: java.lang.String.getChars\"" }, { "commit": "19f6c696bbb7a17d8ac521b316c40f9cbef32151", "tree": "6ce87f3ba9f224efc0036d3ab99e4272c48eeddb", "parents": [ "aea9ffece7eb32f3884a4ad0553e1df4d90fd9e4" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Nov 30 19:19:55 2016 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Dec 13 14:07:16 2016 -0800" }, "message": "MIPS64: Improve method invocation.\n\nImprovements include:\n- support for all kinds of method loads and static/direct calls\n- 32-bit and 64-bit literals for the above and future work\n- shorter instruction sequences for recursive static/direct calls\nAlso:\n- include the MIPS64 dinsu instruction (missed earlier) and minor\n clean-up in the disassembler\n- properly prefix constant names with \u0027k\u0027 in relative patcher tests\n\nTest: test-art-host-gtest\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: \"make -j1 ART_TEST_DEFAULT_COMPILER\u003dfalse ART_TEST_OPTIMIZING\u003dtrue\n ART_TEST_INTERPRETER\u003dfalse ART_TEST_JIT\u003dfalse\n ART_TEST_PIC_TEST\u003dtrue test-art-target-run-test64\"\n\nChange-Id: I19876fa5316b68531af7dfddfce90d2068433116\n" }, { "commit": "e36605910cb13da1440fb9d7a8293842a9209c97", "tree": "6bb2097042a3ee4f0e0b64c4e22575823ca82c11", "parents": [ "b487af4fc80ffabe0219657a9690be1316dab8e7" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Wed Nov 09 11:13:42 2016 -0800" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Fri Dec 02 16:22:56 2016 -0800" }, "message": "MIPS64: java.lang.String.getChars\n\nTest: run-test --64 --optimizing 020-string\nTest: run-test --64 020-string\nTest: run-test --64 --no-prebuild --optimizing 020-string\nTest: run-test --64 --no-prebuild 020-string\nTest: run-test --64 --optimizing 082-inline-execute\nTest: run-test --64 082-inline-execute\nTest: run-test --64 --no-prebuild --optimizing 082-inline-execute\nTest: run-test --64 --no-prebuild 082-inline-execute\nTest: mma -j2 ART_TEST_OPTIMIZING\u003dtrue test-art-target-run-test\nTest: mma test-art-target-gtest -j2\nTest: booted MIPS64R6 emulator.\n\nNote: All tests run against MIPS64 QEMU.\n\nChange-Id: I48b9a87465f2516044a2e4f598cc5dce56b0d1c9\n" }, { "commit": "674b9ee50c812d684a27a28cf09098195f068f3d", "tree": "9b109adff71b48aa531628bf07644bccfc580fa3", "parents": [ "c6c5f6ce1c9cc44f859bbbc447478e4934be0fee" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Sep 20 14:54:15 2016 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Oct 20 15:03:43 2016 -0700" }, "message": "MIPS32: Implement HSelect\n\nTest: booted MIPS32R2 in QEMU\nTest: test-art-target-run-test-optimizing (MIPS32R2) on CI20\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-run-test-optimizing (MIPS32R6) in QEMU\nTest: test-art-host-gtest\n\nChange-Id: I8a8127d8d29cb5df84ed6f4fd4478f8d889e5cb7\n" }, { "commit": "bda1d606f2d31086874b68edd9254e3817d8049c", "tree": "db07417935fe72e99c3da60152e13f0620c7d8d7", "parents": [ "d14d515df39cd963179088b8721768f9645243aa" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Aug 29 17:43:45 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Sep 08 10:13:47 2016 -0700" }, "message": "ART: Detach libart-disassembler from libart\n\nSome more intrusive changes than I would have liked, as long as\nART logging is different from libbase logging.\n\nFix up some includes.\n\nBug: 15436106\nBug: 31338270\nTest: m test-art-host\nChange-Id: I9fbe4b85b2d74e079a4981f3aec9af63b163a461\n" }, { "commit": "372f3a374681ef11f003460e14249adb7bc8313d", "tree": "b6d2bd95975a0ce1096dc2aa761f8e6b30e42b18", "parents": [ "9c07ab332b8ebbcb1586c311bfcb75e19b8a35b4" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Aug 19 10:49:06 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Aug 19 16:46:56 2016 -0700" }, "message": "ART: Add thread offset printing hook to disassembler\n\nTo prepare separation of disassembler from libart, add a function\nhook to the disassembler options for thread offset name printing.\n\nBug: 15436106\nChange-Id: I9e9b7e565ae923952c64026f675ac527b560f51b\n" }, { "commit": "542451cc546779f5c67840e105c51205a1b0a8fd", "tree": "11e09bb5abaee12dddffefbe7e425291076dfa7a", "parents": [ "85c4a4b8c9eabfe16e4e49f9b4aa78c1bf4be023" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jul 26 09:02:02 2016 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Aug 01 18:54:48 2016 -0700" }, "message": "ART: Convert pointer size to enum\n\nMove away from size_t to dedicated enum (class).\n\nBug: 30373134\nBug: 30419309\nTest: m test-art-host\nChange-Id: Id453c330f1065012e7d4f9fc24ac477cc9bb9269\n" }, { "commit": "e3fb245fbdb5e91cf8a9750504df40bd629e0080", "tree": "a3882db92b7942b2edd6add3090b5c875fef2d09", "parents": [ "1fdb340de4e608a88e8683c857cad5d0da2c16de" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue May 10 16:08:05 2016 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Fri Jul 01 14:10:14 2016 -0700" }, "message": "MIPS32: Improve method invocation\n\nImprovements include:\n- CodeGeneratorMIPS::GenerateStaticOrDirectCall() supports:\n - MethodLoadKind::kDirectAddressWithFixup (via literals)\n - CodePtrLocation::kCallDirectWithFixup (via literals)\n - MethodLoadKind::kDexCachePcRelative\n- 32-bit literals to support the above (not ready for general-\n purpose applications yet because RA is not saved in leaf\n methods, but is clobbered on MIPS32R2 when simulating\n PC-relative addressing (MIPS32R6 is OK because it has\n PC-relative addressing with the lwpc instruction))\n- shorter instruction sequences for recursive static/direct\n calls\n\nTested:\n- test-art-host-gtest\n- test-art-target-gtest and test-art-target-run-test-optimizing on:\n - MIPS32R2 QEMU\n - CI20 board\n - MIPS32R6 (2nd arch) QEMU\n\nChange-Id: Id5b137ad32d5590487fd154c9a01d3b3e7e044ff\n" }, { "commit": "a8aaf5a18ad42f3aea9afb3c8d383fe331798c9f", "tree": "56c7500a4c362f56d1c8fec471c61baf810b6658", "parents": [ "12e6e9f3f1352ed58ddd41c7f31831011695b9e4" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Jun 27 14:48:20 2016 -0700" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Thu Jun 30 13:41:14 2016 +0000" }, "message": "MIPS32: Disassemble and test movf.fmt and movt.fmt (missed earlier)\n\nTest: ART gtest assembler_mips_test\nChange-Id: Iafedfafe6ccd76127461d66dfa7984f196be6bd2\n" }, { "commit": "51aff3a6564303cab0b7ac82495b4e2e349c6ff3", "tree": "783344fdc2f757a8fce4ac1b565e2b2798415d2d", "parents": [ "6a329292736c3dd74e9c8cb319c2a233d07fe524" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Mar 17 17:21:45 2016 -0700" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Mar 21 15:23:42 2016 -0700" }, "message": "MIPS32: Implement UnsafeCASInt and UnsafeCASObject intrinsics.\n\nChange-Id: Ie871763b9a36075fd3d70ee6e2e241ae1ccc36cf\n" }, { "commit": "3acee732f9475fbfc6b046e0044b764e7ff5ac01", "tree": "3b87f8b93c427c05e7690ea8d14577ce3e9eb502", "parents": [ "34937e2ed46fa9f56d99e9f32e0bfad050e5e798" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Wed Nov 18 13:31:08 2015 -0800" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Wed Feb 10 16:12:56 2016 -0800" }, "message": "MIPS32: peek*/poke*, and String.charAt intrinsics.\n\n- byte libcore.io.Memory.peekByte(long address)\n- short libcore.io.Memory.peekShort(long address)\n- int libcore.io.Memory.peekInt(long address)\n- long libcore.io.Memory.peekLong(long address)\n- void libcore.io.Memory.pokeByte(long address, byte value)\n- void libcore.io.Memory.pokeShort(long address, short value)\n- void libcore.io.Memory.pokeInt(long address, int value)\n- void libcore.io.Memory.pokeLong(long address, long value)\n- char java.lang.String.charAt(int index)\n\nChange-Id: I5ff30b61d87313d00f0fd3f0ee09f1c454f9c9fa\n" }, { "commit": "92d9060c0cdff7c726549a9d9494e5655404bed7", "tree": "22c1274193e7f1a3bd9872a2455c758394587dee", "parents": [ "376a6f3dbae7b71a6fc2c339ec416d3407277308" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Fri Dec 18 18:16:36 2015 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Jan 04 20:53:44 2016 -0800" }, "message": "MIPS: Implement HRor\n\nThis also fixes differentiation between the SRL and ROTR\ninstructions in the disassembler.\n\nChange-Id: Ie19697f8d6ea8fa4e338adde3e3cf8e4a0383eae\n" }, { "commit": "5c7aed3b9844e240cf785e5885524ac133a04396", "tree": "acc868d1478f0410fda4d0f6de3c60755aa6680e", "parents": [ "1c70f18dce7705ff70147ddebf65a97f66df8d5c" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Nov 25 19:41:54 2015 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Wed Dec 16 15:33:30 2015 -0800" }, "message": "MIPS32: improvements in code generation (mostly 64-bit ALU ops)\n\nSpecifically:\n- Use the delay slot in InvokeRuntime() for direct entry points\n- Use kNoOutputOverlap wherever possible\n- Improve and/or/xor/add/sub with 64-bit integer constants\n- Improve 64-bit shifts by a constant amount on R2+\n- More efficient load/store of 64-bit constants (especially, 0 \u0026 +0.0)\n\nChange-Id: I86d2217c8b5b8e2a9371effc2ce38b9eec62782b\n" }, { "commit": "cd7b0ee296b0462961c63e51d99c9c323e2690df", "tree": "57a9071635389e58a8912d98b99d7e114c1efcc6", "parents": [ "0bbc1727c446ee5f4cc3c28e68127164ef379594" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Thu Dec 03 16:46:38 2015 -0800" }, "committer": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Tue Dec 15 14:29:48 2015 -0800" }, "message": "MIPS32: Fuse long and FP compare \u0026 condition in Optimizing.\n\nThis also does a minor clean-up in the assembler and\nits test.\n\nBug: 25559148\nChange-Id: I9bad3c500b592a09013b56745f70752eb284a842\n" }, { "commit": "e384547851a9d9e5d89ae5bb4c16bfd7d93cc12e", "tree": "41ba461c62b6a89253b59117a68beae05df5006f", "parents": [ "70014c8af8d3a20c2987c308788bc86671bc39e9" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Wed Nov 18 12:27:15 2015 -0800" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Mon Nov 30 17:27:36 2015 -0800" }, "message": "MIPS32: int java.lang.*.numberOfLeadingZeros\n\n- int java.lang.Integer.numberOfLeadingZeros(int)\n- int java.lang.Long.numberOfLeadingZeros(long)\n\nChange-Id: Icaf746cb807863f944ff4ebb5da6e6b2846eac58\n" }, { "commit": "7d4152f3520a3899ab57b61b884a17a2ba49a2ad", "tree": "cb57603e94688a4736798b18d157e4b325885509", "parents": [ "e033ea69bcd1f343c3cf944d78beec726faf348f" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Mon Oct 19 15:17:16 2015 -0700" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Mon Oct 19 17:26:50 2015 -0700" }, "message": "MIPS64: Disassembler support for rotate instructions.\n\nAlso, tighten the tests for recognizing the various shift commands. The\ntests, previously, would be unable to distinguish between \"shift right\nlogical\" and \"rotate right\" commands. In particular:\n\n- SRLV vs. ROTRV\n- DSRLV vs. DROTRV,\n- DSRL vs. DROTR, and\n- DSRL32 vs. DROTR32\n\nChange-Id: I7a6df8ab0d76fd3d34b1207da9915369ad84fa97\n" }, { "commit": "8c434dcc78d497e18590461700894d1c3e96013d", "tree": "6fc88cc839c0415aa90a1bbff25e93a09705d19b", "parents": [ "35ef974da353b13938fb0f3272c03070ad728431" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Aug 26 14:39:44 2015 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Tue Oct 06 16:34:25 2015 +0200" }, "message": "MIPS: Assemblers changes needed for optimizing compiler\n\nAlso add assembler tests for MIPS32.\n\nChange-Id: I3ab1fba7f3b06eb3b5058861946d675494a30775\n" }, { "commit": "2fadd7bb67abf5bc3c5370f9508cfb5959d6e536", "tree": "efdfc90c1cdb4b688c0cdf6c2cf2cfe7b8121d1c", "parents": [ "010c7fd437932e0132fc4b44de6274480573ff30" ], "author": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Fri Aug 14 14:56:10 2015 -0700" }, "committer": { "name": "Chris Larsen", "email": "chris.larsen@imgtec.com", "time": "Thu Sep 10 10:59:11 2015 -0700" }, "message": "Additional MIPS64 instructions needed by intrinsics code.\n\nChange-Id: If2a48300aac7a10dadf485d1765fb5bdeed975fe\n" }, { "commit": "4dda3376b71209fae07f5c3c8ac3eb4b54207aa8", "tree": "0d96a327d1b3a7e09eff178a66c0b5fb946cfc85", "parents": [ "71af6f7aab7491665fe2d6beb9af4c251a99ad56" ], "author": { "name": "Alexey Frunze", "email": "Alexey.Frunze@imgtec.com", "time": "Mon Jun 01 18:31:49 2015 -0700" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Jun 19 15:43:58 2015 +0100" }, "message": "MIPS: Initial version of optimizing compiler for MIPS64R6.\n\nBug: 21555893\nChange-Id: I874dc356eee6ab061a32f8f3df5f8ac3a4ab7dcf\nSigned-off-by: Alexey Frunze \u003cAlexey.Frunze@imgtec.com\u003e\nSigned-off-by: Douglas Leung \u003cdouglas.leung@imgtec.com\u003e\n" }, { "commit": "403e0d55a3e9c18d4228d0aab31dec0c908dc73d", "tree": "22beb87b8be836e2851bb2637446ceb47d9d4389", "parents": [ "1576be32be4a99a1cffdaaf209a3cd67e8b2f88a" ], "author": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Wed Apr 08 16:26:05 2015 +0200" }, "committer": { "name": "Goran Jakovljevic", "email": "Goran.Jakovljevic@imgtec.com", "time": "Thu Apr 09 08:23:53 2015 +0200" }, "message": "[MIPS] Refactoring code for disassembler\n\nCode for mips64 is merged with code for mips.\n\nChange-Id: I2e3f2118c69a189787ae8e7f09adb4ee5c0d00d9\n" }, { "commit": "65b798ea10dd716c1bb3dda029f9bf255435af72", "tree": "774e9901b6917989a63f07f927c3b4d8b921a013", "parents": [ "c411c6cc327d3f2b3b4d1987b07dd442205d9454" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Apr 06 09:35:22 2015 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Apr 06 14:05:07 2015 -0700" }, "message": "ART: Enable more Clang warnings\n\nChange-Id: Ie6aba02f4223b1de02530e1515c63505f37e184c\n" }, { "commit": "027f0ff64c2512b9a5f1f54f3fea1bec481eb0f5", "tree": "9202535f219d7343b4c26d5c43f0bcb7c31650df", "parents": [ "6cc763c8b8157fb42dd44e1dfb84812546500dc1" ], "author": { "name": "Douglas Leung", "email": "douglas.leung@imgtec.com", "time": "Fri Feb 27 19:05:03 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Fri Mar 20 16:51:56 2015 -0700" }, "message": "ART: Add Mips32r6 backend support\n\nAdd Mips32r6 compiler support.\n\nDon\u0027t use deprecated Mips32r2 instructions if running in Mips32r6\nmode.\n\nChange-Id: I54e689aa8c026ccb75c4af515aa2794f471c9f67\n" }, { "commit": "1cd27903529ee10229fa639dc8438a75517de492", "tree": "c3689e5286876ea6deb967a79869bac5d270551f", "parents": [ "f5c224cca603ef1dba9bb80952613facc22598fa" ], "author": { "name": "Douglas Leung", "email": "douglas.leung@imgtec.com", "time": "Fri Feb 13 16:55:57 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Sat Feb 28 00:11:26 2015 +0000" }, "message": "ART: Fix Mips disassembler for some floating point instructions.\n\nChange-Id: I2b661a8dae4cd924c081df85f570007cf645769c\n" }, { "commit": "8d36591d93920e7b7830c3ffee3759b561f5339e", "tree": "3217249ce513848ed93dcec981d6ed4c13c2fc60", "parents": [ "8fccea249b1a6f1469eeea42c2b2cca06ce1c70d" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jan 13 11:32:32 2015 -0800" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Jan 13 11:32:32 2015 -0800" }, "message": "ART: Use jalr instead of jr for Mips\n\nUse the jalr instruction instead of jr in stubs and compiled code.\n\nChange-Id: Idacc5167a5bb0113dc2e7716e4767e5ed07b5e0b\n" }, { "commit": "cf7f19135f0e273f7b0136315633c2abfc715343", "tree": "ffa4d9efd9c45f4b6789acc1f534bb9327052b7e", "parents": [ "aea6888b056be21adf762e066c7f33b8939b8a06" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Oct 22 22:06:39 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Oct 22 22:21:57 2014 -0700" }, "message": "C++11 related clean-up of DISALLOW_..\n\nMove DISALLOW_COPY_AND_ASSIGN to delete functions. By no having declarations\nwith no definitions this prompts better warning messages so deal with these\nby correcting the code.\nAdd a DISALLOW_ALLOCATION and use for ValueObject and mirror::Object.\nMake X86 assembly operand types ValueObjects to fix compilation errors.\nTidy the use of iostream and ostream.\nAvoid making cutils a dependency via mutex-inl.h for tests that link against\nlibart. Push tracing dependencies into appropriate files and mutex.cc.\nx86 32-bit host symbols size is increased for libarttest, avoid copying this\nin run-test 115 by using symlinks and remove this test\u0027s higher than normal\nulimit.\nFix the RunningOnValgrind test in RosAllocSpace to not use GetHeap as it\nreturns NULL when the heap is under construction by Runtime.\n\nChange-Id: Ia246f7ac0c11f73072b30d70566a196e9b78472b\n" }, { "commit": "c7dd295a4e0cc1d15c0c96088e55a85389bade74", "tree": "0c08a2236bc9ba5d9a4dc75d4dd0ed2d76f8f1c6", "parents": [ "94e5af8602150efa95bde35cc9be9891ddf30135" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Oct 21 23:31:19 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Wed Oct 22 12:06:23 2014 -0700" }, "message": "Tidy up logging.\n\nMove gVerboseMethods to CompilerOptions. Now \"--verbose-methods\u003d\" option to\ndex2oat rather than runtime argument \"-verbose-methods:\".\nMove ToStr and Dumpable out of logging.h, move LogMessageData into logging.cc\nexcept for a forward declaration.\nRemove ConstDumpable as Dump methods are all const (and make this so if not\ncurrently true).\nMake LogSeverity an enum and improve compile time assertions and type checking.\nRemove log_severity.h that\u0027s only used in logging.h.\nWith system headers gone from logging.h, go add to .cc files missing system\nheader includes.\nAlso, make operator new in ValueObject private for compile time instantiation\nchecking.\n\nChange-Id: I3228f614500ccc9b14b49c72b9821c8b0db3d641\n" }, { "commit": "2cbaccb67e22c0b313a9785bfc65bcb4b25d0676", "tree": "daeb766e19880b651fd9c4a719c9a07dd7d4bd0e", "parents": [ "bace0378d720a1d2938ec7f6be17e2814671d20a" ], "author": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Sun Sep 14 20:34:17 2014 -0700" }, "committer": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Tue Sep 16 12:50:08 2014 -0700" }, "message": "Avoid printing absolute addresses in oatdump\n\n- Added printing of OatClass offsets.\n- Added printing of OatMethod offsets.\n- Added bounds checks for code size size, code size, mapping table, gc map, vmap table.\n- Added sanity check of 100k for code size.\n- Added partial disassembly of questionable code.\n- Added --no-disassemble to disable disassembly.\n- Added --no-dump:vmap to disable vmap dumping.\n- Reordered OatMethod info to be in file order.\n\nBug: 15567083\n\n(cherry picked from commit 34fa79ece5b3a1940d412cd94dbdcc4225aae72f)\n\nChange-Id: I2c368f3b81af53b735149a866f3e491c9ac33fb8\n" }, { "commit": "dd7624d2b9e599d57762d12031b10b89defc9807", "tree": "c972296737f992a84b1552561f823991d28403f0", "parents": [ "8464a64a50190c06e95015a932eda9511fa6473d" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Mar 14 17:43:00 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Apr 01 08:24:16 2014 -0700" }, "message": "Allow mixing of thread offsets between 32 and 64bit architectures.\n\nBegin a more full implementation x86-64 REX prefixes.\nDoesn\u0027t implement 64bit thread offset support for the JNI compiler.\n\nChange-Id: If9af2f08a1833c21ddb4b4077f9b03add1a05147\n" }, { "commit": "38e12034f1ef2b32e98b6e49cb36b7cc37a7f1be", "tree": "9a879d4034bce742c8b5ef0680c2da2d8da5139d", "parents": [ "fb5b21d1d598b6b42e5d5ca1dac4a040832558fb" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Mar 14 14:06:14 2014 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Mar 14 14:16:04 2014 -0700" }, "message": "x86-64 disassembler support.\n\nChange-Id: I0ae39ae1ffdae2500ff368354f9e4702445176f0\n" }, { "commit": "02ed4c04468ca5f5540c5b704ac3e2f30eb9e8f4", "tree": "fd568452f4ae81868087e9a5f6c04a9051d0ef83", "parents": [ "28c2300d9a85f4e7288fb5d94280332f923b4df3" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Sep 06 13:10:04 2013 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Mon Sep 09 08:33:36 2013 -0700" }, "message": "Move disassembler out of runtime.\n\nBug: 9877500.\nChange-Id: Ica6d9f5ecfd20c86e5230a2213827bd78cd29a29\n" }, { "commit": "7934ac288acfb2552bb0b06ec1f61e5820d924a4", "tree": "43f3acd8af7fd34d4ae7b64f6e06bb8429d74bb8", "parents": [ "fb331d7ca004f39608fcfdae49d38df90c702ea9" ], "author": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Fri Jul 26 10:54:15 2013 -0700" }, "committer": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Fri Jul 26 11:55:10 2013 -0700" }, "message": "Fix cpplint whitespace/comments issues\n\nChange-Id: Iae286862c85fb8fd8901eae1204cd6d271d69496\n" }, { "commit": "7940e44f4517de5e2634a7e07d58d0fb26160513", "tree": "ac90242d96229a6942f6e24ab137bc1f8f2e0025", "parents": [ "5cd9e3b122f276f610980cbaf0d2ad6ed4cd9088" ], "author": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Fri Jul 12 13:46:57 2013 -0700" }, "committer": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Fri Jul 12 17:49:01 2013 -0700" }, "message": "Create separate Android.mk for main build targets\n\nThe runtime, compiler, dex2oat, and oatdump now are in seperate trees\nto prevent dependency creep. They can now be individually built\nwithout rebuilding the rest of the art projects. dalvikvm and jdwpspy\nwere already this way. Builds in the art directory should behave as\nbefore, building everything including tests.\n\nChange-Id: Ic6b1151e5ed0f823c3dd301afd2b13eb2d8feb81\n" }, { "commit": "d74e41b1cce5373aa24fd2fbea735173f6113d5a", "tree": "fa06500c0496aa2954bd2ae32713ba4fd14d4b32", "parents": [ "333a8ec11113e75552093cf8be6fbda2673a5be3" ], "author": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Sun Mar 24 23:47:01 2013 -0700" }, "committer": { "name": "Brian Carlstrom", "email": "bdc@google.com", "time": "Sun Mar 24 23:47:01 2013 -0700" }, "message": "Fixes for comparisons between signed and unsigned values with new jb-mr2 compiler\n\nChange-Id: Ibfcf8dca0b36b29548231c829be3c160c1c6d747\n" }, { "commit": "e222ee0b794f941af4fb1b32fb8224e32942ea7b", "tree": "0b9f5fe6398663c9d871881cf7de28eca8bdfc6f", "parents": [ "1aa246dec5abe212f699de1413a0c4a191ca364a" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Thu Dec 13 14:41:43 2012 -0800" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Thu Dec 13 15:24:45 2012 -0800" }, "message": "Move stringpiece.h and stringprintf.h to base/.\n\nChange-Id: I7f71b4a12f99c5f81771146c66629ae5a947b229\n" }, { "commit": "07ed66b5ae659c452cbe1ab20c3dbf1d6f546461", "tree": "2350745da33df6fcb9fb0c9059e55ea5d5ea8f67", "parents": [ "76b6167407c2b6f5d40ad895b2793a6b037f54b2" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Wed Dec 12 18:34:25 2012 -0800" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Wed Dec 12 18:35:05 2012 -0800" }, "message": "Move logging.h into base/logging.h.\n\nChange-Id: Id68f85f7c3a71b156cb40dec63f94d4fb827f279\n" }, { "commit": "2bcb4a496b7aa00d996df3a070524f7568fb35a1", "tree": "8422ab8d65b7422008094b2eaadec0dad87b2df3", "parents": [ "efc6369224b036a1fb77849f7ae65b3492c832c0" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Thu Nov 08 10:39:18 2012 -0800" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Fri Nov 16 14:01:34 2012 -0800" }, "message": "Add \"kind\" argument to Get/SetVReg.\n\nIn order to determine where a register is promoted its necessary to know\nthe kind of use of the register.\nExtend notion of precise-ness to numeric verifier register types.\nDump verifier output in oatdump.\nDump vregs with their location or constant value.\nIntroduce indenting ostream utility.\n\nChange-Id: Ia3d29497877976bc24465484743bca08236e1768\n" }, { "commit": "b23a7729cf7855fa05345d03a4d84111d5ec7172", "tree": "5313e076b19387db3cbcac95225d3f098f19451d", "parents": [ "137e88f798857321f4007631fdf052d2830ec2c4" ], "author": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Oct 09 16:54:26 2012 -0700" }, "committer": { "name": "Ian Rogers", "email": "irogers@google.com", "time": "Tue Oct 09 16:54:26 2012 -0700" }, "message": "Dump maps inline in disassembled code.\n\nIn pursuit of Bug: 7250540, dump mapping and GC map tables inline such\nas:\n\n0x607333a8: f8dfe11c ldr.w lr, [pc, #284] ; 0x6076416d\n0x607333ac: 1c05 mov r5, r0\n0x607333ae: f8df0144 ldr.w r0, [pc, #324] ; 0x6003ba08\n0x607333b2: 9a0b ldr r2, [sp, #44]\n0x607333b4: f04f0b2f orr r11, pc, ThumbExpand(47)\n0x607333b8: 1c29 mov r1, r5\n0x607333ba: 465b mov r3, r11\n0x607333bc: 2900 cmp r1, #0\n0x607333be: f0008070 beq.w +224 (0x607334a2)\n0x607333c2: 47f0 blx lr\nsuspend point dex PC: 44\nGC map objects: v2 (r7), v3 (r5), v6 ([sp + #84]), v7 (r6)\n...\n\nAs GC map and mapping tables are inline, don\u0027t dump them.\nAlso dump dex instructions before code.\n\nChange-Id: I9f0c04182a4cda6844027eae22e8151f2827dc99\n" }, { "commit": "4f8f04ad94e68d2307a955d6bd72415fc0852725", "tree": "f4c7f58a5149667b5f8e3376064faa81f5b9842e", "parents": [ "3e96a16c27c986275f60afe682d0b2a3064f45c9" ], "author": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Tue Oct 02 18:10:35 2012 -0700" }, "committer": { "name": "jeffhao", "email": "jeffhao@google.com", "time": "Wed Oct 03 13:34:43 2012 -0700" }, "message": "Fix endianness of compiled code and stacks of stubs for MIPS.\n\nThe gtests now all work on MIPS.\n\nChange-Id: I2883ce002f23d75e700366014517c863fb626d09\n" }, { "commit": "60454e8b48663e6e5cb4bb301cec5edf93f8ce54", "tree": "926b9b6cc9379e6ec090d4c36e0698ba76e04380", "parents": [ "f49a495e249534c051d2d10bc3310253bb99b5d3" ], "author": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Wed Apr 25 12:56:03 2012 -0700" }, "committer": { "name": "Elliott Hughes", "email": "enh@google.com", "time": "Wed Apr 25 12:56:03 2012 -0700" }, "message": "MIPS disassembler.\n\n 0x0000: invoke-direct {v0}, Ljava/lang/Object;.\u003cinit\u003e()V // method@163\n 0xf7229004: 8e220050 lw r2, +80(r17) ; stack_end_\n 0xf7229008: 27bdfff8 addiu r29, r29, -8\n 0xf722900c: afb20004 sw r18, +4(r29)\n 0xf7229010: afbf0000 sw r31, +0(r29)\n 0xf7229014: 27a3ffe8 addiu r3, r29, -24\n 0xf7229018: 0062402b sltu r8, r3, r2\n 0xf722901c: 15000010 bne r8, r0, 0xf7229060 ; +68\n 0xf7229020: 00000000 nop\n 0xf7229024: 0060e825 or r29, r3, r0\n 0xf7229028: afa40000 sw r4, +0(r29)\n 0xf722902c: 00a09025 or r18, r5, r0\n 0xf7229030: 8fa40000 lw r4, +0(r29)\n 0xf7229034: 02402825 or r5, r18, r0\n 0xf7229038: 8c840010 lw r4, +16(r4)\n 0xf722903c: 8c840298 lw r4, +664(r4)\n 0xf7229040: 8c820020 lw r2, +32(r4)\n 0xf7229044: 0040f809 jalr r2\n 0xf7229048: 00000000 nop\n 0x0003: return-void\n 0xf722904c: 8fb2001c lw r18, +28(r29)\n 0xf7229050: 8fbf0018 lw r31, +24(r29)\n 0xf7229054: 27bd0020 addiu r29, r29, 32\n 0xf7229058: 03e00008 jr r31\n 0xf722905c: 00000000 nop\n 0x0000: invoke-direct {v0}, Ljava/lang/Object;.\u003cinit\u003e()V // method@163\n 0xf7229060: 27bd0008 addiu r29, r29, 8\n 0xf7229064: 8e2901f4 lw r9, +500(r17) ; pThrowStackOverflowFromCode\n 0xf7229068: 0120f809 jalr r9\n 0xf722906c: 00000000 nop\n\nChange-Id: Ib5b8c9ed91fa92586f3b93793b5fb893e9ac09c2\n" } ] }