)]}'
{
  "log": [
    {
      "commit": "28f6cff854b61e39f953e69ebf3646ee9826ec82",
      "tree": "a98e2bf1746d93079b7abe54e278ba87f0aef360",
      "parents": [
        "06ef9aa6a562a3a1f7c1f9b91aadda5018f8ba86"
      ],
      "author": {
        "name": "David Srbecky",
        "email": "dsrbecky@google.com",
        "time": "Tue Oct 16 15:07:28 2018 +0100"
      },
      "committer": {
        "name": "David Srbecky",
        "email": "dsrbecky@google.com",
        "time": "Mon Oct 22 14:35:07 2018 +0100"
      },
      "message": "Cache the value of MterpShouldSwitchInterpreters()\n\nAdd field to the Thread object which stores the value instead (negated).\nExplicitly update the field when relevant state changes (which is rare).\n\nThis speeds up golem interpreter benchmarks by 3.5%\non average with some benchmarks up to 15% faster.\n\nTest: test.py -b -r --interpreter --host\nChange-Id: If2df0d3bf9e69ab50c30102b2648e997927c34d8\n"
    },
    {
      "commit": "d109e30eab8ba25f8d89be2a83d9036e2d541af2",
      "tree": "24df91603efe9ce8c4a2efd09ac402aceb10df4e",
      "parents": [
        "c916736ca1e375c276df251446baf2ac8ff3eb13"
      ],
      "author": {
        "name": "Alex Light",
        "email": "allight@google.com",
        "time": "Wed Jun 27 10:25:41 2018 -0700"
      },
      "committer": {
        "name": "Alex Light",
        "email": "allight@google.com",
        "time": "Tue Jul 10 08:44:51 2018 -0700"
      },
      "message": "Don\u0027t use StringFactory.newEmptyString in compiled code\n\nWhen compiling debuggable code we would compile a new-instance String\ninstruction into a StringFactory.newEmptyString invoke. This\nadditional invoke could be observed using tracing and is inconsistent\nwith the interpreter, where the string is simply allocated directly.\nIn order to bring these two modes into alignment we added a new\nAllocStringObject quick entrypoint that will be used instead of the\nnormal AllocObject\u003c...\u003e entrypoints when allocating a string. This\nentrypoint directly allocates a new string in the same manner the\ninterpreter does.\n\nNeeds next CL for test to work.\n\nBug: 110884646\nTest: ./test/testrunner/testrunner.py --host --runtime-option\u003d-Xjitthreshold:0 --jit\nTest: Manual inspection of compiled code.\nChange-Id: I7b4b084bcf7dd9a23485c0e3cd2cd04a04b43d3d\n"
    },
    {
      "commit": "4c8e12e66968929b36fac6a2237ca4b04160161e",
      "tree": "d8bbfd72a978c69ef2eef98c37e7869673c52295",
      "parents": [
        "20c64f8d802cc575cc9a1a1f6c493a611b23e2ee"
      ],
      "author": {
        "name": "Orion Hodson",
        "email": "oth@google.com",
        "time": "Fri May 18 08:33:20 2018 +0100"
      },
      "committer": {
        "name": "Orion Hodson",
        "email": "oth@google.com",
        "time": "Mon Jun 11 10:57:17 2018 +0100"
      },
      "message": "ART: Adds an entrypoint for invoke-custom\n\nAdd support for the compiler to call into the runtime for\ninvoke-custom bytecodes.\n\nBug: 35337872\nTest: art/test.py --host -r -t 952\nTest: art/test.py --target --64 -r -t 952\nTest: art/test.py --target --32 -r -t 952\nChange-Id: I821432e7e5248c91b8e1d36c3112974c34171803\n"
    },
    {
      "commit": "dbaa5c7ba8935cf87ceb40a4054f9842929e9a51",
      "tree": "5037625c80cb97a0e13026dc450db28e59ff72ca",
      "parents": [
        "51dda39549033b3c50a7fce5522ffc81325db54b"
      ],
      "author": {
        "name": "Orion Hodson",
        "email": "oth@google.com",
        "time": "Thu May 10 08:22:46 2018 +0100"
      },
      "committer": {
        "name": "Orion Hodson",
        "email": "oth@google.com",
        "time": "Fri May 11 11:55:30 2018 +0100"
      },
      "message": "ART: Compiler support for const-method-handle\n\nImplemented as a runtime call.\n\nBug: 66890674\nTest: art/test.py --target -r -t 979\nTest: art/test.py --target --64 -r -t 979\nTest: art/test.py --host -r -t 979\nChange-Id: I67f461c819a7d528d7455afda8b4a59e9aed381c\n"
    },
    {
      "commit": "18259d7fb7164a5e029df4f883b3a79ccc2403e8",
      "tree": "ba378bfdef4127bb0607215186e3b150fd38bcdf",
      "parents": [
        "922501b4bbf724e4259477a27764291684eedffb"
      ],
      "author": {
        "name": "Orion Hodson",
        "email": "oth@google.com",
        "time": "Thu Apr 12 11:18:23 2018 +0100"
      },
      "committer": {
        "name": "Orion Hodson",
        "email": "oth@google.com",
        "time": "Thu May 10 15:04:09 2018 +0100"
      },
      "message": "ART: Compiler support for const-method-type\n\nImplemented as a runtime call.\n\nBug: 66890674\nTest: art/test.py --target -r -t 979\nTest: art/test.py --target --64 -r -t 979\nTest: art/test.py --host -r -t 979\nChange-Id: I4b3d3969d455d0198cfe122eea8abd54e0ea20ee\n"
    },
    {
      "commit": "4d17987da58d9411adbed1a18203d76d6119612d",
      "tree": "f2953a0eb3ebc3f8533d22c14f4a09d7f0d4168d",
      "parents": [
        "e57043081e6b091a9fd23a84043373148ae72f1f"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Jan 19 14:50:10 2018 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Jan 22 18:35:16 2018 +0000"
      },
      "message": "ART: Add entrypoint and intrinsic for Math.pow().\n\nMathBenchmarks.java#timePow results on taimen\u0027s little cores\nfixed at frequency 1401600 with forced JIT compilation:\n  - before:\n    - X32: 356.33 (@FastNative), 315.39 (@CriticalNative)\n    - X64: 357.31 (@FastNative), 315.37 (@CriticalNative)\n  - after (LICM defeats the benchmark):\n    - X32: 2.88\n    - X64: 2.87\n  - after but with kAllSideEffects to prevent LICM:\n    - X32: 275.42\n    - X64: 275.67\n\nTest: Rely on TreeHugger.\nBug: 70727450\nChange-Id: Iaa31f70acabbd57c163cfeafe02eed67c1348861\n"
    },
    {
      "commit": "c043d006845afef99b17aeab8bb6d6da1a42ad37",
      "tree": "756ce3caca2a7ff62a169c003639657bd7124d2f",
      "parents": [
        "9983e302384c12a975c8d2d5ae239f79fd8e1996"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Fri Jul 14 16:39:16 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Jul 17 18:00:40 2017 +0100"
      },
      "message": "Remove the old ARM assemblers from ART.\n\nNow that the old ARM code generator for ART\u0027s Optimizing\ncompiler is gone, these assemblers no longer have users;\nretiring them.\n\nTest: test.py\nBug: 63316036\nChange-Id: Iaea42432a9e0d3288b71615f85c58846c0336944\n"
    },
    {
      "commit": "6d729a789d3d7771e13d9445ee0be1d9d48a81b5",
      "tree": "360b9af68920f411be5fe6753aaf7ab4976385ea",
      "parents": [
        "8cfbbb826a3ab7bb680cfcd8a8148570b165d620"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Fri Jun 30 18:34:01 2017 +0100"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Thu Jul 13 16:41:07 2017 +0100"
      },
      "message": "Introduce a Marking Register in ARM code generation.\n\nWhen generating code for ARM, maintain the status of\nThread::Current()-\u003eGetIsGcMarking() in register R8,\ndubbed MR (Marking Register), and check the value of that\nregister (instead of loading and checking a read barrier\nmarking entrypoint) in read barriers.\n\nTest: m test-art-target\nTest: m test-art-target with tree built with ART_USE_READ_BARRIER\u003dfalse\nTest: m test-art-host-gtest\nTest: ARM device boot test\nBug: 37707231\nChange-Id: I30b44254460d0bbb9f1b2adc65eca52ca3de3f53\n"
    },
    {
      "commit": "365719c23d809e595cf320bfba40e76bb4e87940",
      "tree": "0939f0d8dc47723978a665fa11dd637f6976d521",
      "parents": [
        "d6705a0586377f1b0d7d14d3abe2b270bb0adb18"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Mar 08 13:11:50 2017 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Tue May 16 01:58:03 2017 +0100"
      },
      "message": "No need to lock when calling Thread.interrupted.\n\nAlso intrinsify the Thread.interrupted call.\n\nThe rationale behind this optimization is that the flag can only\nhave two values, and only self can set it to false.\n\nTest: libcore, jdwp, run-tests, 050-sync-test\nChange-Id: I5c2b43bf872ba0bfafcb54b2cfcd19181864bc4c\n"
    },
    {
      "commit": "28a24b308f665de64c785e2590f9b23ec6ec25aa",
      "tree": "3e9f0779038cefbbae5581b5844ce742ea782f9b",
      "parents": [
        "6bc7774426cc0b6bbab5566fa62b3c509455e583"
      ],
      "author": {
        "name": "Mathieu Chartier",
        "email": "mathieuc@google.com",
        "time": "Wed Apr 19 23:54:33 2017 -0700"
      },
      "committer": {
        "name": "Mathieu Chartier",
        "email": "mathieuc@google.com",
        "time": "Wed Apr 19 23:55:36 2017 -0700"
      },
      "message": "Fix some gtests\n\nForgot to retest.\n\nTest: test-art-host-gtest\n\nChange-Id: I72b07c3872079452a3a01db4fbd2c4ee0060f294\n"
    },
    {
      "commit": "b048cb74b742b03eb6dd5f1d6dd49e559f730b36",
      "tree": "b1f663cbb343488a548cce4db352dbc4af720a89",
      "parents": [
        "f34077c96af3389e8eae65252d4c5d51cf630039"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Jan 23 22:50:24 2017 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jan 26 09:56:36 2017 +0000"
      },
      "message": "Add per array size allocation entrypoints.\n\n- Update architectures that have fast paths for\n  array allocation to use it.\n- Will add more fast paths in follow-up CLs.\n\nTest: test-art-target test-art-host.\nChange-Id: I138cccd16464a85de22a8ed31c915f876e78fb04\n"
    },
    {
      "commit": "8d91ac31ccb92557e434d89ffade3372466e1af5",
      "tree": "37fd364ba6c9a6cf5e6a60a00c2542c5ffb12528",
      "parents": [
        "2f670ccba022fe557c637571ac781519f0e84463"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 18 18:07:15 2017 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jan 19 11:56:43 2017 +0000"
      },
      "message": "Remove unused array entrypoints.\n\nTest: test-art-host test-art-target\nChange-Id: I910d1c912c7c9056ecea0e1e7da7afb2a7220dfa\n"
    },
    {
      "commit": "39cee66a8ddf0254626c9591662cf87e4a1cedc4",
      "tree": "be25df71e51ce03a8847c23934322b8f282a291b",
      "parents": [
        "a3974581751cd73a896f7c4fcab71beb17c4f9dc"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jan 13 16:04:53 2017 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 18 11:12:33 2017 +0000"
      },
      "message": "Entrypoints cleanup.\n\nRemove unused ones to facilitate the transition to compressed\ndex caches.\n\ntest: test-art-host, test-art-target\nChange-Id: I1d1cb0daffa86dd9dda2eaa3c1ea3650a5c8d9d0\n"
    },
    {
      "commit": "e71b35446985835363a4508646cf7b1121bd95a3",
      "tree": "bd40763b04ba2028f3383736b2a14808e407120c",
      "parents": [
        "8bd59a0fd46db83616785168231e09fb95ed2ead"
      ],
      "author": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Mon Jan 16 14:58:23 2017 +0000"
      },
      "committer": {
        "name": "Roland Levillain",
        "email": "rpl@google.com",
        "time": "Tue Jan 17 11:55:07 2017 +0000"
      },
      "message": "Move some fields in art::Thread to reduce maintenance burden.\n\nMove fields `thread_local_start`, `thread_local_pos`,\n`thread_local_end` and `thread_local_objects` before fields\n`jni_entrypoints` and `quick_entrypoints` within\nart::Thread, to avoid repetitive art::Thread field moves in\nfuture CLs caused by the addition or deletion of entry\npoints.\n\nTest: m test-art-host\ntest: m test-art-target (on ARM)\nChange-Id: Ib67842e44a7f21a871ca4d1bb95dc6f7cfedc829\n"
    },
    {
      "commit": "ac141397dc29189ad2b2df41f8d4312246beec60",
      "tree": "a2f481463a14695bf9327fd2f549878ecf30c77b",
      "parents": [
        "5c9f90c5ecf2ff6f93ada0f7b18b46d866c59ea1"
      ],
      "author": {
        "name": "Orion Hodson",
        "email": "oth@google.com",
        "time": "Fri Jan 13 11:53:47 2017 +0000"
      },
      "committer": {
        "name": "Orion Hodson",
        "email": "oth@google.com",
        "time": "Sun Jan 15 15:18:07 2017 +0000"
      },
      "message": "Revert \"Revert \"ART: Compiler support for invoke-polymorphic.\"\"\n\nThis reverts commit 0fb5af1c8287b1ec85c55c306a1c43820c38a337.\n\nThis takes us back to the original change and attempts to fix the\nissues encountered:\n\n- Adds transition record push/pop around artInvokePolymorphic.\n- Changes X86/X64 relocations for MacSDK.\n- Implements MIPS entrypoint for art_quick_invoke_polymorphic.\n- Corrects size of returned reference in art_quick_invoke_polymorphic\n  on ARM.\n\nBug: 30550796,33191393\nTest: art/test/run-test 953\nTest: m test-art-run-test\n\nChange-Id: Ib6b93e00b37b9d4ab743a3470ab3d77fe857cda8\n"
    },
    {
      "commit": "0d3998b5ff619364acf47bec0b541e7a49bd6fe7",
      "tree": "a4763c0660372f6311b612c09267cbbc2fe71e89",
      "parents": [
        "aa89a4c6fca095904521842c018399f1e3501a45"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jan 12 15:35:12 2017 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu Jan 12 16:51:12 2017 +0000"
      },
      "message": "Revert \"Revert \"Make object allocation entrypoints only take a class.\"\"\n\nThis reverts commit f7aaacd97881c6924b8212c7f8fe4a4c8721ef53.\n\nChange-Id: I6756cd1e6110bb45231f62f5e388f16c044cb145\n"
    },
    {
      "commit": "f7aaacd97881c6924b8212c7f8fe4a4c8721ef53",
      "tree": "780209ac8e992fa63307062977f672aa5bb55d9e",
      "parents": [
        "2b615ba29c4dfcf54aaf44955f2eac60f5080b2e"
      ],
      "author": {
        "name": "Hiroshi Yamauchi",
        "email": "yamauchi@google.com",
        "time": "Thu Jan 12 02:58:38 2017 +0000"
      },
      "committer": {
        "name": "Hiroshi Yamauchi",
        "email": "yamauchi@google.com",
        "time": "Thu Jan 12 02:58:38 2017 +0000"
      },
      "message": "Revert \"Make object allocation entrypoints only take a class.\"\n\n960-default-smali64 is failing.\n\nThis reverts commit 2b615ba29c4dfcf54aaf44955f2eac60f5080b2e.\n\nChange-Id: Iebb8ee5a917fa84c5f01660ce432798524d078ef\n"
    },
    {
      "commit": "2b615ba29c4dfcf54aaf44955f2eac60f5080b2e",
      "tree": "0a2fe5f9243645a054d4aa094bff5a69cc1abb88",
      "parents": [
        "c9a060f2688599d4a402ee6234db46c2e9b7463f"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jan 06 14:40:07 2017 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jan 11 10:34:10 2017 +0000"
      },
      "message": "Make object allocation entrypoints only take a class.\n\nChange motivated by:\n- Dex cache compression: having the allocation fast path do a\n  dex cache lookup will be too expensive. So instead, rely on the\n  compiler having direct access to the class (either through BSS for\n  AOT, or JIT tables for JIT).\n- Inlining: the entrypoints relied on the caller of the allocation to\n  have the same dex cache as the outer method (stored at the bottom of\n  the stack). This meant we could not inline methods from a different\n  dex file that do allocations. By avoiding the dex cache lookup in\n  the entrypoint, we can now remove this restriction.\n\nCode expansion on average for Docs/Gms/FB/Framework (go/lem numbers):\n- Around 0.8% on arm64\n- Around 1% for x64, arm\n- Around 1.5% on x86\n\nTest: test-art-host, test-art-target, ART_USE_READ_BARRIER\u003dtrue/false\nTest: test-art-host, test-art-target,  ART_DEFAULT_GC_TYPE\u003dSS ART_USE_TLAB\u003dtrue\n\nChange-Id: I41f3748bb4d251996aaf6a90fae4c50176f9295f\n"
    },
    {
      "commit": "f2665fa6e5ca54c7d4f084ec1fab9a20e96aea75",
      "tree": "2de4c1166f3686b3e1b15c76b14082847985dff6",
      "parents": [
        "294e107e8947224ea6540af5068bce2492ee8d5b"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Wed Dec 21 18:42:21 2016 +0000"
      },
      "committer": {
        "name": "Scott Wakeling",
        "email": "scott.wakeling@linaro.org",
        "time": "Thu Dec 22 14:58:46 2016 +0000"
      },
      "message": "ART: VIXL32: Fix assembler test after VIXL update.\n\nVeneer pool is emitted 4 bytes later, so the expected output for\nthe test has been adjusted.\n\nTest: test-art-host\nTest: test-art-target\nChange-Id: I3d656224fd4151904b8096486adecb6ef1eafea6\n"
    },
    {
      "commit": "8f840f805579896809f6a17705402a85793ebce9",
      "tree": "82426258ac64a453b869896f0ced39b038d9e1f8",
      "parents": [
        "b73e659be3fb6474ff3a993cd25ecbfa1cc4715c"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Thu Dec 15 17:56:27 2016 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Dec 19 09:31:04 2016 +0000"
      },
      "message": "ARM: Fix vixl related branch issue in JNI.\n\nFix VIXL asserts in EncodeLabelFor in JNI macro assembler when\nlabel is out of range of 16-bit branch (now a veneer is correctly\nused).\n\nbug:32545704\n\nTest: ART_USE_VIXL_ARM_BACKEND\u003dtrue m test-art-host\nTest: ART_USE_VIXL_ARM_BACKEND\u003dtrue m test-art-target\nChange-Id: Ie6401394cf364daeaaf107b42275997d2edf5b6d\n"
    },
    {
      "commit": "af1e2990cd1406a0fb7cba1d2e208208e950e413",
      "tree": "07e80e4dcc31931003a87be7884134ea42ceec07",
      "parents": [
        "3f699ae23266b2c4adc98958dcbd80c71c2c3284"
      ],
      "author": {
        "name": "Igor Murashkin",
        "email": "iam@google.com",
        "time": "Wed Oct 12 17:44:50 2016 -0700"
      },
      "committer": {
        "name": "Igor Murashkin",
        "email": "iam@google.com",
        "time": "Wed Oct 19 11:38:54 2016 -0700"
      },
      "message": "jni: Support @FastNative methods that return objects\n\nBug: 32088975\nChange-Id: I16f8b7ec6b251812af60ab25f2153d9b72f37044\n"
    },
    {
      "commit": "aad75c6d5bfab2dc8e30fc99fafe8cd2dc8b74d8",
      "tree": "c1b9e1eabcf35c5cbb5b4f46313a4e062f2d5d51",
      "parents": [
        "82d4838d6bb3480cd25327cedc5179fb2d86881c"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Oct 03 08:46:48 2016 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Oct 04 17:51:46 2016 +0100"
      },
      "message": "Revert \"Revert \"Store resolved Strings for AOT code in .bss.\"\"\n\nFixed oat_test to keep dex files alive. Fixed mips build.\nRewritten the .bss GC root visiting and added write barrier\nto the artResolveStringFromCode().\n\nTest: build aosp_mips-eng\nTest: m ART_DEFAULT_GC_TYPE\u003dSS test-art-target-host-gtest-oat_test\nTest: Run ART test suite on host and Nexus 9.\nBug: 20323084\nBug: 30627598\n\nThis reverts commit 5f926055cb88089d8ca27243f35a9dfd89d981f0.\n\nChange-Id: I07fa2278d82b8eb64964c9a4b66cb93726ccda6b\n"
    },
    {
      "commit": "5f926055cb88089d8ca27243f35a9dfd89d981f0",
      "tree": "8d87d400e36301eb648e19bcd225f13c469648ad",
      "parents": [
        "9e5739aaa690a8529c104f4c05035a657616c310"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Sep 30 17:04:49 2016 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Sep 30 18:08:09 2016 +0100"
      },
      "message": "Revert \"Store resolved Strings for AOT code in .bss.\"\n\nThere are some issues with oat_test64 on host and aosp_mips-eng.\n\nAlso reverts \"compiler_driver: Fix build.\"\n\nBug: 20323084\nBug: 30627598\n\nThis reverts commit 63dccbbefef3014c99c22748d18befcc7bcb3b41.\nThis reverts commit 04a44135ace10123f059373691594ae0f270a8a4.\n\nChange-Id: I568ba3e58cf103987fdd63c8a21521010a9f27c4\n"
    },
    {
      "commit": "63dccbbefef3014c99c22748d18befcc7bcb3b41",
      "tree": "60a498041bebff43bc1f43d438e3bc34a30887f7",
      "parents": [
        "6bee25976782a063d6b44f7718a6302761bf6403"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Sep 21 13:51:10 2016 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Sep 29 15:58:43 2016 +0100"
      },
      "message": "Store resolved Strings for AOT code in .bss.\n\nAnd do some related refactorings.\n\nBug: 20323084\nBug: 30627598\nTest: Run ART test suite including gcstress on host and Nexus 9.\nTest: Run ART test suite including gcstress with baker CC on host and Nexus 9.\nTest: Build aosp_mips64-eng.\nChange-Id: I1b12c1570fee8e5da490b47f231050142afcbd1e\n"
    },
    {
      "commit": "12e097c84cef710fa4f254b1811ff70b876e9e9a",
      "tree": "d8044470b0006a5ff22207ae589a8b05829dfdfa",
      "parents": [
        "ba6b679bd34449ec56508966706ca1b8d5e7cb17"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Mon Aug 08 15:13:26 2016 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Fri Aug 19 15:52:58 2016 +0100"
      },
      "message": "ARM: VIXL32: Implement VIXL-based assembler.\n\nThis patch introduces new ARM assembler (Thumb2) based on VIXL and\nARM VIXL JNI Macro Assembler. Both are turned off by default (JNI\none will be turned on in the following patch).\n\nChange-Id: I5f7eb35da5318d7170b3c7e8553364ebe29cc991\n"
    },
    {
      "commit": "ac6ac10a0801fa6eb95e0ab0c72b2ed562210b34",
      "tree": "3758a1903dbdd273c35d4bae4ee0e820857946c0",
      "parents": [
        "1201804d1813d7db0accead9721d67c40b3de564"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Dec 17 12:14:00 2015 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Dec 22 11:51:33 2015 +0000"
      },
      "message": "Optimizing/ARM: Fix CmpConstant().\n\nCMN updates flags based on addition of its operands.\nDo not confuse the \"N\" suffix with bitwise inversion\nperformed by MVN.\n\nAlso add more special cases analogous to AddConstant()\nand use CmpConstant() more in code generator.\n\nChange-Id: I0d4571770a3f0fdf162e97d4bde56814098e7246\n"
    },
    {
      "commit": "f5c09c3ed5bca4c34d8476dd9ed2714106fafbcf",
      "tree": "6521df348c2fd8d692bb751ed8dffdf70c8f6051",
      "parents": [
        "7f3b38cc23b638ab84ac01a94e90f0456da3b688"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Dec 17 12:08:08 2015 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Dec 17 15:13:39 2015 +0000"
      },
      "message": "Optimizing/ARM: Fix AddConstant() to adhere to set_cc.\n\nAnd improve it to use shorter code sequences.\n\nBug: 26121945\n\nChange-Id: Ia4f1688652c195a7ca19af36d919388a550e2841\n"
    },
    {
      "commit": "b4536b7de576b20c74c612406c5d3132998075ef",
      "tree": "5265c07b51b4d79b2fd64c63d9b78d38b7601a8f",
      "parents": [
        "883ef45b5d5a2e4005914c7b339881900976b6e7"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Nov 24 13:45:23 2015 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Dec 01 11:38:03 2015 +0000"
      },
      "message": "Optimizing/ARM: Implement kDexCachePcRelative dispatch.\n\nChange-Id: I0fe2da50a30a3f62bec8ea01688dd1fec84b1831\n"
    },
    {
      "commit": "f180af0fc0d0bd981dd6356848df2ba237e1a227",
      "tree": "bea248023c5823bbb28a1864655e3afce9226400",
      "parents": [
        "97cd5bb34ca97e7e87a030b2e1acec004fd26275",
        "f9d741e32c6f1629ce70eefc68d3363fa1cfd696"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Nov 23 11:20:35 2015 +0000"
      },
      "committer": {
        "name": "Gerrit Code Review",
        "email": "noreply-gerritcodereview@google.com",
        "time": "Mon Nov 23 11:20:35 2015 +0000"
      },
      "message": "Merge \"Optimizing/ARM: Improve long shifts by 1.\""
    },
    {
      "commit": "f9d741e32c6f1629ce70eefc68d3363fa1cfd696",
      "tree": "409005e5b1d01d2830c20421f8466125e110d6af",
      "parents": [
        "beb709a2607a00b5df33f0235f22ccdd876cee22"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Nov 20 15:08:11 2015 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Nov 20 16:18:39 2015 +0000"
      },
      "message": "Optimizing/ARM: Improve long shifts by 1.\n\nImplement long\n    Shl(x,1) as LSLS+ADC,\n    Shr(x,1) as ASR+RRX and\n    UShr(x,1) as LSR+RRX.\n\nRemove the simplification substituting Shl(x,1) with\nADD(x,x) as it interferes with some other optimizations\ninstead of helping them. And since it didn\u0027t help 64-bit\narchitectures anyway, codegen is the correct place for it.\nThis is now implemented for ARM and x86, so only mips32 can\nbe improved.\n\nChange-Id: Idd14f23292198b2260189e1497ca5411b21743b3\n"
    },
    {
      "commit": "6fd0ffe8da212723a3ac0256ce350b5872cc61d4",
      "tree": "122c89d874460662d3feba523cb9f2553fb78bd3",
      "parents": [
        "beb709a2607a00b5df33f0235f22ccdd876cee22"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Nov 19 21:13:52 2015 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri Nov 20 11:55:49 2015 +0000"
      },
      "message": "Optimizing/Thumb2: Improve load/store for large offsets.\n\nThis reduces the boot.oat size on Nexus 5 by 568KiB (0.8%).\n\nAlso change 32-bit ADD/SUB immediate to use the recommended\nencoding T3 when both T3 and T4 are available.\n\nChange-Id: I174382bda2b22da70560b947f5536acf8c1814a9\n"
    },
    {
      "commit": "d2b4ca2d02c86b1ce1826fd2b35ce6c9c58c1ff1",
      "tree": "dab4cdfacd3e7cb529f3b0de931c8a173039571f",
      "parents": [
        "fb11bab9bc96ff05dcb12f43abf58df256b7c7aa"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Sep 14 15:13:26 2015 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Oct 14 12:20:59 2015 +0100"
      },
      "message": "Improve Thumb2 bitwise operations.\n\nAllow embedding constants in AND, ORR, EOR. Add ORN to\nassembler, use BIC and ORN for AND and ORR when needed.\n\nChange-Id: I24d69ecc7ce6992b9c5eb7a313ff47a942de9661\n"
    },
    {
      "commit": "73cf0fb75de2a449ce4fe329b5f1fb42eef1372f",
      "tree": "d5b0957414c355254babfcd1a797ce87a0eb85a2",
      "parents": [
        "9ee5d6cdc14ac94b64ea1961bf221bad48746929"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Jul 30 15:07:22 2015 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Sep 01 10:10:37 2015 +0100"
      },
      "message": "ART: Add 16-bit Thumb2 ROR, NEGS and CMP for high registers.\n\nAlso clean up the usage of set_cc flag. Define a SetCc\nenumeration that specifies whether to set or keep condition\ncodes or whether we don\u0027t care and a 16-bit instruction\nshould be selected if one exists.\n\nThis reduces the size of Nexus 5 boot.oat by 44KiB (when\ncompiled with Optimizing which is not the default yet).\n\nChange-Id: I047072dc197ea678bf2019c01bcb28943fa9b604\n"
    },
    {
      "commit": "cf93a5cd9c978f59113d42f9f642fab5e2cc8877",
      "tree": "55162627fcbf2cb7913a735c7ed89e8e4b5e84d7",
      "parents": [
        "db40ea768bd914125c3754dacb9b6f534a2e2399"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Jun 16 11:33:24 2015 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Jun 17 09:43:51 2015 +0100"
      },
      "message": "Revert \"Revert \"ART: Implement literal pool for arm, fix branch fixup.\"\"\n\nThis reverts commit fbeb4aede0ddc5b1e6a5a3a40cc6266fe8518c98.\n\nAdjust block label positions. Bad catch block labels were the\nreason for the revert.\n\nChange-Id: Ia6950d639d46b9da6b07f3ade63ab46d03d63310\n"
    },
    {
      "commit": "fbeb4aede0ddc5b1e6a5a3a40cc6266fe8518c98",
      "tree": "76ab28cf259def4dccec529df217fd760f27d2aa",
      "parents": [
        "f38caa68cce551fb153dff37d01db518e58ed00f"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Jun 16 11:32:01 2015 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Jun 16 11:32:01 2015 +0000"
      },
      "message": "Revert \"ART: Implement literal pool for arm, fix branch fixup.\"\n\nThis reverts commit f38caa68cce551fb153dff37d01db518e58ed00f.\n\nChange-Id: Id88b82cc949d288cfcdb3c401b96f884b777fc40\nReason: broke the tests.\n"
    },
    {
      "commit": "f38caa68cce551fb153dff37d01db518e58ed00f",
      "tree": "723612f20666f429b7c67321f0353d57425b1c63",
      "parents": [
        "bd8c725e465cc7f44062745a6f2b73248f5159ed"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Fri May 29 15:50:18 2015 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Jun 15 15:13:28 2015 +0100"
      },
      "message": "ART: Implement literal pool for arm, fix branch fixup.\n\nChange-Id: Iecc91418bb4ee1c957f42fefb737d0ee2ba960e7\n"
    },
    {
      "commit": "d56376cce54e7df976780ecbd03228f60d276433",
      "tree": "5a523ff4a1589a4462207f4c75fad921870a62a2",
      "parents": [
        "aa49c23d47e5fdfcf51380550ee864e9d30d082b"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Thu May 21 12:32:34 2015 +0000"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri May 22 15:06:45 2015 +0100"
      },
      "message": "Revert \"Revert \"Introduce a NearLabel in thumb2.\"\"\n\nThis reverts commit 1f277e3cef6c33cd35e91123978491d83338d2ad.\n\n- Fix CompareAndBranch to not use cbz/cbnz with high registers.\n- Add a test for CompareAndBranch with the *inc file, as the\n  other assembler test infrastructure does not handle labels.\n\nChange-Id: If552bf1112b96caa3b9bb6c73c4b40bb90a33db7\n"
    },
    {
      "commit": "5bc561c31d119a964e54cf73b475f8eac044d905",
      "tree": "d8a7ad92f49cf2af6e5569ae2da99b709be612a9",
      "parents": [
        "7587082c370ef1a90797baf2371ee8e472b2adb8"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue Dec 16 17:41:59 2014 +0000"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Dec 18 14:03:05 2014 +0000"
      },
      "message": "Fix Thumb2 assembler to emit 16-bit add/sub SP, #imm.\n\nAlso allow 16-bit add rN, SP, #imm.\n\nChange-Id: I50100ad0b0e19a1c855a2319615e86d7a2b66a69\n"
    },
    {
      "commit": "3c7bb98698f77af10372cf31824d3bb115d9bf0f",
      "tree": "1cd4cc18babfbb16ab908f23929fa88d7678f06b",
      "parents": [
        "98cc1e552c2ccbe5d51bc81d49e79119280f5416"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Wed Jul 23 16:04:16 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Jul 28 15:44:28 2014 +0100"
      },
      "message": "Implement array get and array put in optimizing.\n\nAlso fix a couple of assembler/disassembler issues.\n\nChange-Id: I705c8572988c1a9c4df3172b304678529636d5f6\n"
    },
    {
      "commit": "96f89a290eb67d7bf4b1636798fa28df14309cc7",
      "tree": "ca2b484a18107f8253aa7774cde304586a31bc60",
      "parents": [
        "4436e926aa8e64ac7e4c4afb81f2a59b2477045a"
      ],
      "author": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Fri Jul 11 10:57:49 2014 +0100"
      },
      "committer": {
        "name": "Nicolas Geoffray",
        "email": "ngeoffray@google.com",
        "time": "Mon Jul 21 09:54:20 2014 +0100"
      },
      "message": "Add assembly operations with constants in optimizing compiler.\n\nChange-Id: I5bcc35ab50d4457186effef5592a75d7f4e5b65f\n"
    },
    {
      "commit": "0bb9ade51635559f991259a7ac90d8570ad886aa",
      "tree": "b8fc0e1a304eeefac2b7d8f46c8ff8aee5b0435e",
      "parents": [
        "fee5586dac3bf22a31dbbffe7b4ca7e978e53185"
      ],
      "author": {
        "name": "Dave Allison",
        "email": "dallison@google.com",
        "time": "Thu Jun 26 17:57:36 2014 -0700"
      },
      "committer": {
        "name": "Dave Allison",
        "email": "dallison@google.com",
        "time": "Thu Jun 26 18:14:50 2014 -0700"
      },
      "message": "Fix off-by-one errors in limit checking for ldr/str instructions.\n\nThe LDR/STR encoder in the thumb assembler had an off-by-one\nerror for limit checking for immediates.  This resulted in an\nassertion failure for things like \u0027ldr rx,[ry,#128]\u0027\n\nBug: 15876206\n\nChange-Id: Ic866212e2feae94e0bd4c753724898d84f5cb944\n"
    },
    {
      "commit": "45fdb93f04b981f70f7b6d98949ab3986b7331f8",
      "tree": "8233265f998fdd9d4de38acb5ed56a663b10c26e",
      "parents": [
        "1528b02c4d5241e785bb680f13de70c355e67429"
      ],
      "author": {
        "name": "Dave Allison",
        "email": "dallison@google.com",
        "time": "Wed Jun 25 12:37:10 2014 -0700"
      },
      "committer": {
        "name": "Dave Allison",
        "email": "dallison@google.com",
        "time": "Thu Jun 26 10:46:19 2014 -0700"
      },
      "message": "Support additional instructions in ARM and thumb assemblers\n\nThis adds the following support for the ARM and thumb assemblers:\n\n1. Shifting by a register.\n2. LDR/STR with a register offset, possibly shifted.\n3. LDR(literal).\n4. STR PC relative.\n\nAlso adds tests for them in the thumb assembler gtest.\n\nChange-Id: Ie467e3c1d06b699cacbdef3482ed9a92e4f1809b\n"
    },
    {
      "commit": "65fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7",
      "tree": "fc0ce77d446477be37f0ec8c86d67df4941cac9b",
      "parents": [
        "e3b5cb502371aff7e7b7291facfc27b092e7803e"
      ],
      "author": {
        "name": "Dave Allison",
        "email": "dallison@google.com",
        "time": "Mon Apr 28 13:45:27 2014 -0700"
      },
      "committer": {
        "name": "Dave Allison",
        "email": "dallison@google.com",
        "time": "Thu Jun 05 12:45:20 2014 -0700"
      },
      "message": "Thumb2 assembler for JNI compiler and optimizing compiler\n\nThis provides a programmatic assembler for the thumb2 instruction set for\nARM.  The interface is the same as the ARM assembler and the ARM assembler has\nbeen moved into Arm32Assembler.  The assembler handles most 16 and 32 bit instructions\nand also allows relocations due to branch expansion.  It will also rewrite cbz/cbnz\ninstructions if they go out of range.\n\nIt also changes the JNI compiler to use the thumb2 assembler as opposed\nto forcing it to use ARM32.  The trampoline compiler still uses ARM due to the\nway it returns the address of its generated code.  A trampoline in thumb2 is the\nsame size as that in ARM anyway (8 bytes).\n\nProvides gtest for testing the thumb2 instruction output.  This gtest only runs\non the host as it uses arm-eabi-objdump to disassemble the generated code.  On the\ntarget the output is not checked but the assembler will still be run to perform\nall its checks.\n\nChange-Id: Icd9742b6f13541bec5b23097896727392e3a6fb6\n"
    }
  ]
}