)]}'
{
  "log": [
    {
      "commit": "bd78567cef305e35481734b7fc24f68ded031439",
      "tree": "e3873b73e3631c5cd70c1a3f8f38e79dad25d890",
      "parents": [
        "9926e4615d75cb6c9371e1766a14b0a80089ae18"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu May 03 17:09:09 2018 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Tue May 08 11:36:11 2018 +0100"
      },
      "message": "Store HIR type in HInstruction::packed_field_.\n\nThis is similar to\n    https://android-review.googlesource.com/609566\nthough the performance impact has not been measured.\nHowever, avoiding a virtual call reduces pressure on the\nbranch predictor and provides better optimization\nopportunities for the C++ compiler.\n\nAs there is now no difference between HTemplateInstruction\u003c\u003e\nand HExpression\u003c\u003e (the type is stored in HInstruction), we\nremove the former and use HExpression\u003c\u003e for all instructions\nthat have a fixed number of inputs.\n\nTest: Rely on TreeHugger.\nChange-Id: Ib3fd111048b0ac38ee65386a7e5af70c5ccc98de\n"
    },
    {
      "commit": "d9e4d73b20d68aa387f5837e1535b6fc26b2859a",
      "tree": "b55a96e66f2db1482571788b33c6d3055cb47396",
      "parents": [
        "8dbb4ba7ffdf42cf08c55b117370efc0ec5357e8"
      ],
      "author": {
        "name": "Gupta Kumar, Sanjiv",
        "email": "sanjiv.kumar.gupta@intel.com",
        "time": "Mon Feb 05 13:35:03 2018 +0530"
      },
      "committer": {
        "name": "Gupta Kumar, Sanjiv",
        "email": "sanjiv.kumar.gupta@intel.com",
        "time": "Wed Feb 21 14:56:13 2018 +0530"
      },
      "message": "Fix iCache misses for GetKind on x86,x86_64\n\nGetKind() takes about 2.6% of total compilation time on x86_64.\nThe primary reason is that the target call GetKindInternal() is often\nbeyond the page boundary causing frequent i-cache misses.\nThis patch removes the virtual call to GetKindInternal () and instead\nkeeps the InstructionKind into each constructed instruction.\nSince we have about 121 instructions in total as of now,\nit takes about 7 extra bits in each instruction.\ndex2oat runs about 12% faster with --compiler-filter\u003deverything on an\nAPK of 25MB.\n\nTest: Tested the patch by running host art tests.\n\nRebased.\n\nChange-Id: Ia7bbcd67180151e4565507164a718acbb6284885\nSigned-off-by: Gupta Kumar, Sanjiv \u003csanjiv.kumar.gupta@intel.com\u003e\n"
    },
    {
      "commit": "cced8ba4245a061ab047a0a6882468d75d619dd9",
      "tree": "b379abfa48689c108e1cacedd2b13d4b5394baf2",
      "parents": [
        "96c76457d5c5af2d4243c78d74ada77de3223d88"
      ],
      "author": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Wed Jul 19 18:18:09 2017 +0100"
      },
      "committer": {
        "name": "Artem Serov",
        "email": "artem.serov@linaro.org",
        "time": "Tue Nov 07 12:56:17 2017 +0000"
      },
      "message": "ART: Introduce individual HInstruction cloning.\n\nIntroduce API for HInstruction cloning, support it for a few\ninstructions. add a gtest.\n\nTest: cloner_test.cc, test-art-target, test-art-host.\n\nChange-Id: I8b6299be5d04a26390d9ef13a20ce82ee5ae4afe\n"
    },
    {
      "commit": "a290160f74ee53c0ffb51c7b3ac916d239c9556a",
      "tree": "0bfc9728ccee68dbd359b023319423f703448aac",
      "parents": [
        "86d244ec33f333b32301a9ee09088300c8544a7b"
      ],
      "author": {
        "name": "Lena Djokic",
        "email": "Lena.Djokic@imgtec.com",
        "time": "Thu Sep 21 13:50:52 2017 +0200"
      },
      "committer": {
        "name": "Lena Djokic",
        "email": "Lena.Djokic@imgtec.com",
        "time": "Thu Oct 05 11:43:34 2017 +0200"
      },
      "message": "MIPS32R2: Share address computation\n\nFor array accesses the element address has the following structure:\nAddress \u003d CONST_OFFSET + base_addr + index \u003c\u003c ELEM_SHIFT\n\nThe address part (index \u003c\u003c ELEM_SHIFT) can be shared across array\naccesses with the same data type and index.\n\nFor example, in the following loop 5 accesses can share address\ncomputation:\n\nvoid foo(int[] a, int[] b, int[] c) {\n  for (i...) {\n    a[i] \u003d a[i] + 5;\n    b[i] \u003d b[i] + c[i];\n  }\n}\n\nTest: test-art-host, test-art-target\nChange-Id: Id09fa782934aad4ee47669275e7e1a4d7d23b0fa\n"
    },
    {
      "commit": "0ebe0d83138bba1996e9c8007969b5381d972b32",
      "tree": "a5ee66ebc5b587ade97e56ac8fc7d832fbbed4af",
      "parents": [
        "e1e347dace0ded83774999bb26c37527dcdb1d5a"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Thu Sep 21 22:50:39 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon Sep 25 15:45:01 2017 +0100"
      },
      "message": "ART: Introduce compiler data type.\n\nReplace most uses of the runtime\u0027s Primitive in compiler\nwith a new class DataType. This prepares for introducing\nnew types, such as Uint8, that the runtime does not need\nto know about.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nBug: 23964345\nChange-Id: Iec2ad82454eec678fffcd8279a9746b90feb9b0c\n"
    },
    {
      "commit": "0eb882bfc5d260e8014c26adfda11602065aa5d8",
      "tree": "e66dbebfb1e9a254c20954a2f2f98541aebfd5af",
      "parents": [
        "b5f5d746ac3f2c3088292395603cb1470e7749d2"
      ],
      "author": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Mon May 15 13:39:18 2017 +0100"
      },
      "committer": {
        "name": "Vladimir Marko",
        "email": "vmarko@google.com",
        "time": "Wed Jun 07 15:39:24 2017 +0100"
      },
      "message": "Use ArtMethod* .bss entries for HInvokeStaticOrDirect.\n\nTest: m test-art-host-gtest\nTest: testrunner.py --host\nTest: testrunner.py --target\nTest: Nexus 6P boots.\nTest: Build aosp_mips64-userdebug.\nBug: 30627598\nChange-Id: I0e54fdd2e91e983d475b7a04d40815ba89ae3d4f\n"
    },
    {
      "commit": "96b6682d2d65f94c262590ef88bafdc70171ab8c",
      "tree": "ebb8a72edbaff6a6c62a6ce8bfb177a57389abaf",
      "parents": [
        "9ef68a3ad02eb7e2242a6d7f6a208c7a9b8ac407"
      ],
      "author": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Sat Sep 10 02:32:44 2016 -0700"
      },
      "committer": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Wed Sep 14 00:44:11 2016 -0700"
      },
      "message": "MIPS32: Implement table-based packed switch\n\nTest: booted MIPS32R2 in QEMU\nTest: test-art-target-run-test-optimizing (MIPS32R2) on CI20\nTest: booted MIPS64 (with 2nd arch MIPS32R6) in QEMU\nTest: test-art-target-run-test-optimizing (MIPS32R6) in QEMU\nTest: test-art-host-gtest\n\nChange-Id: I2e1a65ff1ba9406b84351ba7998f853b1ce4aef9\n"
    },
    {
      "commit": "e3fb245fbdb5e91cf8a9750504df40bd629e0080",
      "tree": "a3882db92b7942b2edd6add3090b5c875fef2d09",
      "parents": [
        "1fdb340de4e608a88e8683c857cad5d0da2c16de"
      ],
      "author": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Tue May 10 16:08:05 2016 -0700"
      },
      "committer": {
        "name": "Alexey Frunze",
        "email": "Alexey.Frunze@imgtec.com",
        "time": "Fri Jul 01 14:10:14 2016 -0700"
      },
      "message": "MIPS32: Improve method invocation\n\nImprovements include:\n- CodeGeneratorMIPS::GenerateStaticOrDirectCall() supports:\n  - MethodLoadKind::kDirectAddressWithFixup (via literals)\n  - CodePtrLocation::kCallDirectWithFixup (via literals)\n  - MethodLoadKind::kDexCachePcRelative\n- 32-bit literals to support the above (not ready for general-\n  purpose applications yet because RA is not saved in leaf\n  methods, but is clobbered on MIPS32R2 when simulating\n  PC-relative addressing (MIPS32R6 is OK because it has\n  PC-relative addressing with the lwpc instruction))\n- shorter instruction sequences for recursive static/direct\n  calls\n\nTested:\n- test-art-host-gtest\n- test-art-target-gtest and test-art-target-run-test-optimizing on:\n  - MIPS32R2 QEMU\n  - CI20 board\n  - MIPS32R6 (2nd arch) QEMU\n\nChange-Id: Id5b137ad32d5590487fd154c9a01d3b3e7e044ff\n"
    }
  ]
}