)]}' { "log": [ { "commit": "fbdaa30a448029d75422c76f29087a4e39630f4a", "tree": "e28784ff44d740884a7949f11745706e2831c873", "parents": [ "b4e2fbbed28c3bcdb8fd0fee5a201ba78e1edf28" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri May 29 12:06:56 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri May 29 12:06:56 2015 +0100" }, "message": "Use the new HCurrentMethod in HLoadString.\n\nChange-Id: I23d27e5e10736d127519eb3238ff8f25df3843a2\n" }, { "commit": "b4e2fbbed28c3bcdb8fd0fee5a201ba78e1edf28", "tree": "2da8c563cca7c9e7e125819ba3022915dca18ca9", "parents": [ "31db3432157caac55584a59827c69b303ba09d13", "76b1e1799a713a19218de26b171b0aef48a59e98" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu May 28 10:10:24 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu May 28 10:10:24 2015 +0000" }, "message": "Merge \"Add a HCurrentMethod node.\"" }, { "commit": "76b1e1799a713a19218de26b171b0aef48a59e98", "tree": "897d0d22d246367eb09d8b825b43c384074083f4", "parents": [ "382f5c24eb663ca8fa39a94a038349138a00272a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed May 27 17:18:33 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu May 28 10:44:36 2015 +0100" }, "message": "Add a HCurrentMethod node.\n\nThis enables register allocation for the current method, so\nthat users of it don\u0027t always load it from the stack.\n\nCurrently only used by HLoadClass. Will make follow-up\nCLs for the other users.\n\nChange-Id: If73324d85643102faba47fabbbd2755eb258c59c\n" }, { "commit": "0d37cd0a895cedb1653cf9897d9f9058855e2aee", "tree": "51a4e8310601cc4b5910eee15413d2c70fca3078", "parents": [ "6c70104dc3ecd66b46f56cae068a14e12021c9f2" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed May 27 16:39:19 2015 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed May 27 16:48:45 2015 +0100" }, "message": "Rename VisitCondition\u0027s argument in code generators.\n\nThis argument is a condition instruction, not a comparison.\n\nChange-Id: I026f799d2161df58b0c8a84600eb8fffd6f7b998\n" }, { "commit": "33bf2459e6cfe477a9be0c45aec3f6f359ee077c", "tree": "b7f62193677c1516f53ddbc5eef58cf26b9ec907", "parents": [ "00f09ff93480d5f43aaf657650a59d57330184aa" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed May 27 10:08:24 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed May 27 10:08:24 2015 -0400" }, "message": "[optimizing] x86: Prefer add over lea if possible\n\nLooking at some generated code, I noticed an lea being used when an add\nwas sufficient. Check for that case, and generate the add.\n\nFixed for x86 and x86_64.\n\nChange-Id: I110304ff0fed8837ada96d34353a293d29022ce5\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "07276db28d654594e0e86e9e467cad393f752e6e", "tree": "6450e07d64045f0c0949b3423501316b672641c7", "parents": [ "17f1bc531ea2f8c1a6fac3def13dee1b901949dd" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 18 14:22:09 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon May 18 19:15:52 2015 +0100" }, "message": "Don\u0027t do a null test in MarkGCCard if the value cannot be null.\n\nChange-Id: I45687f6d3505178e2fc3689eac9cb6ab1b2c1e29\n" }, { "commit": "c74652867cd9293e86232324e5e057cd73c48e74", "tree": "2670fa4ee6ff86e7c7a6d7ffa07f7a58df45dfb5", "parents": [ "70d3d1433ee3d33dfdc9f687c94383d527871455" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Wed May 13 17:50:09 2015 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri May 15 14:04:08 2015 +0100" }, "message": "ART: Refactor GraphVisualizer attribute printing\n\nThis patch unifies the way GraphVisualizer prints instruction\nattributes in preparation of changes to the Checker syntax.\n\nChange-Id: I44e91e36c660985ddfe039a9f410fedc48b496ec\n" }, { "commit": "ba56d060116d6e145be348fa575314654c6b0572", "tree": "4ef90809f6628435a60320b8fa0fd939849e2d29", "parents": [ "6727a48193db2a0cf01af971cccffe1a6518c247" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue May 05 21:34:03 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Mon May 11 08:44:54 2015 -0400" }, "message": "[optimizing] Improve 32 bit long shift by 1.\n\nAlso change FOO \u003c\u003c 1 to FOO+FOO in the instruction simplifier. This is\nan architecture independent simplification, which helps \u0027long \u003c\u003c 1\u0027 for\n32 bit architectures.\n\nGenerate an add/adc for long \u003c\u003c 1 in x86, in case something is generated\nafter the simplifier.\n\nAdd test cases for the simplification.\n\nChange-Id: I0d512331ef13cc4ccf10c80f11c370a10ed02294\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "db216f4d49ea1561a74261c29f1264952232728a", "tree": "8b7914435ad1ba519a3d88b5cca7f0f6e842cd4f", "parents": [ "bc3b93eadd155342b6124d2d5ef3806ecec5dfd6" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue May 05 17:02:20 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu May 07 09:54:09 2015 +0100" }, "message": "Relax the only one back-edge restriction.\n\nThe rule is in the way for better register allocation, as\nit creates an artificial join point between multiple paths.\n\nChange-Id: Ia4392890f95bcea56d143138f28ddce6c572ad58\n" }, { "commit": "7394569c9252b277710b2d7d3fc35fb0dd48fc4b", "tree": "9ce2241c95d93e873c45416a2d17e2c4084d220b", "parents": [ "8a30bf23bcb1ad8d4ed9060ddbb27edbfd57a897" ], "author": { "name": "Mark P Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Apr 29 14:56:17 2015 +0000" }, "committer": { "name": "Mark P Mendell", "email": "mark.p.mendell@intel.com", "time": "Mon May 04 14:14:32 2015 +0000" }, "message": "Revert \"Revert \"Revert \"Revert \"[optimizing] Improve x86 shifts\"\"\"\"\n\nThis reverts commit 2a7a1d7808f003bea908023ebd11eb442d2fca39.\n\nFix the problem that a long long \u003e\u003e 63 got the wrong answer. The\nproblem was that a shr was used instead of a sar.\n\nChange-Id: I0327f79c718016ddec9272a605fc50ec15ec4566\n" }, { "commit": "2d27c8e338af7262dbd4aaa66127bb8fa1758b86", "tree": "e01e0bc57359df0bdf00c3da694c5403fb7fc9e6", "parents": [ "3adfc4bbe6c42d574bd2069d8e38a13d5ad98ccf" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Apr 28 15:48:45 2015 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Wed Apr 29 14:09:17 2015 +0100" }, "message": "Refactor InvokeDexCallingConventionVisitor in Optimizing.\n\nChange-Id: I7ede0f59d5109644887bf5d39201d4e1bf043f34\n" }, { "commit": "80613ffd5699e6207d6b1264d600a0fc168074ce", "tree": "dbe8971e367e2529586821f3caa223fd22c28ce3", "parents": [ "a94fb1f99ee3390bca9531b2512f8fc65f13ceee", "3e3d73349a2de81d14e2279f60ffbd9ab3f3ac28" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Apr 28 10:31:38 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Apr 28 10:31:38 2015 +0000" }, "message": "Merge \"Have HInvoke instructions know their number of actual arguments.\"" }, { "commit": "3e3d73349a2de81d14e2279f60ffbd9ab3f3ac28", "tree": "69ad3378263c9a4b967cb7e27de0027264c12eb6", "parents": [ "a0ee862288b702468f8c2b6d0ad0f1c61be0b483" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Apr 28 11:00:54 2015 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Apr 28 11:00:54 2015 +0100" }, "message": "Have HInvoke instructions know their number of actual arguments.\n\nAdd an art::HInvoke::GetNumberOfArguments routine so that\nart::HInvoke and its subclasses can return the number of\nactual arguments of the called method. Use it in code\ngenerators and intrinsics handlers.\n\nConsequently, no longer remove a clinit check as last input\nof a static invoke if it is still present during baseline\ncode generation, but ensure that static invokes have no such\ncheck as last input in optimized compilations.\n\nChange-Id: Iaf9e07d1057a3b15b83d9638538c02b70211e476\n" }, { "commit": "848f70a3d73833fc1bf3032a9ff6812e429661d9", "tree": "b0349b3a40aab5a915af491b100659a5ca9fbbf6", "parents": [ "d14438f0c5071962be7fab572b54687d32d9d087" ], "author": { "name": "Jeff Hao", "email": "jeffhao@google.com", "time": "Wed Jan 15 13:49:50 2014 -0800" }, "committer": { "name": "Jeff Hao", "email": "jeffhao@google.com", "time": "Mon Apr 27 18:54:52 2015 -0700" }, "message": "Replace String CharArray with internal uint16_t array.\n\nSummary of high level changes:\n - Adds compiler inliner support to identify string init methods\n - Adds compiler support (quick \u0026 optimizing) with new invoke code path\n that calls method off the thread pointer\n - Adds thread entrypoints for all string init methods\n - Adds map to verifier to log when receiver of string init has been\n copied to other registers. used by compiler and interpreter\n\nChange-Id: I797b992a8feb566f9ad73060011ab6f51eb7ce01\n" }, { "commit": "808db5276827c909818d5595a5600e64b97f66e0", "tree": "7098009ac994bb77a40d07390610f63d767a0dec", "parents": [ "c435e014f7c0c93b0459a0d04e3f7e893d6ce9c6", "99dbd6883f5dab7743d5fb5d0ad2e82c75a7011e" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Sat Apr 25 03:25:43 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Sat Apr 25 03:25:43 2015 +0000" }, "message": "Merge \"[optimizing] Handle x86 const length BoundsCheck\"" }, { "commit": "99dbd6883f5dab7743d5fb5d0ad2e82c75a7011e", "tree": "21b307f551ec645aeefb848c7fb2d8b7f41c6e67", "parents": [ "76f1413492c228bfa710e1eaa4c60370eaffbb8a" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Apr 22 16:18:52 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Apr 24 19:53:16 2015 -0400" }, "message": "[optimizing] Handle x86 const length BoundsCheck\n\nAllow a constant length for BoundsCheck.\n\nChange-Id: I2c7adc6e733cf8ce6997aba76aa763d0835bd2d6\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "0379f82393237798616d485ad99952e73e480e12", "tree": "87f5ccd1fd0f4fa8156c31191040b7433c9ec907", "parents": [ "3507b795c034617e1c94fc9544a208d6c6f75735" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Apr 24 23:01:24 2015 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Apr 24 23:29:06 2015 +0100" }, "message": "Fix DCHECKs about clinit checks in Optimizing\u0027s code generators.\n\nThese assertions are not true for the baseline compiler. As\na temporary workaround, remove a clinit check as last input\nof a static invoke if it is still present at the stage of\ncode generation.\n\nChange-Id: I5655f4a0873e2e7ee7790b6a341c18b4b7b52af1\n" }, { "commit": "eb5459ca861b58ee8a9907789f11400dcdddb87b", "tree": "36c1f328c48f0ec111ee31702cc4a82ddb2ad784", "parents": [ "ae803f6efbe8378b5423c51ee3c5564cae0e6e59", "4c0eb42259d790fddcd9978b66328dbb3ab65615" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Apr 24 18:17:40 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Apr 24 18:17:41 2015 +0000" }, "message": "Merge \"Ensure inlined static calls perform clinit checks in Optimizing.\"" }, { "commit": "4c0eb42259d790fddcd9978b66328dbb3ab65615", "tree": "9d1ac505dfd4d0225f479d860b72a58747c8f6ce", "parents": [ "223f2f5b2a20ca8246da1523494900a2424d5956" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Apr 24 16:43:49 2015 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Apr 24 16:43:49 2015 +0100" }, "message": "Ensure inlined static calls perform clinit checks in Optimizing.\n\nCalls to static methods have implicit class initialization\n(clinit) checks of the method\u0027s declaring class in\nOptimizing. However, when such a static call is inlined,\nthe implicit clinit check vanishes, possibly leading to an\nincorrect behavior.\n\nTo ensure that inlining static methods does not change the\nbehavior of a program, add explicit class initialization\nchecks (art::HClinitCheck) as well as load class\ninstructions (art::HLoadClass) as last input of static\ncalls (art::HInvokeStaticOrDirect) in Optimizing\u0027 control\nflow graphs, when the declaring class is reachable and not\nknown to be already initialized. Then when considering the\ninlining of a static method call, proceed only if the method\nhas no implicit clinit check requirement.\n\nThe added explicit clinit checks are already removed by the\nart::PrepareForRegisterAllocation visitor. This CL also\nextends this visitor to turn explicit clinit checks from\nstatic invokes into implicit ones after the inlining step,\nby removing the added art::HLoadClass nodes mentioned\nhereinbefore.\n\nChange-Id: I9ba452b8bd09ae1fdd9a3797ef556e3e7e19c651\n" }, { "commit": "5ea536aa4a6414db01beaf6f8bd8cb9adc5cfc92", "tree": "27b3f1c148744452b26bd4841f0dabe0549c3d86", "parents": [ "c5cb691ca6a746a193bfbe3525aafa7cbb281d40" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Mon Apr 20 20:11:30 2015 +0100" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Fri Apr 24 11:08:46 2015 +0100" }, "message": "Remove ArtMethod* parameter from dex cache entry points.\n\nLoad the ArtMethod* using an optimized stack walk instead.\nThis reduces the size of the generated code.\n\nThree of the entry points are called only from a slow-path\nand the fourth (InitializeTypeAndVerifyAccess) is rare and\nalready slow enough that the one or two extra loads\n(depending on whether we already have the ArtMethod* in a\nregister) are insignificant. And as we\u0027re starting to use\nPC-relative addressing of the dex cache arrays (already\ndone by Quick for the boot image), having the ArtMethod* in\na register becomes less likely anyway.\n\nChange-Id: Ib19b9d204e355e13bf386662a8b158178bf8ad28\n" }, { "commit": "322b389a74177c9d938f1f73d53110623dfc61b6", "tree": "b2437d4cdce399ce462d587d9c9c47a8fceb8953", "parents": [ "272bf7e60add5f741fb9a2589eaa71945257afcc", "af88835231c2508509eb19aa2d21b92879351962" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Apr 23 17:19:34 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 23 17:19:34 2015 +0000" }, "message": "Merge \"Remove unnecessary null checks in CheckCast and InstanceOf\"" }, { "commit": "af88835231c2508509eb19aa2d21b92879351962", "tree": "4ef1c8fb3c5b78175767999a888b0c2cb1ea6485", "parents": [ "da93333d568f3c5bd8eeb58341d10a332e1d42bf" ], "author": { "name": "Guillaume \"Vermeille\" Sanchez", "email": "guillaumesa@google.com", "time": "Mon Apr 20 14:41:30 2015 +0100" }, "committer": { "name": "Guillaume \"Vermeille\" Sanchez", "email": "guillaumesa@google.com", "time": "Thu Apr 23 17:53:17 2015 +0100" }, "message": "Remove unnecessary null checks in CheckCast and InstanceOf\n\nChange-Id: I6fd81cabd8673be360f369e6318df0de8b18b634\n" }, { "commit": "4bb014fd8e0aa45b012d56bc4813f18fa295d2b0", "tree": "ba5fa5beef6e2c4a91ec5bbe7b0ed81b168b4958", "parents": [ "d677de20906067061f262bdd434536a02e7f0dd0", "232ade0b9401404ad4b61b1003551b58b96195a8" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Apr 21 16:09:29 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Apr 21 16:09:30 2015 +0000" }, "message": "Merge \"Revert \"Revert \"Optimizing: Fix long-to-fp conversion on x86.\"\"\"" }, { "commit": "b3306642f42d47ddb4d021a2f48ce9b1bd235857", "tree": "5b997bad1c6021c1ab777c2250816f1c22e930db", "parents": [ "b9791aa606834160b085dec7c5b32ccbeaf9a186" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Apr 20 18:30:42 2015 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Tue Apr 21 13:59:33 2015 +0100" }, "message": "[optimzing] Fix codegen bug and improve type propagation\n\n- don\u0027t bound the type if there are no relevant uses\n- insert the bound type in the bounded block (this allows for condition\nmaterialization without changing the logic there).\n- add more comments\n- add tests for BoundType generation\n- fix GenerateTestAndBranch\n\nChange-Id: I5c1fdda104da4a46775d207270220d410234a472\n" }, { "commit": "6149f962cd0815c61c134a7554036ca88d0abef1", "tree": "d41a91d6d43caaf6efd117ad482c7d558790471f", "parents": [ "9fab1eea3b9dc7a284dd74487ac603d9ffbb79fb", "8693fe1eda2e37ad162d792e9e793827bfa1c236" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Mon Apr 20 17:11:32 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Apr 20 17:11:33 2015 +0000" }, "message": "Merge \"RecordPcInfo() in GenerateStaticOrDirectCall() is misplaced on x86.\"" }, { "commit": "232ade0b9401404ad4b61b1003551b58b96195a8", "tree": "54fe7cc37674246dead84f883a4c8be2123e7d26", "parents": [ "2e0f89b1b61685f7c322a4c6ec3e3b4839e76d64" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Apr 20 15:14:36 2015 +0100" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Mon Apr 20 15:53:12 2015 +0100" }, "message": "Revert \"Revert \"Optimizing: Fix long-to-fp conversion on x86.\"\"\n\nThis reverts commit 386ce406f150645158d6067c4e0a36565aefc44f.\n\nBug: 20413424\nChange-Id: I6e93ff132907f2653f1ae12d6676ff2298f62ca1\n" }, { "commit": "36aafd94af64d6f1ba603392f66959998f2a93a2", "tree": "13de8641b36380015b80dac1a231b58d08b3de29", "parents": [ "aff3f0a0a2a080e313ae80c9b0216aa26a668623", "27df758e2e7baebb6e3f393f9732fd0d064420c8" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Apr 20 13:03:14 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Apr 20 13:03:14 2015 +0000" }, "message": "Merge \"[optimizing] Add memory barriers in constructors when needed\"" }, { "commit": "27df758e2e7baebb6e3f393f9732fd0d064420c8", "tree": "261207281fd574deffb4dc1c1bc6bea8f150993e", "parents": [ "f8bdd9f3a002970e4b8fdcf6fe6730116f1626c3" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Apr 17 19:12:31 2015 +0100" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Apr 20 14:02:51 2015 +0100" }, "message": "[optimizing] Add memory barriers in constructors when needed\n\nIf a class has final fields we must add a memory barrier before\nreturning from constructor. This makes sure the fields are visible to\nother threads.\n\nBug: 19851497\nChange-Id: If8c485092fc512efb9636cd568cb0543fb27688e\n" }, { "commit": "88c13cddc3a4184908662b0f3de796565d348c76", "tree": "6986849099ff7afc042eac31a3e53df0c468962b", "parents": [ "f458ba7d9c04bc8d499532b5470af28db18e4149" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Tue Apr 14 17:35:39 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Apr 20 11:35:44 2015 +0100" }, "message": "Opt compiler: Correctly require register or FPU register.\n\nAlso add a check that location summary are correctly typed\nwith the HInstruction.\n\nChange-Id: I699762ff4e8f4e321c7db01ea005236ea1934af9\n" }, { "commit": "8693fe1eda2e37ad162d792e9e793827bfa1c236", "tree": "25477a6397692e3c46eb75b8b6bee8b6c1c0cce9", "parents": [ "33259fdfcd350793d10f67f2ea7dfc6051a8afa2" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Fri Apr 17 16:51:08 2015 -0700" }, "committer": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Fri Apr 17 17:09:12 2015 -0700" }, "message": "RecordPcInfo() in GenerateStaticOrDirectCall() is misplaced on x86.\n\nGenerateStaticOrDirectCall() is invoked in intrinsics_x86.cc and\nRecordPcInfo() is already taken care of there. It should be moved\nto VisitInvokeStaticOrDirect() as done in other archs.\n\nChange-Id: Id08d84c9046e55dea9d8a8452c979294c4183150\n" }, { "commit": "13b4718ecd52a674b25eac106e654d8e89872750", "tree": "34d6efd2cda3ceb233118e4d135c4a897f02ea12", "parents": [ "da93333d568f3c5bd8eeb58341d10a332e1d42bf" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Wed Apr 15 16:29:32 2015 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Thu Apr 16 11:09:55 2015 +0100" }, "message": "ART: Remove DCHECKs for boolean type\n\nSince bool and int are interchangeable types, checking whether an\ninput is kPrimBoolean can fail when replaced with 0/1 constant or\na phi. This patch removes the problematic DCHECKs, adds a best-effort\nverification into SSAChecker but leaves the phi case empty until a\nsuitable analysis is implemented.\n\nChange-Id: I31e8daf27dd33d2fd74049b82bed1cb7c240c8c6\n" }, { "commit": "669d8a1edbb2a78e08731a9cd6d8e815b0ec49db", "tree": "240d26edb4af28ccd7fa65a9fecc39f718d3d603", "parents": [ "ee2da343bb2a54d9d77e29226e0317ccc913c8c1", "e14590bdfed24df30e6b7545fc819ba03ff8bba1" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Apr 16 09:40:38 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 16 09:40:39 2015 +0000" }, "message": "Merge \"Revert \"[optimizing] Improve x86 parallel moves/swaps\"\"" }, { "commit": "e14590bdfed24df30e6b7545fc819ba03ff8bba1", "tree": "1fe89a424c91dae7adc07ebd620dce8297a0854e", "parents": [ "a5c19ce8d200d68a528f2ce0ebff989106c4a933" ], "author": { "name": "Guillaume Sanchez", "email": "guillaumesa@google.com", "time": "Wed Apr 15 18:57:27 2015 +0000" }, "committer": { "name": "Guillaume Sanchez", "email": "guillaumesa@google.com", "time": "Wed Apr 15 18:57:27 2015 +0000" }, "message": "Revert \"[optimizing] Improve x86 parallel moves/swaps\"\n\nThis reverts commit a5c19ce8d200d68a528f2ce0ebff989106c4a933.\n\nThis commit introduces a performance regression on CaffeineLogic of 30%.\n\nChange-Id: I917e206e249d44e1748537bc1b2d31054ea4959d\n" }, { "commit": "a76a08fed88bd081bcc4d240f1ba3472a2acbbab", "tree": "cd016bb007c3757ab2a6df28bc1a65d6a8e78e44", "parents": [ "acf9b7b7616a9b104e6f2146051d8e14d9cb9030", "9021825d1e73998b99c81e89c73796f6f2845471" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Apr 15 14:10:29 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Apr 15 14:10:29 2015 +0000" }, "message": "Merge \"Type MoveOperands.\"" }, { "commit": "9021825d1e73998b99c81e89c73796f6f2845471", "tree": "13e1038931cbb8bf8b8d0f4e3f51553ba1bfa983", "parents": [ "858d28ca2e73a785977f53141e775a7d4841b89d" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Apr 15 11:56:51 2015 +0100" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Apr 15 12:53:42 2015 +0100" }, "message": "Type MoveOperands.\n\nThe ParallelMoveResolver implementation needs to know if a move\nis for 64bits or not, to handle swaps correctly.\n\nBug found, and test case courtesy of Serguei I. Katkov.\n\nChange-Id: I9a0917a1cfed398c07e57ad6251aea8c9b0b8506\n" }, { "commit": "66d126ea06ce3f507d86ca5f0d1f752170ac9be1", "tree": "8e247db17ef085b55725b21c64d292414fd00b32", "parents": [ "9bb3e8e10d7d9230a323511094a9e260062a1473" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Fri Apr 03 16:02:44 2015 +0100" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Wed Apr 15 12:51:49 2015 +0100" }, "message": "ART: Implement HBooleanNot instruction\n\nOptimizations simplifying operations on boolean values (boolean\nsimplifier, instruction simplifier) can benefit from having a special\nHInstruction for negating booleans in order to perform more transforms\nand produce faster machine code.\n\nThis patch implements HBooleanNot as \u0027x xor 1\u0027, assuming that booleans\nare 1-bit integers and allowing for a single-instruction negation on\nall supported platforms.\n\nChange-Id: I33a2649c1821255b18a86ca68ed16416063c739f\n" }, { "commit": "daba9dff2ba0160332fe54ab14fc4283b8ea86fb", "tree": "0984e431727fe4dd8b56d2891a2d343882daebbf", "parents": [ "c4542866d2e68dcdfa2c7efa5cddbb131003da81", "9d8606de5e274c00242ee73ffb693bc34589f184" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Mon Apr 13 20:00:39 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Apr 13 20:00:40 2015 +0000" }, "message": "Merge \"Whitespace cleanup in DWARFReg helper functions.\"" }, { "commit": "9d8606de5e274c00242ee73ffb693bc34589f184", "tree": "bc16051f6b9de2a69bdf0c7f6800d6534d10d005", "parents": [ "58565098b2298041ccc97371a3cc486df88d51b3" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Sun Apr 12 09:35:32 2015 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Sun Apr 12 09:35:32 2015 +0100" }, "message": "Whitespace cleanup in DWARFReg helper functions.\n\nChange-Id: Iedc05969b05be6d93e40467ff23287faaae08fb3\n" }, { "commit": "c34dc9362b9ec624b3bdd97d36b6b2098814cd73", "tree": "c2049b2dc19d318e3917b52ef66608b985d7ac69", "parents": [ "58565098b2298041ccc97371a3cc486df88d51b3" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Sun Apr 12 09:27:43 2015 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Sun Apr 12 09:30:57 2015 +0100" }, "message": "Move \u0027ret\u0027 instruction generation inside GenerateFrameExit.\n\nChange-Id: I0c594d9a2356a006a5ce8dfd41d307cf7c3704ba\n" }, { "commit": "1b743777e6b6cec3387b0ee347b6a8a03779c345", "tree": "036c42dbf10d8c75de1326e16406a12191c704ce", "parents": [ "cf69f8163d700be29a1732e7e229101c67a51803", "f9aac1e9f442c2486cd54f045d43e15791601205" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Apr 10 21:40:59 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Apr 10 21:41:00 2015 +0000" }, "message": "Merge \"Revert \"[optimizing] Improve x86 shifts\"\"" }, { "commit": "f9aac1e9f442c2486cd54f045d43e15791601205", "tree": "2f3aa65a881020beeb6f4b3313b3366733bbf3f5", "parents": [ "222fcf96c9b73bbb739012575e7e413caf9348ec" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Apr 10 18:12:48 2015 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Apr 10 18:12:48 2015 +0000" }, "message": "Revert \"[optimizing] Improve x86 shifts\"\n\nThis reverts commit 222fcf96c9b73bbb739012575e7e413caf9348ec.\n\nReverting this CL as it is breaking a few tests (see http://build.chromium.org/p/client.art/builders/host-x86/builds/3251/steps/test%20optimizing/logs/stdio). Will investigate ASAP.\n\nChange-Id: Iddd8363e83a24aa49fbdf0f0c9dc12e63b4848de\n" }, { "commit": "27ef3177fb164b5e1a3b8a6fd43d25f3074e586d", "tree": "3717202ea300f60f6df3aa29922b98579b7958d5", "parents": [ "47317b430ee4f0094e58df45b557fe754b29b63b", "b19930c5cba3cf662dce5ee057fcc9829b4cbb9c" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Apr 10 16:15:07 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Apr 10 16:15:07 2015 +0000" }, "message": "Merge \"Follow up of \"div/rem on x86 and x86_64\", to tidy up the code a little.\"" }, { "commit": "a5c19ce8d200d68a528f2ce0ebff989106c4a933", "tree": "4638a8d8e5b1562ec5ed05967490fec1ef7f0d17", "parents": [ "6d80318c382a3490ab605b46fa7cb22c5e823fec" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Apr 01 12:51:05 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Apr 10 12:08:31 2015 -0400" }, "message": "[optimizing] Improve x86 parallel moves/swaps\n\nAdd a new constructor to ScratchRegisterScope that will supply a\nregister if there is a free one, but not spill to force one. Use this\nto generated alternate code that doesn\u0027t use a temporary, as the\nspill/restore of a register generates extra instructions that aren\u0027t\nnecessary on x86.\n\nHere is the benefit for a 32 bit memory-to-memory exchange with no\nfree registers:\n\u003c 50 \t push eax\n\u003c 53 \t push ebx\n\u003c 8B44244C \t mov eax, [esp + 76]\n\u003c 8B5C246C \t mov ebx, [esp + 108]\n\u003c 8944246C \t mov [esp + 108], eax\n\u003c 895C244C \t mov [esp + 76], ebx\n\u003c 5B \t pop ebx\n\u003c 58 \t pop eax\n---\n\u003e FF742444 \t push [esp + 68]\n\u003e FF742468 \t push [esp + 104]\n\u003e 8F44244C \t pop [esp + 72]\n\u003e 8F442468 \t pop [esp + 100]\n\nAvoid using xchg instruction, as it is slow on smaller processors.\n\nChange-Id: Id29ee3abd998577baaee552d55d23e60ae0c7871\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "6d80318c382a3490ab605b46fa7cb22c5e823fec", "tree": "1fe89a424c91dae7adc07ebd620dce8297a0854e", "parents": [ "07d1f0d6c15f78e107c7b77e993b4d4d08ae1ad8", "222fcf96c9b73bbb739012575e7e413caf9348ec" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Apr 10 15:39:15 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Apr 10 15:39:16 2015 +0000" }, "message": "Merge \"[optimizing] Improve x86 shifts\"" }, { "commit": "07d1f0d6c15f78e107c7b77e993b4d4d08ae1ad8", "tree": "34a48e22719bec06356788bd904b425dbe84284e", "parents": [ "4df30d988105f988dbcdb4f28263654e9ce20687", "55501ce0db57bccfa23b0226faffc964203701f9" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Fri Apr 10 14:15:37 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Apr 10 14:15:38 2015 +0000" }, "message": "Merge \"Optimizing x86: Fix VisitArraySet for FP value\"" }, { "commit": "222fcf96c9b73bbb739012575e7e413caf9348ec", "tree": "e0441bc484cc8f441685de49c931a030730a3701", "parents": [ "fcfea6324b2913621d5cb642d4315f22c4901368" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Mon Mar 30 14:13:30 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Apr 10 09:33:52 2015 -0400" }, "message": "[optimizing] Improve x86 shifts\n\nSupport memory operands for integer shifts. Generate better code for\nlong shifts by constants.\n\nChange-Id: Icc92fa1b59cc280d4894af6f054e19b01977d5ce\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "b19930c5cba3cf662dce5ee057fcc9829b4cbb9c", "tree": "c226f8fffc4522b273072c516507083e2a77c505", "parents": [ "0f88e87085b7cf6544dadff3f555773966a6853e" ], "author": { "name": "Guillaume Sanchez", "email": "guillaumesa@google.com", "time": "Thu Apr 09 21:12:15 2015 +0100" }, "committer": { "name": "Guillaume Sanchez", "email": "guillaumesa@google.com", "time": "Fri Apr 10 10:28:02 2015 +0100" }, "message": "Follow up of \"div/rem on x86 and x86_64\", to tidy up the code a little.\n\nChange-Id: Ibf39cbc8ac1d773599d70be2cb1e941674b60f1d\n" }, { "commit": "55501ce0db57bccfa23b0226faffc964203701f9", "tree": "b9abd5dcbfd1ec5aff448e4a5d0ce051b27f0466", "parents": [ "1576be32be4a99a1cffdaaf209a3cd67e8b2f88a" ], "author": { "name": "Serguei Katkov", "email": "serguei.i.katkov@intel.com", "time": "Wed Apr 08 13:26:09 2015 +0600" }, "committer": { "name": "Serguei Katkov", "email": "serguei.i.katkov@intel.com", "time": "Fri Apr 10 14:50:43 2015 +0600" }, "message": "Optimizing x86: Fix VisitArraySet for FP value\n\nInstruction generator expects to see FP value in XMM register,\nso update location builder to follow this.\n\nChange-Id: Idca4bb5cdb59249c77fcc6f76cdfcaba47222b3d\nSigned-off-by: Serguei Katkov \u003cserguei.i.katkov@intel.com\u003e\n" }, { "commit": "917f0866f66d3465fa41ddcf9ab09eba2fa78dd3", "tree": "08bc03c6ac1a3d06672edaf4b74ce89db4c28da5", "parents": [ "467e33616472fe92051c75b65327aad87a639f3f", "c6b4dd8980350aaf250f0185f73e9c42ec17cd57" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu Apr 09 17:27:31 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 09 17:27:31 2015 +0000" }, "message": "Merge \"Implement CFI for Optimizing.\"" }, { "commit": "c6b4dd8980350aaf250f0185f73e9c42ec17cd57", "tree": "ef8d73e37abc04aecb430072a8bc463c73398fee", "parents": [ "dd97393aca1a3ff2abec4dc4f78d7724300971bc" ], "author": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Tue Apr 07 20:32:43 2015 +0100" }, "committer": { "name": "David Srbecky", "email": "dsrbecky@google.com", "time": "Thu Apr 09 16:47:50 2015 +0100" }, "message": "Implement CFI for Optimizing.\n\nCFI is necessary for stack unwinding in gdb, lldb, and libunwind.\n\nChange-Id: I1a3480e3a4a99f48bf7e6e63c4e83a80cfee40a2\n" }, { "commit": "96159860fc6c4bf68a51a8a57941971f122685d6", "tree": "ef2465ab2d84b9076ab57ad239333910f68abd2b", "parents": [ "0c51da5db821493bcef4617ccab04ea367ecc444", "0f88e87085b7cf6544dadff3f555773966a6853e" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Thu Apr 09 12:46:58 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 09 12:46:59 2015 +0000" }, "message": "Merge \"Speedup div/rem by constants on x86 and x86_64\"" }, { "commit": "0f88e87085b7cf6544dadff3f555773966a6853e", "tree": "ea0ae17c712b995e258f1f749a1b8cd98b1fa34b", "parents": [ "c4bd0e6a7f4839ea99222f06979cc2369cb9bf10" ], "author": { "name": "Guillaume Sanchez", "email": "guillaumesa@google.com", "time": "Mon Mar 30 17:55:45 2015 +0100" }, "committer": { "name": "Guillaume Sanchez", "email": "guillaumesa@google.com", "time": "Thu Apr 09 12:24:10 2015 +0100" }, "message": "Speedup div/rem by constants on x86 and x86_64\n\nThis is done using the algorithms in Hacker\u0027s Delight chapter 10.\n\nChange-Id: I7bacefe10067569769ed31a1f7834f796fb41119\n" }, { "commit": "65b798ea10dd716c1bb3dda029f9bf255435af72", "tree": "774e9901b6917989a63f07f927c3b4d8b921a013", "parents": [ "c411c6cc327d3f2b3b4d1987b07dd442205d9454" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Apr 06 09:35:22 2015 -0700" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Mon Apr 06 14:05:07 2015 -0700" }, "message": "ART: Enable more Clang warnings\n\nChange-Id: Ie6aba02f4223b1de02530e1515c63505f37e184c\n" }, { "commit": "97597c9be7f4eb5263a80e7de4684dbfa1427e9a", "tree": "690dc04c72690a056aa84ac0206f96e5f513b3c2", "parents": [ "7775d2c1e48c0bb0880f720f3dfbd4b4d0de7c6e", "fb8d279bc011b31d0765dc7ca59afea324fd0d0c" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Thu Apr 02 23:10:46 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Apr 02 23:10:46 2015 +0000" }, "message": "Merge \"[optimizing] Implement x86/x86_64 math intrinsics\"" }, { "commit": "e4285226d1d4d7c4feee16a968540fb2e363339f", "tree": "835b91c05b39cdb1053c2cd28e0e23c202dc020b", "parents": [ "79bdb47d8c87ca3ee7da4aa2ca56105728257a32", "d43b3ac88cd46b8815890188c9c2b9a3f1564648" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Wed Apr 01 23:15:52 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Apr 01 23:15:53 2015 +0000" }, "message": "Merge \"Revert \"Revert \"Deoptimization-based bce.\"\"\"" }, { "commit": "d43b3ac88cd46b8815890188c9c2b9a3f1564648", "tree": "6c599c3f40d57e92786bd7f41c0541d9eaa2643b", "parents": [ "a109632b240f3c9355ca95500f6f48e4478e3c51" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Wed Apr 01 14:03:04 2015 -0700" }, "committer": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Wed Apr 01 14:05:13 2015 -0700" }, "message": "Revert \"Revert \"Deoptimization-based bce.\"\"\n\nThis reverts commit 0ba627337274ccfb8c9cb9bf23fffb1e1b9d1430.\n\nChange-Id: I1ca10d15bbb49897a0cf541ab160431ec180a006\n" }, { "commit": "fb8d279bc011b31d0765dc7ca59afea324fd0d0c", "tree": "01b21964ce0516bda835faa15b260ac290714fe0", "parents": [ "dcff612c3a6e1427749771c4559f198fa480f709" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Mar 31 22:16:59 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Apr 01 08:45:38 2015 -0400" }, "message": "[optimizing] Implement x86/x86_64 math intrinsics\n\nImplement floor/ceil/round/RoundFloat on x86 and x86_64.\nImplement RoundDouble on x86_64.\n\nAdd support for roundss and roundsd on both architectures. Support them\nin the disassembler as well.\n\nAdd the instruction set features for x86, as the \u0027round\u0027 instruction is\nonly supported if SSE4.1 is supported.\n\nFix the tests to handle the addition of passing the instruction set\nfeatures to x86 and x86_64.\n\nAdd assembler tests for roundsd and roundss to x86_64 assembler tests.\n\nChange-Id: I9742d5930befb0bbc23f3d6c83ce0183ed9fe04f\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "2be48692eaa15c1d9f6ca1b3477bb75429843aff", "tree": "b2be35b194d952907d44d77a6c6448cd41edbfed", "parents": [ "38d3b133dcb5968a69ffbcda58990fcdca5b56a1" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Tue Mar 31 17:03:08 2015 -0700" }, "committer": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Tue Mar 31 17:03:08 2015 -0700" }, "message": "Clean up some RecordPcInfo in x86 slow paths.\n\nCalling codegen-\u003eRecordPcInfo() is likely to miss the third argument which\nis the slow path. And can cause deopt bugs later.\n\nThe change calls the slow path\u0027s version of RecordPcInfo() in slow paths\nconsistently.\n\nChange-Id: I41605f1b06ee2c6d3d7ffd5aa0c1366940b5a029\n" }, { "commit": "42514f63aadfa9faec3718874db2108f3e89082d", "tree": "76d3abb94595097828724215cf8f6f5448bcf012", "parents": [ "547bfb87696fb53a87d4f4418da86938179af9cd" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Mar 31 11:34:22 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Mar 31 11:34:22 2015 -0400" }, "message": "[optimizing] trivial x86 explicit null check fix\n\nChange a cmp reg,0 to test reg,reg. I don\u0027t know that this code\nis even invoked.\n\nChange-Id: Ifddffcb22d8a4060b7abbea17d8e7168535e409b\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "d75948ac93a4a317feaf136cae78823071234ba5", "tree": "7593fb8c1ba2b67decdaa967b6348501f58d8b9d", "parents": [ "b3665e3dfdd23cc7a2f17a0b53bb16205bf4151f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 27 09:53:16 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 27 12:01:40 2015 +0000" }, "message": "Intrinsify String.compareTo.\n\nChange-Id: Ia540df98755ac493fe61bd63f0bd94f6d97fbb57\n" }, { "commit": "09ed1a3125849ec6ac07cb886e3c502e1dcfada2", "tree": "d86be714298806cfcd6a16be674573369474e8f7", "parents": [ "03910065cd025ecb07781b85c2240be69c202d75" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Mar 25 08:30:06 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Thu Mar 26 21:28:33 2015 -0400" }, "message": "[optimizing] Implement X86 intrinsic support\n\nImplement the supported intrinsics for X86.\n\nEnhance the graph visualizer to print \u003cU\u003e for unallocated locations, to\nallow calling the graph dumper from within register allocation for\ndebugging purposes.\n\nChange-Id: I3b0319eb70a9a4ea228f67065b4c52d13a1ae775\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "b2bd1c5f9171f35fa5b71ada42d1a9e11189428d", "tree": "db9165b3daa18d1d430b690b78c2d125bade3021", "parents": [ "11e99b19f48576f1bb6d0993635b34b6e09c9832" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Wed Mar 25 11:17:37 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Wed Mar 25 12:30:26 2015 +0000" }, "message": "ART: Formatting and comments in BooleanSimplifier\n\nChange-Id: I9a5aa3f2aa8b0a29d7b0f1e5e247397cf8e9e379\n" }, { "commit": "b64b782f9ae7a94ecbbf64c83cbcdc7d716ba560", "tree": "df3aa814ff7762d681c50781c413fd510440ae61", "parents": [ "2c2d00e8ca841aa2f57fa2f852e896378ef67144", "46e2a3915aa68c77426b71e95b9f3658250646b7" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Mar 24 17:31:29 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Tue Mar 24 17:31:31 2015 +0000" }, "message": "Merge \"ART: Boolean simplifier\"" }, { "commit": "46e2a3915aa68c77426b71e95b9f3658250646b7", "tree": "2b0a4470b05291894db73c631fe94f0fdff8c46b", "parents": [ "bce0855ca1dbb1fa226c5b6a81760272ce0b64ef" ], "author": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Mon Mar 16 17:31:52 2015 +0000" }, "committer": { "name": "David Brazdil", "email": "dbrazdil@google.com", "time": "Tue Mar 24 17:28:37 2015 +0000" }, "message": "ART: Boolean simplifier\n\nThe optimization recognizes the negation pattern generated by \u0027javac\u0027\nand replaces it with a single condition. To this end, boolean values\nare now consistently assumed to be represented by an integer.\n\nThis is a first optimization which deletes blocks from the HGraph and\ndoes so by replacing the corresponding entries with null. Hence,\nexisting code can continue indexing the list of blocks with the block\nID, but must check for null when iterating over the list.\n\nChange-Id: I7779da69cfa925c6521938ad0bcc11bc52335583\n" }, { "commit": "da4d79bc9a4aeb9da7c6259ce4c9c1c3bf545eb8", "tree": "151dd61c4b6a8fd512ea4c2c862af28b02f4ed9c", "parents": [ "af87659f462ac650009fce295097cae3dabce171" ], "author": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Mar 24 14:36:11 2015 +0000" }, "committer": { "name": "Roland Levillain", "email": "rpl@google.com", "time": "Tue Mar 24 16:02:21 2015 +0000" }, "message": "Unify ART\u0027s various implementations of bit_cast.\n\nART had several implementations of art::bit_cast:\n\n1. one in runtime/base/casts.h, declared as:\n\n template \u003cclass Dest, class Source\u003e\n inline Dest bit_cast(const Source\u0026 source);\n\n2. another one in runtime/utils.h, declared as:\n\n template\u003ctypename U, typename V\u003e\n static inline V bit_cast(U in);\n\n3. and a third local version, in runtime/memory_region.h,\n similar to the previous one:\n\n template\u003ctypename Source, typename Destination\u003e\n static Destination MemoryRegion::local_bit_cast(Source in);\n\nThis CL removes versions 2. and 3. and changes their callers\nto use 1. instead. That version was chosen over the others\nas:\n- it was the oldest one in the code base; and\n- its syntax was closer to the standard C++ cast operators,\n as it supports the following use:\n\n bit_cast\u003cDestination\u003e(source)\n\n since `Source\u0027 can be deduced from `source\u0027.\n\nChange-Id: I7334fd5d55bf0b8a0c52cb33cfbae6894ff83633\n" }, { "commit": "0ba627337274ccfb8c9cb9bf23fffb1e1b9d1430", "tree": "0e1d0813c1d8d1c7239a900c1653296975713df0", "parents": [ "e295e6ec5beaea31be5d7d3c996cd8cfa2053129" ], "author": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Mar 24 02:39:46 2015 +0000" }, "committer": { "name": "Andreas Gampe", "email": "agampe@google.com", "time": "Tue Mar 24 02:39:46 2015 +0000" }, "message": "Revert \"Deoptimization-based bce.\"\n\nThis breaks compiling the core image:\n\n Error after BCE: art::SSAChecker: Instruction 219 in block 1 does not dominate use 221 in block 1.\n\nThis reverts commit e295e6ec5beaea31be5d7d3c996cd8cfa2053129.\n\nChange-Id: Ieeb48797d451836ed506ccb940872f1443942e4e\n" }, { "commit": "e295e6ec5beaea31be5d7d3c996cd8cfa2053129", "tree": "4d8a657d23d511743ce35bee596544d7f652efdb", "parents": [ "d24ba2c44c76a2b2dd13aafe8f7981c15be31a98" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Sat Mar 07 06:37:59 2015 -0800" }, "committer": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Mon Mar 23 16:39:37 2015 -0700" }, "message": "Deoptimization-based bce.\n\nA mechanism is introduced that a runtime method can be called\nfrom code compiled with optimizing compiler to deoptimize into\ninterpreter. This can be used to establish invariants in the managed code\nIf the invariant does not hold at runtime, we will deoptimize and continue\nexecution in the interpreter. This allows to optimize the managed code as\nif the invariant was proven during compile time. However, the exception\nwill be thrown according to the semantics demanded by the spec.\n\nThe invariant and optimization included in this patch are based on the\nlength of an array. Given a set of array accesses with constant indices\n{c1, ..., cn}, we can optimize away all bounds checks iff all 0 \u003c\u003d min(ci) and\nmax(ci) \u003c array-length. The first can be proven statically. The second can be\nestablished with a deoptimization-based invariant. This replaces n bounds\nchecks with one invariant check (plus slow-path code).\n\nChange-Id: I8c6e34b56c85d25b91074832d13dba1db0a81569\n" }, { "commit": "af2bec33e5f124e37e9dbbe0fef1261411bd372d", "tree": "4b49689ff6d7483440fa250c68ea65b8f68e26dd", "parents": [ "461bd6cbcd26731aad019d382aafbdbc7ee19e69", "3f6c7f61855172d3d9b7a9221baba76136088e7c" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Mar 23 15:23:23 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Mon Mar 23 15:23:24 2015 +0000" }, "message": "Merge \"[optimizing] Improve x86, x86_64 code\"" }, { "commit": "68e15009173f92fe717546a621b56413d5e9fba1", "tree": "460f18693f53bcbcc6f79b03f8a211f271c973a7", "parents": [ "1311ef7226f6147f2ef8c491321972a79d73914a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Mar 17 16:16:49 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Mar 17 16:23:17 2015 +0000" }, "message": "PREOPT compiles using dex2oatd so don\u0027t emit debug instructions.\n\nChange-Id: I8d2ab8d956ad0ce313928918c658d49f490ad081\n" }, { "commit": "3f6c7f61855172d3d9b7a9221baba76136088e7c", "tree": "b61ab89a880ae74f44956425f5c9794d73ef029d", "parents": [ "cc22e3946baf035c8732e9417ab132bfe663aa45" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Mar 13 13:47:53 2015 -0400" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Mar 13 14:01:43 2015 -0400" }, "message": "[optimizing] Improve x86, x86_64 code\n\nTweak the generated code to allow more use of constants and other small\nchanges\n- Use test vs. compare to 0\n- EmitMove of 0.0 should use xorps\n- VisitCompare kPrimLong can use constants\n- cmp/add/sub/mul on x86_64 can use constants if in int32_t range\n- long bit operations on x86 examine long constant high/low to optimize\n- Use 3 operand imulq if constant is in int32_t range\n\nChange-Id: I2dd4010fdffa129fe00905b0020590fe95f3f926\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "a8ac9130b872c080299afacf5dcaab513d13ea87", "tree": "2bd0a2a88cbb6e7a3ae79dff84c466bed9189eb5", "parents": [ "cc22e3946baf035c8732e9417ab132bfe663aa45" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 16:36:36 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 13 16:47:44 2015 +0000" }, "message": "Refactor code in preparation of correct stack maps in slow path.\n\nMove the logic of saving/restoring live registers in slow path\nin the SlowPathCode method. Also add a RecordPcInfo helper to\nSlowPathCode, that will act as the placeholder of saving correct\nstack maps.\n\nChange-Id: I25c2bc7a642ef854bbc8a3eb570e5c8c8d2d030c\n" }, { "commit": "234d69d075d1608f80adb647f7935077b62b6376", "tree": "f6b68ff38722dc91bd0de2387609ee0ce950e0ce", "parents": [ "31df246d330c45f5691e226d176d0c59450f8435" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Mon Mar 09 10:28:50 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Mar 11 14:23:38 2015 +0000" }, "message": "Revert \"Revert \"[optimizing] Enable x86 long support.\"\"\n\nThis reverts commit 154552e666347d41d95d7619c6ee56249ff4feca.\n\nChange-Id: Idc726551c249a888b7ff5fde8508ae50e81b2e13\n" }, { "commit": "0e242b5cad3c0b68b72f28c1e5fd3fdd4c05bfd8", "tree": "1446f5a1ec95cf1c641228fd7dc2fecb67962723", "parents": [ "7e5b740cc387645c6b2e0dc8604b1e074c398b4d", "154552e666347d41d95d7619c6ee56249ff4feca" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 06 16:10:31 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Fri Mar 06 16:10:32 2015 +0000" }, "message": "Merge \"Revert \"[optimizing] Enable x86 long support.\"\"" }, { "commit": "154552e666347d41d95d7619c6ee56249ff4feca", "tree": "b8bdb820be33317f23ef1d3e43d13b2b6bfb3ba5", "parents": [ "b4ba354cf8d22b261205494875cc014f18587b50" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 06 16:10:14 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 06 16:10:14 2015 +0000" }, "message": "Revert \"[optimizing] Enable x86 long support.\"\n\nFew libcore failures.\n\nThis reverts commit b4ba354cf8d22b261205494875cc014f18587b50.\n\nChange-Id: I4a28d853e730dff9b69aec9555505803cf2fcd63\n" }, { "commit": "2ed20afc6a1032e9e0cf919cb8d1b2b41e147182", "tree": "169a7bf67d0431922896fe91db3f34a03b786ad7", "parents": [ "b341b70b2418922d9b792cdba96d22bece87c55a" ], "author": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Fri Mar 06 13:55:35 2015 +0000" }, "committer": { "name": "Alexandre Rames", "email": "alexandre.rames@arm.com", "time": "Fri Mar 06 14:15:57 2015 +0000" }, "message": "Opt compiler: Clean the use of `virtual` and `OVERRIDE`.\n\nChange-Id: I806ec522b979334cee8f344fc95e8660c019160a\n" }, { "commit": "b4ba354cf8d22b261205494875cc014f18587b50", "tree": "b6ce1e89f56f4d5adf238188df5b02fd7e2c23ac", "parents": [ "af8db2ea18135588b267fe9a0b2f7af734b906cc" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Mar 05 11:28:58 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Mar 06 11:37:33 2015 +0000" }, "message": "[optimizing] Enable x86 long support.\n\nChange-Id: I9006972a65a1f191c45691104a960366747f9d16\n" }, { "commit": "af8db2ea18135588b267fe9a0b2f7af734b906cc", "tree": "b8bdb820be33317f23ef1d3e43d13b2b6bfb3ba5", "parents": [ "65b50272a15c52d753f68df2468fe1792f2516ea", "5f8741860d465410bfed495dbb5f794590d338da" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Mar 05 11:22:00 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Mar 05 11:22:01 2015 +0000" }, "message": "Merge \"[optimizing] Use callee-save registers for x86\"" }, { "commit": "5f8741860d465410bfed495dbb5f794590d338da", "tree": "cf295594b5b018e96959ddf474e7c8b7374006b5", "parents": [ "c670efd6ba9dbd1166bfd8c805bb6b2df7d4313a" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Mar 04 15:42:45 2015 -0500" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Mar 05 11:08:33 2015 +0000" }, "message": "[optimizing] Use callee-save registers for x86\n\nAdd ESI, EDI, EBP to available registers for non-baseline mode. Ensure\nthat they aren\u0027t used when byte addressible registers are needed.\n\nChange-Id: Ie7130d4084c2ae9cfcd1e47c26eb3e5dcac1ebd6\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "f60c90ba8d1eee6f137a9e1a8a65e4d6bec35d6d", "tree": "c0c41ae585ceb66c237a08e3ee8ce206920e9dee", "parents": [ "ff3ef43f3d0f0986fe23286af028b352277b6e1e" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Mar 04 15:12:59 2015 -0500" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Mar 04 15:17:09 2015 -0500" }, "message": "[optimizing] Improve x86/x86_64 bound check code\n\nDon\u0027t force a constant index into a register just to compare to the\narray size. Allow a constant, and compare the constant to the size.\n\nChange-Id: I1c5732fbd42e63f7eac5c6219a19e9c431c22664\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "8928cab7c1a00f38b9c9a575998093d1b4138805", "tree": "991a48e144df77b9afec226cc3ef8e571c1b4d6b", "parents": [ "49ccb6e6e126bbb7af5e16e608e080fd07968caf" ], "author": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Tue Mar 03 16:15:23 2015 -0800" }, "committer": { "name": "Mingyao Yang", "email": "mingyao@google.com", "time": "Tue Mar 03 16:15:23 2015 -0800" }, "message": "Add a change that should be part of \"enhance gvn for commutative ops.\"\n\nChange-Id: Id1a30afb095b2c7e27a4ef8a1ef7293022c1aaed\n" }, { "commit": "09b8463493aeb6ea2bce05f67d3457d5fcc8a7d9", "tree": "bc1b2eddb27143144c2ca1a7ac4a811cfaf42232", "parents": [ "4ab52e75c782abf19ff9ebff8d19c87ec4ec97b6" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Feb 13 17:48:38 2015 -0500" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Mon Mar 02 11:27:05 2015 -0500" }, "message": "[optimizing compiler] x86 goodness\n\nImplement the x86 version of\nhttps://android-review.googlesource.com/#/c/129560/, which made some\nenhancements to x86_64 code.\n- Use leal to implement 3 operand adds\n- Use testl rather than cmpl to 0 for registers\n- Use leaq for x86_64 for adds with constant in int32_t range\n\nNote:\n- The range and register allocator tests seem quite fragile. I had to\n change ADD_INT_LIT8 to XOR_INT_LIT8 for the register allocator test to\n get the code to run. It seems like this is a bit hard-coded to\n expected code generation sequences. I also changes BuildTwoAdds to\n BuildTwoSubs for the same reason.\n- For the live range test, I just changed the expected output, as the\n Locations were different.\n\nChange-Id: I402f2e95ddc8be4eb0befb3dae1b29feadfa29ab\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "d8ef2e991a1a65f47a26a1eb8c6b34c92b775d6b", "tree": "d3aa88b42db86584724a2566da304aff70be5613", "parents": [ "a48c573d2351177d878e36e003f0cdf4d7f9328f" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Feb 24 16:02:06 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Tue Feb 24 16:04:07 2015 +0000" }, "message": "not-int can also take non-int (byte and short) instructions.\n\nSo we should use the result-type instead if the input type\nfor knowning what instruction to use.\n\nBug: 19454010\nChange-Id: I88782ad27ae8c8e1b7868afede5057d26f14685a\n" }, { "commit": "3173c8a11f7e23a89526e0ac3b21af5150966d74", "tree": "490fb32942acdcd19f02adfd075fdd32f0830a7e", "parents": [ "735969139b162f9d45a3c0e47dc24a8aec63c736" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Feb 23 15:53:39 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Feb 23 15:55:11 2015 +0000" }, "message": "[optimizing] Fix float addition on x86.\n\nChange-Id: Ic39aaae89b8e5184b98001ea67221a3564e9334a\n" }, { "commit": "b1498f67b444c897fa8f1530777ef118e05aa631", "tree": "7ff4709329b0ba752a6111103a76fcea896a3adb", "parents": [ "acf735c13998ad2a175f5a17e7bfce220073279d" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Feb 16 13:13:29 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Fri Feb 20 14:26:08 2015 +0000" }, "message": "Improve type propagation with if-contexts\n\nThis works by adding a new instruction (HBoundType) after each `if (a\ninstanceof ClassA) {}` to bound the type that `a` can take in the True-\ndominated blocks.\n\nChange-Id: Iae6a150b353486d4509b0d9b092164675732b90c\n" }, { "commit": "d6138ef1ea13d07ae555542f8898b30d89e9ac9a", "tree": "a8ffd5fd966512fd280bc1b3214f4e57a9e1805f", "parents": [ "92095533ac28879ddd8b44b559d700527ca12b8a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Feb 18 14:48:53 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Feb 19 14:01:18 2015 +0000" }, "message": "Ensure the graph is correctly typed.\n\nWe used to be forgiving because of HIntConstant(0) also being\nused for null. We now create a special HNullConstant for such uses.\n\nAlso, we need to run the dead phi elimination twice during ssa\nbuilding to ensure the correctness.\n\nChange-Id: If479efa3680d3358800aebb1cca692fa2d94f6e5\n" }, { "commit": "c0572a451944f78397619dec34a38c36c11e9d2a", "tree": "2cc6f3c6f5ad45b4b85fb62627e797fe7e7734e1", "parents": [ "0f2433bfcb02a662fe739e8e2b068abc2958e4c1" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Feb 06 14:35:25 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Feb 06 17:37:57 2015 +0000" }, "message": "Optimize leaf methods.\n\nAvoid suspend checks and stack changes when not needed.\n\nChange-Id: I0fdb31e8c631e99091b818874a558c9aa04b1628\n" }, { "commit": "f4b24f7ea507ff41db39154a1e6a681a582e224a", "tree": "ed70e8d35e91dd93d9dd5130ab88d6453dd4b6f3", "parents": [ "6bc17805d2df2678de186e3b4c3e2f959a48555f", "3e6a3bf797e49b7f449256455c7e522e888687d8" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Feb 04 09:45:14 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Feb 04 09:45:14 2015 +0000" }, "message": "Merge \"ART: Change x86 long param ABI (Quick/JNI/Opt)\"" }, { "commit": "cb1b00aedd94785e7599f18065a0b97b314e64f6", "tree": "fdde101b239c66325243bcc60d3d94f07ff56492", "parents": [ "9544368685b4aa65e746332e602491a3e8e5b247" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 28 14:50:01 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 30 17:43:16 2015 +0000" }, "message": "Use the non access check entrypoint when possible.\n\nChange-Id: I0b53d63141395e26816d5d2ce3fa6a297bb39b54\n" }, { "commit": "3e6a3bf797e49b7f449256455c7e522e888687d8", "tree": "1e574169ff7743729cdfb1b9cf3b217f198a330d", "parents": [ "9544368685b4aa65e746332e602491a3e8e5b247" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Mon Jan 19 14:09:22 2015 -0500" }, "committer": { "name": "Mark P Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Jan 30 13:17:23 2015 +0000" }, "message": "ART: Change x86 long param ABI (Quick/JNI/Opt)\n\nEnsure that we don\u0027t pass a long parameter across the last register\nand the stack: skip the register and allocate it only on the stack.\nThis was requested to simplify the optimizing compiler code\ngeneration for x86.\n\nOptimizing (Baseline) compiler support for x86 longs:\n- Remove QuickParameter from Location, as there are no longer any uses\n of it.\n\nBump oat.h version because we changed an ABI again.\n\nI changed IsParamALong() to return false for argument 0 (this argument).\nI am not sure why it differed from all other tests.\n\nI have not tested on ARM. I followed Nicolas\u0027s suggestions for setting\nthe value of kSplitPairAcrossRegisterAndStack for different\narchitectures.\n\nChange-Id: I2f16b33c1dac58dd4f4f503e9c2309d845f5fb7a\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "c9ff6b112d25657128f9a7251e253b1382b0f1b9", "tree": "dd43d2c53a7d4470c63e21e02b46d07b2ed046c5", "parents": [ "0d5917fedc6f62715759c24f14810733c409ebff", "7c8d009552545e6f1fd6036721e4e42e3fd14697" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 29 11:05:48 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Thu Jan 29 11:05:49 2015 +0000" }, "message": "Merge \"[optimizing compiler] Support x86 hard float ABI\"" }, { "commit": "1cf95287364948689f6a1a320567acd7728e94a3", "tree": "70a8b60c768894d635cf63b0a480baa5073d2bed", "parents": [ "4a50662eeaa0b1a26be66e7584fb765151dabc59" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Dec 12 19:22:03 2014 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 29 10:52:14 2015 +0000" }, "message": "Small optimization for recursive calls: avoid dex cache.\n\nChange-Id: I044757a2f06e535cdc1480c4fc8182b89635baf6\n" }, { "commit": "7c8d009552545e6f1fd6036721e4e42e3fd14697", "tree": "f7290aba6a1dcb008af1388f582d422fe1c07ff6", "parents": [ "763abfd0d803f8169e97d3da944043c2464aac0a" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Mon Jan 26 11:21:33 2015 -0500" }, "committer": { "name": "Mark P Mendell", "email": "mark.p.mendell@intel.com", "time": "Wed Jan 28 00:48:50 2015 +0000" }, "message": "[optimizing compiler] Support x86 hard float ABI\n\nAdd support for the new ABI passing FP parameters in XMM0-XMM3. This\nallows us to optimize for x86 methods that don\u0027t use \u0027long\u0027.\n\nChange-Id: Ic79a24767173451e7d7095ccc2a00b307593a868\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "966c3ae95d3c699ee9fbdbccc1acdaaf02325faf", "tree": "7a9bd5dbfb8b02f8bb7e3387876be0c1f7844063", "parents": [ "85ed6bdd890c08f50c205d7f0604b5a35603b13e" ], "author": { "name": "Mark P Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Jan 27 15:45:27 2015 +0000" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Jan 27 17:00:21 2015 -0500" }, "message": "Revert \"Revert \"ART: Implement X86 hard float (Quick/JNI/Baseline)\"\"\n\nThis reverts commit 949c91fb91f40a4a80b2b492913cf8541008975e.\n\nThis time, don\u0027t clobber EBX before saving it.\n\nRedo some of the macros to make register usage explicit.\n\nChange-Id: I8db8662877cd006816e16a28f42444ab7c36bfef\n" }, { "commit": "949c91fb91f40a4a80b2b492913cf8541008975e", "tree": "45c840d1d6fd0ab71d96cb6c61931f468b3a0adf", "parents": [ "aeb47bb12420e65b4b5f61164e6396ea93734a0a" ], "author": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jan 27 10:48:44 2015 +0000" }, "committer": { "name": "Vladimir Marko", "email": "vmarko@google.com", "time": "Tue Jan 27 13:41:29 2015 +0000" }, "message": "Revert \"ART: Implement X86 hard float (Quick/JNI/Baseline)\"\n\nAnd the 3 Mac build fixes. Fix conflicts in context_x86.* .\n\nThis reverts commits\n 3d2c8e74c27efee58e24ec31441124f3f21384b9 ,\n 34eda1dd66b92a361797c63d57fa19e83c08a1b4 ,\n f601d1954348b71186fa160a0ae6a1f4f1c5aee6 ,\n bc503348a1da573488503cc2819c9e30807bea31 .\n\nBug: 19150481\nChange-Id: I6650ee30a7d261159380fe2119e14379e4dc9970\n" }, { "commit": "3d2c8e74c27efee58e24ec31441124f3f21384b9", "tree": "416a60f70414b026395e3660edeee5e1cb10b6f7", "parents": [ "d834380c94af85b498560f3b5feae21ef7fab1ed" ], "author": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Tue Jan 13 17:32:55 2015 -0500" }, "committer": { "name": "Mark Mendell", "email": "mark.p.mendell@intel.com", "time": "Fri Jan 23 12:53:45 2015 -0500" }, "message": "ART: Implement X86 hard float (Quick/JNI/Baseline)\n\nUse XMM0-XMM3 as parameter registers for float/double on X86. X86_64\nalready uses XMM0-XMM7 for parameters.\n\nChange the \u0027hidden\u0027 argument register from XMM0 to XMM7 to avoid a\nconflict.\n\nAdd support for FPR save/restore in runtime/arch/x86.\n\nMinimal support for Optimizing baseline compiler.\n\nBump the version in runtime/oat.h because this is an ABI change.\n\nChange-Id: Ia6fe150e8488b9e582b0178c0dda65fc81d5a8ba\nSigned-off-by: Mark Mendell \u003cmark.p.mendell@intel.com\u003e\n" }, { "commit": "d97dc40d186aec46bfd318b6a2026a98241d7e9c", "tree": "5cf0257eda25e2722a1adafb9de22690c06a56d8", "parents": [ "c698b78a17043d8898deb817098181595fbe734e" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Thu Jan 22 13:50:01 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Fri Jan 23 09:20:42 2015 +0000" }, "message": "Support callee save floating point registers on x64.\n\n- Share the computation of core_spill_mask and fpu_spill_mask\n between backends.\n- Remove explicit stack overflow check support: we need to adjust\n them and since they are not tested, they will easily bitrot.\n\nChange-Id: I0b619b8de4e1bdb169ea1ae7c6ede8df0d65837a\n" }, { "commit": "988939683c26c0b1c8808fc206add6337319509a", "tree": "876e94428276547a29c27ccf17509a42dfe7cda1", "parents": [ "59add47cabce3735ccd470cd3b5dac8b112e09ab" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 12:32:32 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 18:50:25 2015 +0000" }, "message": "Enable core callee-save on x64.\n\nWill work on other architectures and FP support in other CLs.\n\nChange-Id: I8cef0343eedc7202d206f5217fdf0349035f0e4d\n" }, { "commit": "b6b114c02b8bacd3b5d64e646fdaefa03c069c61", "tree": "cd702f32a9241c94d9e0d12828f3bcb0291b087b", "parents": [ "73d8fe409fbf2cb9665779690660ccc852d60431", "fa93b504b324784dd9a96e28e6e8f3f1b1ac456a" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 17:33:43 2015 +0000" }, "committer": { "name": "Gerrit Code Review", "email": "noreply-gerritcodereview@google.com", "time": "Wed Jan 21 17:33:43 2015 +0000" }, "message": "Merge \"Do not use HNot for creating !bool.\"" }, { "commit": "fa93b504b324784dd9a96e28e6e8f3f1b1ac456a", "tree": "8a3e691268657db75a69c8d644e5a963abee66d6", "parents": [ "1147eeed2ffc82ac9b1405f9fb0a6cbc8560c42b" ], "author": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 15:44:16 2015 +0000" }, "committer": { "name": "Nicolas Geoffray", "email": "ngeoffray@google.com", "time": "Wed Jan 21 17:03:29 2015 +0000" }, "message": "Do not use HNot for creating !bool.\n\nHNot folds to ~, not !.\n\nChange-Id: I681f968449a2ade7110b2f316146ad16ba5da74c\n" }, { "commit": "77520bca97ec44e3758510cebd0f20e3bb4584ea", "tree": "2e3be6fdc182e5cf5ae390019457af5e9c1ed242", "parents": [ "4d2c611bf17ff309abfa152e56c0b98a21ec8787" ], "author": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Mon Jan 12 18:45:46 2015 +0000" }, "committer": { "name": "Calin Juravle", "email": "calin@google.com", "time": "Wed Jan 21 14:26:35 2015 +0000" }, "message": "Record implicit null checks at the actual invoke time.\n\nImplicitNullChecks are recorded only for instructions directly (see NB\nbelow) preceeded by NullChecks in the graph. This way we avoid recording\nredundant safepoints and minimize the code size increase.\n\nNB: ParallalelMoves might be inserted by the register allocator between\nthe NullChecks and their uses. These modify the environment and the\ncorrect action would be to reverse their modification. This will be\naddressed in a follow-up CL.\n\nChange-Id: Ie50006e5a4bd22932dcf11348f5a655d253cd898\n" } ], "next": "24f2dfae084b2382c053f5d688fd6bb26cb8a328" }