)]}' { "log": [ { "commit": "63eaaf6f62c404e6b91b32677918a03609c189e0", "tree": "c0db36ec327e4defd4fcfd01262c0091ff0b6bd0", "parents": [ "e308fc6335f45b83c4362fa1c5297bd813b3bc42" ], "author": { "name": "Michael Bestas", "email": "mkbestas@lineageos.org", "time": "Mon May 27 14:29:39 2024 +0300" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:55:00 2024 +0530" }, "message": "techpack: camera: Nuke unused OIS source\n\nThis code contains float usage, but that is not permitted with\n-mgeneral-regs-only enabled in the kernel.\n\nChange-Id: I55f3d6ad4cea7121825e2b08ae890dce8b939304\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "e308fc6335f45b83c4362fa1c5297bd813b3bc42", "tree": "dd9bb204940b9391b6e40e009251e8e67d01ecd7", "parents": [ "785ec4295b837119e2eddd4ae770a8a8297671a1" ], "author": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Wed Jul 03 21:43:50 2024 +0530" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:55:00 2024 +0530" }, "message": "kernelsu: Backport path_umount from 5.9 kernel\n\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "785ec4295b837119e2eddd4ae770a8a8297671a1", "tree": "df22727d54b00e86d3b680dd0ae042bd224cc759", "parents": [ "889ce7329f3ae8e0504485fb01b59c25c213a45d" ], "author": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Wed Jul 03 21:43:50 2024 +0530" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:55:00 2024 +0530" }, "message": "techpack: display: Fix mixing declarations warning\n\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "889ce7329f3ae8e0504485fb01b59c25c213a45d", "tree": "83842e2066e56b109fa19c1bd647bb2cd2b29863", "parents": [ "8968942735fe257e53ccd736333e76767b867a41" ], "author": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Wed Jul 03 21:42:34 2024 +0530" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:55:00 2024 +0530" }, "message": "techpack: camera: Fix misleading indentation warning\n\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "8968942735fe257e53ccd736333e76767b867a41", "tree": "96e81b0ab13edb4e99e746b1357be7bd6eb171b5", "parents": [ "f721f5603039e7550a9c70321d5210b8dbf5e0f2" ], "author": { "name": "LuK1337", "email": "priv.luk@gmail.com", "time": "Sat Dec 02 23:21:20 2023 +0100" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:55:00 2024 +0530" }, "message": "disp: msm: Skip null flush on Pixelworks Iris 5 devices\n\nIt seems that it breaks touchscreen on boot.\n\nChange-Id: I87b88729dd4af1ffc84c4d4d16435b04bd3b3917\n" }, { "commit": "f721f5603039e7550a9c70321d5210b8dbf5e0f2", "tree": "2ef0528971833ccfe0cfb238a93844bd30b0f618", "parents": [ "8382e35121593ca2771bf7e166d80fb8ec1d7666" ], "author": { "name": "kaderbava", "email": "ksbava7325@gmail.com", "time": "Thu Nov 23 17:40:47 2023 +0200" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:55:00 2024 +0530" }, "message": "selinux: Allow init exec ksud under nosuid\n" }, { "commit": "8382e35121593ca2771bf7e166d80fb8ec1d7666", "tree": "83f1e92ebde07dfc0943a41d1ab4e4e62e15869b", "parents": [ "05d74fc3fedb5164049f8fe1d6e827a3481cae8e" ], "author": { "name": "Lup Gabriel", "email": "gwolf2u.website@gmail.com", "time": "Mon Jun 24 18:30:07 2024 +0300" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:55:00 2024 +0530" }, "message": "drivers: import KernelSU 0.9.5\n\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "05d74fc3fedb5164049f8fe1d6e827a3481cae8e", "tree": "6e1134ca23d0fb736f26cb2f0afe212c30a7263a", "parents": [ "831274b058f3afb7d6f45b49f633c3e4a43cb7a9" ], "author": { "name": "LuK1337", "email": "priv.luk@gmail.com", "time": "Sun Oct 29 13:19:09 2023 +0100" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:55:00 2024 +0530" }, "message": "misc: tri_state_key: Assign vendor id\n\nThis prevents inputflinger from grouping tri key under some unrelated\ninput device.\n\nChange-Id: I6dfc7caf031fac0bff4a7b2f13c324814d297e9b\n" }, { "commit": "831274b058f3afb7d6f45b49f633c3e4a43cb7a9", "tree": "8f60da2cf7ac455e3c213b862d4164ed94591fd9", "parents": [ "aedb1281d83b1bd3081132e2ab489f68b49666e5" ], "author": { "name": "Vaisakh Murali", "email": "mvaisakh@statixos.com", "time": "Wed Mar 29 00:31:19 2023 +0600" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:55:00 2024 +0530" }, "message": "techpack/dataipa: disable regdump for ipa drivers\n\nChange-Id: Ia62129bbc6909e0514f138a6ed51e153181a1603\nSigned-off-by: Vaisakh Murali \u003cmvaisakh@statixos.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "aedb1281d83b1bd3081132e2ab489f68b49666e5", "tree": "2bd06200ae6a588cc6c958068646192d5f1ed9d5", "parents": [ "4b91844752f59a4e3cfb061af089c50763e088a2" ], "author": { "name": "Vaisakh Murali", "email": "mvaisakh@statixos.com", "time": "Wed Mar 29 00:26:27 2023 +0600" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:55:00 2024 +0530" }, "message": "techpack/data: raise qmi send timeout to 6secs\n\nThe request timeout of 1 sec is way too small, and may get send\nanother request before the previous one has even finished.\nIncrease it to 6 seconds to avoid this.\n\nChange-Id: I6007292153ac808e28cfceb2c724a33c4cad4153\nSigned-off-by: Vaisakh Murali \u003cmvaisakh@statixos.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "4b91844752f59a4e3cfb061af089c50763e088a2", "tree": "f83b95015c621eebafc5ba6d78d1db22d643ccd1", "parents": [ "96e4c8dc38b4ed70f3d56928ea14c906aa2128a4" ], "author": { "name": "celtare21", "email": "celtare21@gmail.com", "time": "Tue Dec 29 09:08:16 2020 +0200" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "kernel: alarmtimer: Relax wakelock\n\nChange-Id: I9f944f60db57705f3e35bd710ca72cd85f86d822\nSigned-off-by: celtare21 \u003cceltare21@gmail.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "96e4c8dc38b4ed70f3d56928ea14c906aa2128a4", "tree": "1a35eeb2ded3382d31fc3f90c1711ec5b07cdb2a", "parents": [ "f0c2e8bb777eda0efc65ccf7c16c74108be49a5b" ], "author": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Tue May 16 22:13:32 2023 +0530" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "techpack: audio: tfa98xx: Remove build timestamp injection\n\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "f0c2e8bb777eda0efc65ccf7c16c74108be49a5b", "tree": "3df916a2c651f6eecb1d663bf3ee9980ede4242f", "parents": [ "d3fa3dcea76f80c79c9c5da033aa2a00d6889ae3" ], "author": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Sun May 07 00:27:26 2023 +0530" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "lahaina-qgki_defconfig: Disable DEBUG_STACK_USAGE and DEBUG_MEMORY_INIT\n\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "d3fa3dcea76f80c79c9c5da033aa2a00d6889ae3", "tree": "7924fad862ecb50eef991c4eb4fd629d79d5e013", "parents": [ "b76a4a1c487ee07b5543d4985d7fb5038409201e" ], "author": { "name": "Gustavo A. R. Silva", "email": "gustavo@embeddedor.com", "time": "Mon Mar 23 17:23:01 2020 -0500" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "energy_model.h: Replace zero-length array with flexible-array member\n\nThe current codebase makes use of the zero-length array language\nextension to the C90 standard, but the preferred mechanism to declare\nvariable-length types such as these ones is a flexible array member[1][2],\nintroduced in C99:\n\nstruct foo {\n int stuff;\n struct boo array[];\n};\n\nBy making use of the mechanism above, we will get a compiler warning\nin case the flexible array does not occur last in the structure, which\nwill help us prevent some kind of undefined behavior bugs from being\ninadvertently introduced[3] to the codebase from now on.\n\nAlso, notice that, dynamic memory allocations won\u0027t be affected by\nthis change:\n\n\"Flexible array members have incomplete type, and so the sizeof operator\nmay not be applied. As a quirk of the original implementation of\nzero-length arrays, sizeof evaluates to zero.\"[1]\n\nThis issue was found with the help of Coccinelle.\n\n[1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html\n[2] https://github.com/KSPP/linux/issues/21\n[3] commit 76497732932f (\"cxgb3/l2t: Fix undefined behaviour\")\n\nSigned-off-by: Gustavo A. R. Silva \u003cgustavo@embeddedor.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "b76a4a1c487ee07b5543d4985d7fb5038409201e", "tree": "a89d96c83ee93a2490a43bc9ac555c255a13221b", "parents": [ "14f36637ceb91f1dfaa94b0fdc08116b92419220" ], "author": { "name": "Tetsuo Handa", "email": "penguin-kernel@I-love.SAKURA.ne.jp", "time": "Thu Apr 01 14:58:23 2021 +0900" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "kernel: Initialize cpumask before parsing\n\nKMSAN complains that new_value at cpumask_parse_user() from\nwrite_irq_affinity() from irq_affinity_proc_write() is uninitialized.\n\n [ 148.133411][ T5509] \u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n [ 148.135383][ T5509] BUG: KMSAN: uninit-value in find_next_bit+0x325/0x340\n [ 148.137819][ T5509]\n [ 148.138448][ T5509] Local variable ----new_value.i@irq_affinity_proc_write created at:\n [ 148.140768][ T5509] irq_affinity_proc_write+0xc3/0x3d0\n [ 148.142298][ T5509] irq_affinity_proc_write+0xc3/0x3d0\n [ 148.143823][ T5509] \u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\u003d\n\nSince bitmap_parse() from cpumask_parse_user() calls find_next_bit(),\nany alloc_cpumask_var() + cpumask_parse_user() sequence has possibility\nthat find_next_bit() accesses uninitialized cpu mask variable. Fix this\nproblem by replacing alloc_cpumask_var() with zalloc_cpumask_var().\n\nSigned-off-by: Tetsuo Handa \u003cpenguin-kernel@I-love.SAKURA.ne.jp\u003e\nSigned-off-by: Thomas Gleixner \u003ctglx@linutronix.de\u003e\nAcked-by: Steven Rostedt (VMware) \u003crostedt@goodmis.org\u003e\nLink: https://lore.kernel.org/r/20210401055823.3929-1-penguin-kernel@I-love.SAKURA.ne.jp\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "14f36637ceb91f1dfaa94b0fdc08116b92419220", "tree": "81b7217321514682a0924087e183b3a6fa94ef7f", "parents": [ "e2e166c7867b56a8e50a7e7ae630f5f709edcceb" ], "author": { "name": "Rob Herring", "email": "robh@kernel.org", "time": "Wed Dec 11 17:23:45 2019 -0600" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "drivers: of: Rework and simplify phandle cache to use a fixed size\n\nThe phandle cache was added to speed up of_find_node_by_phandle() by\navoiding walking the whole DT to find a matching phandle. The\nimplementation has several shortcomings:\n\n - The cache is designed to work on a linear set of phandle values.\n This is true for dtc generated DTs, but not for other cases such as\n Power.\n - The cache isn\u0027t enabled until of_core_init() and a typical system\n may see hundreds of calls to of_find_node_by_phandle() before that\n point.\n - The cache is freed and re-allocated when the number of phandles\n changes.\n - It takes a raw spinlock around a memory allocation which breaks on\n RT.\n\nChange the implementation to a fixed size and use hash_32() as the\ncache index. This greatly simplifies the implementation. It avoids\nthe need for any re-alloc of the cache and taking a reference on nodes\nin the cache. We only have a single source of removing cache entries\nwhich is of_detach_node().\n\nUsing hash_32() removes any assumption on phandle values improving\nthe hit rate for non-linear phandle values. The effect on linear values\nusing hash_32() is about a 10% collision. The chances of thrashing on\ncolliding values seems to be low.\n\nTo compare performance, I used a RK3399 board which is a pretty typical\nsystem. I found that just measuring boot time as done previously is\nnoisy and may be impacted by other things. Also bringing up secondary\ncores causes some issues with measuring, so I booted with \u0027nr_cpus\u003d1\u0027.\nWith no caching, calls to of_find_node_by_phandle() take about 20124 us\nfor 1248 calls. There\u0027s an additional 288 calls before time keeping is\nup. Using the average time per hit/miss with the cache, we can calculate\nthese calls to take 690 us (277 hit / 11 miss) with a 128 entry cache\nand 13319 us with no cache or an uninitialized cache.\n\nComparing the 3 implementations the time spent in\nof_find_node_by_phandle() is:\n\nno cache: 20124 us (+ 13319 us)\n128 entry cache: 5134 us (+ 690 us)\ncurrent cache: 819 us (+ 13319 us)\n\nWe could move the allocation of the cache earlier to improve the\ncurrent cache, but that just further complicates the situation as it\nneeds to be after slab is up, so we can\u0027t do it when unflattening (which\nuses memblock).\n\nReported-by: Sebastian Andrzej Siewior \u003cbigeasy@linutronix.de\u003e\nCc: Michael Ellerman \u003cmpe@ellerman.id.au\u003e\nCc: Segher Boessenkool \u003csegher@kernel.crashing.org\u003e\nCc: Frank Rowand \u003cfrowand.list@gmail.com\u003e\nSigned-off-by: Rob Herring \u003crobh@kernel.org\u003e\nLink: https://lkml.kernel.org/r/20191211232345.24810-1-robh@kernel.org\nSigned-off-by: Sebastian Andrzej Siewior \u003cbigeasy@linutronix.de\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "e2e166c7867b56a8e50a7e7ae630f5f709edcceb", "tree": "f1cf378c1cb1aa11fe5b2f5f07f382a2b877c191", "parents": [ "97687802b8f48a0997eeec1f4df907e6d59558af" ], "author": { "name": "Juhyung Park", "email": "qkrwngud825@gmail.com", "time": "Thu Jan 27 14:41:16 2022 +0900" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "drivers: of: set *lenp to zero on errors\n\nDuring clang-13 bring-up, boot failure was encountered due to\nmsm_pcie_probe() failure.\n\nIt turned out that msm_pcie_probe() had a local variable `int size`\nuninitialized and the following code was triggered:\n\n```\n\tof_get_property(pdev-\u003edev.of_node, \"qcom,filtered-bdfs\", \u0026size);\n\tif (size) {\n\t\tpcie_dev-\u003efiltered_bdfs \u003d devm_kzalloc(\u0026pdev-\u003edev, size,\n\t\t\t\t\t\t GFP_KERNEL);\n\t\tif (!pcie_dev-\u003efiltered_bdfs)\n\t\t\treturn -ENOMEM; // Triggered!\n```\n\nWe can simply initialize the variable there, but unfortunately it turns out\nthat a lot of Qualcomm\u0027s code have this semantic errors.\n\nFix this from __of_find_property() directly by setting *lenp (\u0026size from the\ncode above) when it errors out (i.e., not found).\n\nSigned-off-by: Juhyung Park \u003cqkrwngud825@gmail.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "97687802b8f48a0997eeec1f4df907e6d59558af", "tree": "226d85e2787e02abb2f3f0bf391ef4d600fae3ac", "parents": [ "cfa869eaa8ca40b0d38dedd31fb6fc85389065a3" ], "author": { "name": "Sultan Alsawaf", "email": "sultan@kerneltoast.com", "time": "Mon Jan 11 23:29:32 2021 -0800" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "drivers: bus: mhi: Fix parentheses warning for bitwise operations\n\nChange-Id: If7c94aee007b21ffe058cf972a33a9c7195c85c0\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "cfa869eaa8ca40b0d38dedd31fb6fc85389065a3", "tree": "8674cd220849dbddd8ce78916d2adda1d940f17a", "parents": [ "c9f02d8d0db10e1d6552fe054a52465b5008799f" ], "author": { "name": "Divyanshu-Modi", "email": "divyan.m05@gmail.com", "time": "Sat Apr 02 10:41:19 2022 +0530" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "block: neuron_block_server: silence useless logger\n\n There\u0027s no entry for this node in it\u0027s yaml as well\n So, don\u0027t spit in my log\n\nChange-Id: I2d1fb61a76ff688b1b75bc57d8538cd3859c9ed6\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "c9f02d8d0db10e1d6552fe054a52465b5008799f", "tree": "f5382995788544307d2e9effd6e98d21fced0cb7", "parents": [ "b6b2972165e3a3029ccdd256aabd0889c40a02ba" ], "author": { "name": "Divyanshu-Modi", "email": "divyan.m05@gmail.com", "time": "Fri Apr 01 23:39:51 2022 +0530" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "arm64: cpufeature: Silence SANITY CHECK logspam\n\nChange-Id: If2fd0dcfed76b59a69fbd6951014cbbddf170b2e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "b6b2972165e3a3029ccdd256aabd0889c40a02ba", "tree": "8817040ff034f88ce5766a97c07ebdf955b5a32c", "parents": [ "69727ec233954a2cca54a92e9ae703dfbba452ce" ], "author": { "name": "Danny Lin", "email": "danny@kdrag0n.dev", "time": "Sun Nov 01 16:58:55 2020 -0800" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "Arm64: kernel: Suppress overly verbose log spam\n\nIt\u0027s hard to see anything that\u0027s actually useful with so much verbose\nspam in the log buffer.\n\nChange-Id: I0283cbc401d0014463fac436c8fd123d0a9fe565\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "69727ec233954a2cca54a92e9ae703dfbba452ce", "tree": "952a05b87bf0767a2cddf49eeb5734871ce62152", "parents": [ "ee3554ee78b922870b9bf17681e0f583bf0f8525" ], "author": { "name": "Sultan Alsawaf", "email": "sultan@kerneltoast.com", "time": "Wed Jan 06 21:00:31 2021 -0800" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "dma-buf/sync_file: Speed up ioctl by omitting debug names\n\nA lot of CPU time is wasted on allocating, populating, and copying\ndebug names back and forth with userspace when they\u0027re not actually\nneeded. We can\u0027t just remove the name buffers from the various sync data\nstructures though because we must preserve ABI compatibility with\nuserspace, but instead we can just pretend the name fields of the\nuser-shared structs aren\u0027t there. This massively reduces the sizes of\nmemory allocated for these data structures and the amount of data passed\nbetween userspace, as well as eliminates a kzalloc() entirely from\nsync_file_ioctl_fence_info(), thus improving graphics performance.\n\nChange-Id: Ibfdf22c77becb26ce453e811f1a4fd8d050b2ca0\nSigned-off-by: Sultan Alsawaf \u003csultan@kerneltoast.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "ee3554ee78b922870b9bf17681e0f583bf0f8525", "tree": "a1bcce813d74183a18415c451984db67b9b62260", "parents": [ "145c4ab9cc69ff4d97fb7132b2ab39d1d8345270" ], "author": { "name": "Cosmin Tanislav", "email": "demonsingur@gmail.com", "time": "Mon Oct 04 10:29:20 2021 +0300" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "arm64: dts: lahaina: remove memory offline support\n\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "145c4ab9cc69ff4d97fb7132b2ab39d1d8345270", "tree": "4bf2c852ce78c90db8844390649c961f2921b658", "parents": [ "865607354ea84d06d8461a14d8574cf58dff54a3" ], "author": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Apr 24 01:42:49 2023 +0530" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "lahaina-qgki_defconfig: Enable UFS Host Performance Booster support\n\n* Improves sequential writes from 490 MB/s to 515 MB/s.\n\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "865607354ea84d06d8461a14d8574cf58dff54a3", "tree": "f6b0de289526f2657162b68c6f7199e4e9221ed0", "parents": [ "e0a62ab17ff1003adc05519ff9121daf372aa6b8" ], "author": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Sun Apr 23 23:01:43 2023 +0530" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "Revert \"HACK: binder: Disable freeze related ioctls\"\n\nThis reverts commit 1c1f642a117305ecb1db1707412d43f140777c7e.\n" }, { "commit": "e0a62ab17ff1003adc05519ff9121daf372aa6b8", "tree": "9d2c8c9a198cee5fff66af88d60bff837fb85ae7", "parents": [ "581c38921f1af0b4b75767a1ad21feb0a5e23f5c" ], "author": { "name": "Juhyung Park", "email": "qkrwngud825@gmail.com", "time": "Fri Sep 17 19:10:02 2021 +0900" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "time: move frequently used functions to headers and declare them inline\n\nThose function are frequently used in various places and declaring them inline\ncan reduce overheads.\n\nSigned-off-by: Juhyung Park \u003cqkrwngud825@gmail.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "581c38921f1af0b4b75767a1ad21feb0a5e23f5c", "tree": "c684296215befccb6843ae719323f1e85a4624af", "parents": [ "47b82407d5968521edff4a81e8916f3f5156feb3" ], "author": { "name": "Park Ju Hyung", "email": "qkrwngud825@gmail.com", "time": "Sun Oct 28 09:28:56 2018 +0900" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "printk: disable console suspend by default\n\nSigned-off-by: Park Ju Hyung \u003cqkrwngud825@gmail.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "47b82407d5968521edff4a81e8916f3f5156feb3", "tree": "ef90f8bbf1ba3ef89835ce1f78f4865f2dfbc7a3", "parents": [ "ebc2de449befcb8ccfee7d65f8b1f115250e41c6" ], "author": { "name": "Park Ju Hyung", "email": "qkrwngud825@gmail.com", "time": "Wed Mar 18 20:23:03 2020 +0900" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "kthread: use buffer from the stack space\n\nstruct kthread_create_info is small enough to fit perfectly under\nthe stack space.\n\nSigned-off-by: Park Ju Hyung \u003cqkrwngud825@gmail.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "ebc2de449befcb8ccfee7d65f8b1f115250e41c6", "tree": "430bff34f2dbc524272113f1170d50cf15cdef82", "parents": [ "d9b7944142e47bf5c60675eef11400c26feba632" ], "author": { "name": "Park Ju Hyung", "email": "qkrwngud825@gmail.com", "time": "Wed Mar 18 19:18:19 2020 +0900" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "printk: use buffer from the stack space\n\nAndroid uses way too much printk.\n\nAvoid allocating heap memory for lower overheads.\n\nSigned-off-by: Park Ju Hyung \u003cqkrwngud825@gmail.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "d9b7944142e47bf5c60675eef11400c26feba632", "tree": "d33935060156446776bdcdd9fdb9e8b7908cb393", "parents": [ "a7d50a06d6b5e233de128e489bd44e94d8829332" ], "author": { "name": "Park Ju Hyung", "email": "qkrwngud825@gmail.com", "time": "Tue Mar 12 14:14:42 2019 +0900" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "msm_geni_serial: featurize console\n\nGuard with macros to skip compilation altogether\n\nSigned-off-by: Park Ju Hyung \u003cqkrwngud825@gmail.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "a7d50a06d6b5e233de128e489bd44e94d8829332", "tree": "75ff6c97285d2c63aaff109d0e9e0e53c9c52bfb", "parents": [ "72562b0a78157761bd12eb6f58b7d566b22abdea" ], "author": { "name": "Vaisakh Murali", "email": "mvaisakh@statixos.com", "time": "Mon Aug 01 15:21:53 2022 +0000" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "techpack/audio: tfa: Queue delayed work on power efficient wq\n\nSigned-off-by: Vaisakh Murali \u003cmvaisakh@statixos.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "72562b0a78157761bd12eb6f58b7d566b22abdea", "tree": "00007acdd2844b2de52399a9152d9ecafbf67654", "parents": [ "1e5e8658857796bb409c9aa8fae33d1766c7e39f" ], "author": { "name": "Vaisakh Murali", "email": "mvaisakh@statixos.com", "time": "Wed Mar 01 18:20:05 2023 +0000" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "cnss2: switch to late suspend irq instead of noirq suspend\n\nnoirq suspend irq leads to callback fails, waking up the CPU from\nsuspend.\n\nChange-Id: Icf294227ea184816cfe6db20c027ac9354756dc2\nCo-authored-by: atndko \u003cz1281552865@gmail.com\u003e\nSigned-off-by: Vaisakh Murali \u003cmvaisakh@statixos.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "1e5e8658857796bb409c9aa8fae33d1766c7e39f", "tree": "3dd1f22cb671fe08b26e3e88cf6ac538c567300f", "parents": [ "7a1cc05b0d5a7e889d2c5237311019175d115992" ], "author": { "name": "Vaisakh Murali", "email": "mvaisakh@statixos.com", "time": "Fri Mar 17 18:58:24 2023 +0600" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:59 2024 +0530" }, "message": "techpack/audio: bolero: queue work on power efficient freezable wq\n\nChange-Id: Ibfd36f8579cce2ecb45c0b545d226486f4e9e24a\nSigned-off-by: Vaisakh Murali \u003cmvaisakh@statixos.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "7a1cc05b0d5a7e889d2c5237311019175d115992", "tree": "65f377d8bfa527b897ef2fe9b1b30182a4a7fece", "parents": [ "da4482dfa4f9611f8d68d4637345d619b66b2474" ], "author": { "name": "Vaisakh Murali", "email": "mvaisakh@statixos.com", "time": "Sun Mar 26 17:39:59 2023 +0900" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "lahaina-qgki: set QRTR wake timeout to 500ms\n\nChange-Id: Iba7a17ad913c3174257d7e9c7a876acb4c605e40\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "da4482dfa4f9611f8d68d4637345d619b66b2474", "tree": "f985e987a12f9c063c3d6b8ebcd828c86eb0714e", "parents": [ "6d35f6b4e5b8b43e64d74c57645f9df0565c379b" ], "author": { "name": "wenchangliu", "email": "wenchangliu@google.com", "time": "Fri Feb 07 15:22:22 2020 +0800" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "msm: vidc: disable decode batching feature\n\nThis feature implemented for power optimization\nwith OMX but not well compliant with Codec 2.0.\nDisable it to unblock VT frame drop issue.\n\nBug: 149071324\nTest: VT frame rate test\nChange-Id: I187958f4da10d5936c0f0fbd5060301e55ac7f29\nSigned-off-by: Wen Chang Liu \u003cwenchangliu@google.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "6d35f6b4e5b8b43e64d74c57645f9df0565c379b", "tree": "8764b5674040d6753cf6e2a53a2d53f599e0f0f4", "parents": [ "515e9909da2cc48ce7406aedb86e5fd0ac9af342" ], "author": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Thu Mar 30 09:01:50 2023 +0530" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "arm64: configs: Use 58 ms as GPU idle timeout\n\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "515e9909da2cc48ce7406aedb86e5fd0ac9af342", "tree": "449b3c3a80752002481eddccf1f355f1ac49bcdf", "parents": [ "b4ecc8cee50f624c37198cb70a510422d06ca282" ], "author": { "name": "Adithya R", "email": "gh0strider.2k18.reborn@gmail.com", "time": "Sun Mar 26 17:22:44 2023 +0900" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "drivers: gpu: Force GPU idle timeout to 58 ms\n\nThis matches the ULPS timeout used in msm_drm, which is defined as 58 ms\nby IDLE_POWERCOLLAPSE_DURATION. No need to keep the GPU running after\nthe display enters a low-power state.\n\nChange-Id: Ic9271e076d33c4b5625f6ad3164af4cd755d6d4c\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "b4ecc8cee50f624c37198cb70a510422d06ca282", "tree": "9db69c6e1cb813499e1d62995725292c8cd2f8bf", "parents": [ "6473140ee28367df25bb8c451b24efcda44e0625" ], "author": { "name": "Danny Lin", "email": "danny@kdrag0n.dev", "time": "Tue Nov 24 20:18:27 2020 -0800" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "fs: f2fs: Demote GC thread to idle scheduler class\n\nWe don\u0027t want the background GC work causing UI jitter should it ever\ncollide with periods of user activity.\n\nSigned-off-by: Danny Lin \u003cdanny@kdrag0n.dev\u003e\nChange-Id: I91cc3b7e7546f601c42a629b0c305669fbcdd383\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "6473140ee28367df25bb8c451b24efcda44e0625", "tree": "46e5c6fcdc9d482a11534368763bcb12c5654b09", "parents": [ "8c4f5a5dbb4c6264230a716723ad9e451a64287b" ], "author": { "name": "Wei Wang", "email": "wvw@google.com", "time": "Fri Sep 20 23:59:39 2019 -0700" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "ANDROID: sched: fair: balance for single core cluster\n\nAndroid will unset SD_LOAD_BALANCE for single core cluster domain and\nfor some product it is true to have a single core cluster and the MC\ndomain thus lacks the SD_LOAD_BALANCE flag. This will cause\nselect_task_rq_fair logic break and the task will spin forever\nin that core.\n\nFixes: 00bbe7d605a9 \"ANDROID: sched: EAS \u0026 \u0027single cpu per cluster\u0027/cpu hotplug interoperability\"\n\nBug: 141334320\nTest: boot and see task on core7 scheduled correctly\nSigned-off-by: Wei Wang \u003cwvw@google.com\u003e\nChange-Id: I08917836d8b99116353bfec5791af69d916583fe\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "8c4f5a5dbb4c6264230a716723ad9e451a64287b", "tree": "abd78301f5e368c065a6902249892d094bb8a31e", "parents": [ "ddbf5c89bbdcd36e6a2fd917ff9c5da1e098b874" ], "author": { "name": "Vaisakh Murali", "email": "mvaisakh@statixos.com", "time": "Fri Mar 17 00:04:34 2023 +0600" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "drivers/input: oplus-ts-v2: cleanup mtk code\n\nunused on qcom driver\n\nChange-Id: I14de4b8aa98f88afd38a21101f20e82078397096\nSigned-off-by: Vaisakh Murali \u003cmvaisakh@statixos.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "ddbf5c89bbdcd36e6a2fd917ff9c5da1e098b874", "tree": "8fdbc2b17bc1ced58d9eeb79dfa1ffab9c14f31e", "parents": [ "9793c044bfeaf3a8a522c1e2701a91515f31f82c" ], "author": { "name": "Vaisakh Murali", "email": "mvaisakh@statixos.com", "time": "Sat Feb 25 23:06:31 2023 +0600" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "drivers/input: oplus-ts-v2: refactor fb_notifier_callback\n\nRely on switch case instead of the massive if-else ladder.\n\nChange-Id: I6e6876dfa364f292de1abcac8999df789924c6e9\nCo-authored-by: John Galt \u003cjohngaltfirstrun@gmail.com\u003e\nSigned-off-by: Vaisakh Murali \u003cmvaisakh@statixos.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "9793c044bfeaf3a8a522c1e2701a91515f31f82c", "tree": "2b1f61b273d3ee7cd68e0888bf7e27c265697a1b", "parents": [ "65fb44ee976818d55ae8c5bb14392a31d749bcf8" ], "author": { "name": "Vaisakh Murali", "email": "mvaisakh@statixos.com", "time": "Sat Feb 25 22:43:45 2023 +0600" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "drivers/input: oplus-ts-v2: clean up fb code\n\nThis kernel doesn\u0027t rely on FB support anyway. We use newer msm drm\nAPI.\n\nChange-Id: Ied2bd742a373b84265336033ee7ddd653a509532\nSigned-off-by: Vaisakh Murali \u003cmvaisakh@statixos.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "65fb44ee976818d55ae8c5bb14392a31d749bcf8", "tree": "6d08c383ef8c2bb95daccc1d5597ee8976ea755d", "parents": [ "37d3ab4151aec5ca8ec8b97b4773f3c0b325614b" ], "author": { "name": "Juhyung Park", "email": "qkrwngud825@gmail.com", "time": "Fri Sep 17 21:34:36 2021 +0900" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "adreno: disable snapshot, coresight and trace\n\nChange-Id: Ida62b2d078ce0cd4139450bd3f2d7168ca2230f7\nSigned-off-by: Juhyung Park \u003cqkrwngud825@gmail.com\u003e\nSigned-off-by: rk134 \u003cme@rk134.cf\u003e\nSigned-off-by: Vaisakh Murali \u003cmvaisakh@statixos.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "37d3ab4151aec5ca8ec8b97b4773f3c0b325614b", "tree": "f81db2013d02613cc965a76e5e33df9d9e92f954", "parents": [ "8838f0c00796caf7937b404cc4b6fd66f4fce89f" ], "author": { "name": "Juhyung Park", "email": "qkrwngud825@gmail.com", "time": "Fri Sep 17 19:51:51 2021 +0900" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "adreno: hardcode for a660 \u0026 a642L\n\nSigned-off-by: Juhyung Park \u003cqkrwngud825@gmail.com\u003e\nSigned-off-by: rk134 \u003cme@rk134.cf\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "8838f0c00796caf7937b404cc4b6fd66f4fce89f", "tree": "03cabf731fdd91a1bd8f7ae8eef25267ac5ff5e4", "parents": [ "1765f58ad3abde251bb56ee43046bdb16a280b20" ], "author": { "name": "wangwang1", "email": "wangwang1@lenovo.com", "time": "Tue Oct 12 18:31:09 2021 +0800" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "kernel:cma:increase contiguous area size to 20MB\n\ncnss firmware allocatation uses DMA COHERENT POOL which often occasionary\nused by some other hardware components at runtime, the competition could\ncause cma allocation failure. Enlarge this area to 20MB from 16MB to mitigate\nthe failure\n\nChange-Id: Ic3ae05edf21000857d49d99dfcaa68b861536e54\nSigned-off-by: wangwang1 \u003cwangwang1@mt.com\u003e\nReviewed-on: https://gerrit.mot.com/2088268\nSLTApproved: Slta Waiver\nSME-Granted: SME Approvals Granted\nTested-by: Jira Key\nReviewed-by: Xiangpo Zhao \u003czhaoxp3@motorola.com\u003e\nSubmit-Approved: Jira Key\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "1765f58ad3abde251bb56ee43046bdb16a280b20", "tree": "1d93a24cfb8ea44606e0f9e301b1ea688fdea918", "parents": [ "3bfdbf0d73321c552d700b719f3f41db10c84437" ], "author": { "name": "zhangpei5", "email": "zhangpei5@lenovo.com", "time": "Sat Sep 10 10:47:15 2022 +0700" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "ARM64: configs: Disable config cleancache\n\nChange-Id: I5ca251f9cf03409cb971cc91e0628154c8673931\nReviewed-on: https://gerrit.mot.com/2037419\nSLTApproved: Slta Waiver\nSME-Granted: SME Approvals Granted\nTested-by: Jira Key\nReviewed-by: Xiangpo Zhao \u003czhaoxp3@motorola.com\u003e\nSubmit-Approved: Jira Key\nSigned-off-by: zhangpei5 \u003czhangpei5@lenovo.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "3bfdbf0d73321c552d700b719f3f41db10c84437", "tree": "dc5abb3b591d35b579be7b39d5aa5502652bbbb4", "parents": [ "b34133c9f83652fd9670e398f9c0fe6defe99a98" ], "author": { "name": "huangzq2", "email": "huangzq2@motorola.com", "time": "Wed Sep 01 21:45:05 2021 +0800" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "disable watermark boost as it is not working fine\n\nPropagated from (CR)\n\nChange-Id: Iabf50b932044187d170f63f104522731e260008d\nSigned-off-by: huangzq2 \u003chuangzq2@motorola.com\u003e\nReviewed-on: https://gerrit.mot.com/2057054\nSME-Granted: SME Approvals Granted\nSLTApproved: Slta Waiver\nTested-by: Jira Key\nReviewed-by: Wang Wang \u003cwangwang1@mt.com\u003e\nSubmit-Approved: Jira Key\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "b34133c9f83652fd9670e398f9c0fe6defe99a98", "tree": "fdb9629d3417704a2193072684ed0434055b76ee", "parents": [ "cf9c53117b8494645de444ccd1ec3f79cd7c141f" ], "author": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Sat Mar 11 01:28:37 2023 +0530" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "arm64: configs: Disable SPLIT_RSS_COUNTING since HAVE_USERSPACE_LOW_MEMORY_KILLER enabled\n\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "cf9c53117b8494645de444ccd1ec3f79cd7c141f", "tree": "4b9256c7c97be5e9d37bcc18ab76323f6274ade7", "parents": [ "7816c4625b457adce072628f89b57709d374b708" ], "author": { "name": "huangzq2", "email": "huangzq2@motorola.com", "time": "Wed Jul 08 13:29:04 2020 +0800" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "disable SPLIT_RSS_COUNTING to fix zero RSS issue\n\nrss in statm sometimes is zero value which will affect lmk kill\nas it depends on the rss size of each process in lmkd.\n\nChange-Id: Iee0bdf2534fee660e64d8e8221c4dc571e13921e\nSigned-off-by: huangzq2 \u003chuangzq2@motorola.com\u003e\nReviewed-on: https://gerrit.mot.com/1668699\nSLTApproved: Slta Waiver\nSME-Granted: SME Approvals Granted\nTested-by: Jira Key\nReviewed-by: Xiangpo Zhao \u003czhaoxp3@motorola.com\u003e\nSubmit-Approved: Jira Key\nReviewed-by: Bingqian Yang \u003cyangbq1@mt.com\u003e\n(cherry picked from commit 09b4d0ed5f4710c7ee6f263a2faca67846565256)\nReviewed-on: https://gerrit.mot.com/1673149\nReviewed-by: Zhenxin Xi \u003cxizx@motorola.com\u003e\nReviewed-on: https://gerrit.mot.com/1944201\nReviewed-by: Jichao Zou \u003czoujc@motorola.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "7816c4625b457adce072628f89b57709d374b708", "tree": "bb44916f963b652d4a8b115ae777d4a800f470b7", "parents": [ "b0102188fc239f5c6f515ca7f9d98e5a69d2ec9b" ], "author": { "name": "engstk", "email": "eng.stk@sapo.pt", "time": "Mon Mar 06 16:18:19 2023 +0000" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "make: Remove op build logspam\n\nSigned-off-by: engstk \u003ceng.stk@sapo.pt\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "b0102188fc239f5c6f515ca7f9d98e5a69d2ec9b", "tree": "c8158d3684782b7aa774507172e465c5f9c35b24", "parents": [ "0daa0560b8624e83d1b29874173f9df6243568e7" ], "author": { "name": "Kristof Petho", "email": "kristof.petho@gmail.com", "time": "Fri Jul 09 17:39:23 2021 +0200" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "Revert \"ANDROID: kbuild: limit LTO inlining\"\n\nThis reverts commit 1a387ad21d08ea23b9ad9312d02221d01b6654be.\n\nThis increases syscall speed by ~5%.\n\nChange-Id: Ie374c0e30f94ff499c25c57a033c6538ec9b92df\nSigned-off-by: chandu078 \u003cchandudyavanapelli03@gmail.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "0daa0560b8624e83d1b29874173f9df6243568e7", "tree": "43c196d8c2c2cb95f555676fc07a101b04caadcf", "parents": [ "f0af8865721475eafabe759152b3db8dfb908fc1" ], "author": { "name": "jabashque", "email": "jabashque@gmail.com", "time": "Fri Feb 10 19:20:56 2023 +0100" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "arm64: dts: Don\u0027t blank screen as part of LP1 cmd\n\nWe send the LP1 command as part of entering Always-On Display mode, but\nwe don\u0027t want that command to blank the screen. After all, the point of\nAoD mode is to keep the screen on to display the time, notifications,\netc.\n\nSigned-off-by: chandu078 \u003cchandudyavanapelli03@gmail.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "f0af8865721475eafabe759152b3db8dfb908fc1", "tree": "bd74daee1d42701631378ded5d36638859b126db", "parents": [ "d8aa2292094694a10d0a3fe6c55c66d4c6a6a324" ], "author": { "name": "Divyanshu-Modi", "email": "divyan.m05@gmail.com", "time": "Wed Sep 28 23:33:56 2022 +0530" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "kernel: sched: Import SONY changes\n\n* From sony sagami 61.1.A.9.207 kernel copyleft\n\nChange-Id: I81389fd39f2017ccbb1a02b462e4932a0937cc81\nSigned-off-by: Divyanshu-Modi \u003cdivyan.m05@gmail.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "d8aa2292094694a10d0a3fe6c55c66d4c6a6a324", "tree": "efa760448fc482674c29086081b50a4e5ab6715d", "parents": [ "e46221d8f0dc5f12c1c6d15ea5a3793ef513e1bd" ], "author": { "name": "jabashque", "email": "jabashque@gmail.com", "time": "Fri Jan 27 17:10:11 2023 +0900" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "techpack: display: oplus: Set AoD low light mode as default\n\nThe brightness level of AoD high mode is a bit too much for an always-on\ndisplay. Default to low mode instead to help reduce screen burn-in.\n\nChange-Id: I05d923cea4eb7865179cf9c886c443dbddd5cca1\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "e46221d8f0dc5f12c1c6d15ea5a3793ef513e1bd", "tree": "aa234d9d4de53116f54afe2871dea7039c6ad5b2", "parents": [ "4990a7452d2861c7186746ac93c951e941fde74f" ], "author": { "name": "jabashque", "email": "jabashque@gmail.com", "time": "Fri Jan 27 17:09:44 2023 +0900" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "techpack: display: Don\u0027t skip LP1 cmd for AoD with fingerprint_mode on\n\nOPlus added extra code to skip sending the LP1/LP2 command if the\nfingerprint sensor is active. They probably have other changes they made\nin their fork of Android that requires this, but for us, this causes our\npanels to not actually enter LP1 mode at all when Ambient Display is\nenabled.\n\nDelete special case handling for this so that we can actually use LP1\nmode properly.\n\nChange-Id: I990aaed3980654de4d153661a721cc303dcb3ea6\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "4990a7452d2861c7186746ac93c951e941fde74f", "tree": "5f83457ad69b3245f3fce92e2214a83da280e4e9", "parents": [ "201be83e7b126f44b3aee7b3ef6dbb22ccecbe09" ], "author": { "name": "jabashque", "email": "jabashque@gmail.com", "time": "Fri Jan 27 16:57:22 2023 +0900" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:58 2024 +0530" }, "message": "techpack: display: Make dimlayer transparent in LP1/LP2 power mode\n\nTo account for cases where dimlayer_hbm can be enabled while entering\nAoD (and thus disabling Hight Brightness Mode), OPlus added code to make\nthe dimlayer fully transparent if the panel was in LP1 or LP2 mode and\nthe AoD layer is present. However, this is specific to OxygenOS; on\nAOSP, we don\u0027t have that AoD layer, so this doesn\u0027t make the dimlayer\ntransparent for us.\n\nInstead, let\u0027s remove all the AoD specific code and make it so that\nany time the panel is in LP1 or LP2 mode, we make the dimlayer\ntransparent.\n\nChange-Id: If396865ed38abd720ee8f2ed638d7b35ea9ef55f\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "201be83e7b126f44b3aee7b3ef6dbb22ccecbe09", "tree": "bb0e2f3d4cc8fcd2306f0fb913bf62267f54091a", "parents": [ "e108d1f28efbd7e28b6dc1bbc6038ba38019ea5c" ], "author": { "name": "Vishalcj17", "email": "vishalcj@aospa.co", "time": "Fri Jan 27 16:55:37 2023 +0900" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:57 2024 +0530" }, "message": "lahaina-qgki_defconfig: Disable Download mode.\n\nChange-Id: I58a521a608862304232c441b11624c48e06ae8fa\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "e108d1f28efbd7e28b6dc1bbc6038ba38019ea5c", "tree": "a87cace1cabd7c49401f4ac52e88e50f7f44b945", "parents": [ "be91b6d4bc483a9a6fb81193353eb7c49d454d7e" ], "author": { "name": "Sultan Alsawaf", "email": "sultan@kerneltoast.com", "time": "Thu Mar 03 23:04:41 2022 -0800" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:57 2024 +0530" }, "message": "arm64: Enable PCI_LOCKLESS_CONFIG for ARCH_QCOM\n\nThe pci-msm driver has its own locks, so the generic PCI spin locks are\nunneeded on ARCH_QCOM. Remove them by enabling PCI_LOCKLESS_CONFIG.\n\nSigned-off-by: Sultan Alsawaf \u003csultan@kerneltoast.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "be91b6d4bc483a9a6fb81193353eb7c49d454d7e", "tree": "ac9661b85c48e4cd7057d447198a00f38f99e3eb", "parents": [ "93cbc13329fbd79b9998368d4fcfb6e1a5b6e9a3" ], "author": { "name": "Kazuki Hashimoto", "email": "kazukih@tuta.io", "time": "Wed Aug 24 14:00:40 2022 +0900" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:57 2024 +0530" }, "message": "lpm-levels: Remove dev_pm_qos notifier\n\nWhy do we even need this.\n\nSigned-off-by: Kazuki Hashimoto \u003ckazukih@tuta.io\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "93cbc13329fbd79b9998368d4fcfb6e1a5b6e9a3", "tree": "d6a421f32bb70942ac25f6fc701c80e43ae10a07", "parents": [ "35b4e1268b4293f80deb9b23ada65da08f017252" ], "author": { "name": "Kazuki Hashimoto", "email": "kazukih@tuta.io", "time": "Sat Aug 13 15:56:11 2022 +0900" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:57 2024 +0530" }, "message": "lpm-levels: Remove cpu_lock\n\nThese bits of code are never going to run concurrently as confirmed by\nruntime tests.\n\nSigned-off-by: Kazuki Hashimoto \u003ckazukih@tuta.io\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "35b4e1268b4293f80deb9b23ada65da08f017252", "tree": "b84bc5b5c5f482ad576f747a48d4022d5a6cf41e", "parents": [ "9c5e3c7444dd2da3ee3d86e45e4be8ed47843994" ], "author": { "name": "Kazuki Hashimoto", "email": "kazukih@tuta.io", "time": "Sat Aug 13 15:43:22 2022 +0900" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:57 2024 +0530" }, "message": "lpm-levels: Don\u0027t disable rimps timer when it hasn\u0027t been enabled\n\nSigned-off-by: Kazuki Hashimoto \u003ckazukih@tuta.io\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "9c5e3c7444dd2da3ee3d86e45e4be8ed47843994", "tree": "d2a39c604fe587a7fdd58abd493599e99906986b", "parents": [ "15c34c3f9e9490417bec415461344247eac11198" ], "author": { "name": "Kazuki Hashimoto", "email": "kazukih@tuta.io", "time": "Sat Aug 13 12:22:23 2022 +0900" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:57 2024 +0530" }, "message": "lpm-levels: Remove unused code used for debugging\n\nSigned-off-by: Kazuki Hashimoto \u003ckazukih@tuta.io\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "15c34c3f9e9490417bec415461344247eac11198", "tree": "7d5dc821aa53d37c716723a9f462827c3eb0c058", "parents": [ "186da3ece7994d636c6527d8936000fbd62beb47" ], "author": { "name": "Kazuki Hashimoto", "email": "kazukih@tuta.io", "time": "Fri Jun 17 15:46:01 2022 +0900" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:57 2024 +0530" }, "message": "lpm-levels: Ensure that timer pending is read before writing timeout val\n\nIt is possible for the block of code in the spinlock to be reordered,\ncausing RIMPS timer pending to be read after the writes are finished,\ndespite it having to be read prior to the writes. Fix it.\n\nSigned-off-by: Kazuki Hashimoto \u003ckazukih@tuta.io\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "186da3ece7994d636c6527d8936000fbd62beb47", "tree": "9b15ba79f007e00f3feef2d74a605a85a53d7535", "parents": [ "84f148d7ff22dc307298cb5fd72f15134beaa8f9" ], "author": { "name": "Sultan Alsawaf", "email": "sultan@kerneltoast.com", "time": "Thu Mar 03 21:39:30 2022 -0800" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:57 2024 +0530" }, "message": "cpuidle: lpm-levels: Make hrtimers expire in hard IRQ context\n\nThe CPU idle driver\u0027s hrtimers need to be able to wake CPUs up from their\nC-states using a timer interrupt. This doesn\u0027t work if the hrtimers are\ninstead queued into soft IRQ and run from there, so make them expire in\nhard IRQ.\n\nSigned-off-by: Sultan Alsawaf \u003csultan@kerneltoast.com\u003e\nSigned-off-by: Kazuki Hashimoto \u003ckazukih@tuta.io\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "84f148d7ff22dc307298cb5fd72f15134beaa8f9", "tree": "4dfaefc9fa9cdf767a28e840b5c89053fc168813", "parents": [ "6fcd131764b694c028f86a5ebd53492857c06625" ], "author": { "name": "Sultan Alsawaf", "email": "sultan@kerneltoast.com", "time": "Wed May 01 17:54:26 2019 -0700" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:57 2024 +0530" }, "message": "cpuidle: lpm-levels: Allow exit latencies equal to target latencies\n\nThis allows pm_qos votes with, say, 100 us for example to select power\nlevels with exit latencies equal to 100 us. The extra microsecond of\nexit latency doesn\u0027t hurt.\n\nSigned-off-by: Sultan Alsawaf \u003csultan@kerneltoast.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "6fcd131764b694c028f86a5ebd53492857c06625", "tree": "70f8f3dea7636dd87ae59f200dea36aa3a2e5837", "parents": [ "8eb9a399790d127ee6303f81ab99668a1c278743" ], "author": { "name": "Rick Yiu", "email": "rickyiu@google.com", "time": "Mon Jan 30 23:15:56 2023 +0900" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:57 2024 +0530" }, "message": "lahaina-qgki_defconfig: Change UCLAMP_BUCKETS_COUNT to 20\n\nUsing the default setting 5 means the first bucket contains the\nuclamp values from 0 to 19 (in percentage), in this case, if the\nuclamp.min setting of a group is under 20, it will fall into this\nbucket with other groups that have uclamp.min set to 0, which\nincrease the possibility of over boost. By setting the bucket\ncount to 20 will ease this situation, while a uclamp.min greater\nthan 4 will fall into a different bucket.\n\nBug: 170487162\nChange-Id: Ie74349c2434c7739ed1fff9f26df71bb25c8ede4\nSigned-off-by: Rick Yiu \u003crickyiu@google.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "8eb9a399790d127ee6303f81ab99668a1c278743", "tree": "0b10ac6bda0ef340e79fab930b71e3b5d72a67bd", "parents": [ "0ae622f7b0ac6f9bcfa0c73cde79cf2648ac3e84" ], "author": { "name": "Mike Tipton", "email": "mdtipton@codeaurora.org", "time": "Thu Oct 21 20:17:48 2021 -0700" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:57 2024 +0530" }, "message": "cpufreq: qcom-hw: Reduce limits polling delay\n\nIt was suggested that 10ms is an unnecessarily long delay and that 4ms\nis better aligned to our scheduler and may improve performance.\n\nChange-Id: I149c55fe000d058fc6b8b26398816492ce703538\nSigned-off-by: Mike Tipton \u003cmdtipton@codeaurora.org\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "0ae622f7b0ac6f9bcfa0c73cde79cf2648ac3e84", "tree": "76c2f594c1d0cdf2d5ff427d748aa0e9f358c48b", "parents": [ "28c2b32b0a04f103b04e29eb5e2091057af89c9f" ], "author": { "name": "Abhijeet Dharmapurikar", "email": "adharmap@codeaurora.org", "time": "Wed Nov 03 22:05:10 2021 -0700" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:57 2024 +0530" }, "message": "cpufreq: qcom-hw: Switch to non deferrable work\n\nCurrently, when lmh interrupt fires we notify the scheduler about\nthermal pressure. The scheduler reduces the capacity of the cpu(s)\nfor which the interrupt fired, while we requeue our deferrable work.\n\nThis leads to an interesting deadlock, since the cpu is running with\nreduced capacity, the scheduler does not put any task on it,\nextending the idle time and causing it to remain at reduced capacity -\nleading to severe underutilization of the cpu(s).\n\nSwitch to using delayed work instead of deferrable work. This will cause\nus to exit idle until the thermal condition is recovered.\n\nChange-Id: I4c27c9a952ed556336297eb25e815c848b8266eb\nSigned-off-by: Abhijeet Dharmapurikar \u003cadharmap@codeaurora.org\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "28c2b32b0a04f103b04e29eb5e2091057af89c9f", "tree": "a0f5485e7620a96091cc79c65424f0aa5d369c6e", "parents": [ "81c7efbdeeb99b66bf4b580e852261e6ebace379" ], "author": { "name": "Yaroslav Furman", "email": "yaro330@gmail.com", "time": "Mon Jan 10 02:33:47 2022 +0300" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:57 2024 +0530" }, "message": "arm64: lse: Omit LL/SC alternatives patching\n\nOriginal idea by: Danny Lin \u003cdanny@kdrag0n.dev\u003e\nSigned-off-by: Yaroslav Furman \u003cyaro330@gmail.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "81c7efbdeeb99b66bf4b580e852261e6ebace379", "tree": "6788b221da62434ab3b88579c7628dc424584dfa", "parents": [ "bf66a99814dcd448bb1023fbac08530bf0f182d1" ], "author": { "name": "Danny Lin", "email": "danny@kdrag0n.dev", "time": "Wed Nov 18 16:25:17 2020 -0800" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:57 2024 +0530" }, "message": "arm64: lse: Prefetch operands to speed up atomic operations\n\nOn a Kryo 485 CPU (semi-custom Cortex-A76 derivative) in a Snapdragon\n855 (SM8150) SoC, switching from traditional LL/SC atomics to LSE\ncauses LKDTM\u0027s ATOMIC_TIMING test to regress by 2x:\n\nLL/SC ATOMIC_TIMING: 34.14s 34.08s\nLSE ATOMIC_TIMING: 70.84s 71.06s\n\nPrefetching the target operands fixes the regression and makes LSE\nperform better than LSE as expected:\n\nLSE+prfm ATOMIC_TIMING: 21.36s 21.21s\n\n\"dd if\u003d/dev/zero of\u003d/dev/null count\u003d10000000\" also runs faster:\n LL/SC: 3.3 3.2 3.3 s\n LSE: 3.1 3.2 3.2 s\n LSE+p: 2.3 2.3 2.3 s\n\nCommit 0ea366f5e1b6413a6095dce60ea49ae51e468b61 applied the same change\nto LL/SC atomics, but it was never ported to LSE.\n\nSigned-off-by: Danny Lin \u003cdanny@kdrag0n.dev\u003e\n[Kazuki: Port to v5.4]\nSigned-off-by: Kazuki Hashimoto \u003ckazukih@tuta.io\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "bf66a99814dcd448bb1023fbac08530bf0f182d1", "tree": "c524c4ee57a0feb5de10d9e2db060e28b9b18c3c", "parents": [ "19e3e292ee4ec23a9b2278665dd17247a65a2d9a" ], "author": { "name": "Kees Cook", "email": "keescook@chromium.org", "time": "Wed Jan 12 12:22:59 2022 -0800" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:57 2024 +0530" }, "message": "arm64: atomics: lse: Dereference matching size\n\nWhen building with -Warray-bounds, the following warning is generated:\n\nIn file included from ./arch/arm64/include/asm/lse.h:16,\n from ./arch/arm64/include/asm/cmpxchg.h:14,\n from ./arch/arm64/include/asm/atomic.h:16,\n from ./include/linux/atomic.h:7,\n from ./include/asm-generic/bitops/atomic.h:5,\n from ./arch/arm64/include/asm/bitops.h:25,\n from ./include/linux/bitops.h:33,\n from ./include/linux/kernel.h:22,\n from kernel/printk/printk.c:22:\n./arch/arm64/include/asm/atomic_lse.h:247:9: warning: array subscript \u0027long unsigned int[0]\u0027 is partly outside array bounds of \u0027atomic_t[1]\u0027 [-Warray-bounds]\n 247 | asm volatile( \\\n | ^~~\n./arch/arm64/include/asm/atomic_lse.h:266:1: note: in expansion of macro \u0027__CMPXCHG_CASE\u0027\n 266 | __CMPXCHG_CASE(w, , acq_, 32, a, \"memory\")\n | ^~~~~~~~~~~~~~\nkernel/printk/printk.c:3606:17: note: while referencing \u0027printk_cpulock_owner\u0027\n 3606 | static atomic_t printk_cpulock_owner \u003d ATOMIC_INIT(-1);\n | ^~~~~~~~~~~~~~~~~~~~\n\nThis is due to the compiler seeing an unsigned long * cast against\nsomething (atomic_t) that is int sized. Replace the cast with the\nmatching size cast. This results in no change in binary output.\n\nNote that __ll_sc__cmpxchg_case_##name##sz already uses the same\nconstraint:\n\n\t[v] \"+Q\" (*(u##sz *)ptr\n\nWhich is why only the LSE form needs updating and not the\nLL/SC form, so this change is unlikely to be problematic.\n\nCc: Will Deacon \u003cwill@kernel.org\u003e\nCc: Peter Zijlstra \u003cpeterz@infradead.org\u003e\nCc: Boqun Feng \u003cboqun.feng@gmail.com\u003e\nCc: linux-arm-kernel@lists.infradead.org\nAcked-by: Ard Biesheuvel \u003cardb@kernel.org\u003e\nAcked-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nSigned-off-by: Kees Cook \u003ckeescook@chromium.org\u003e\nLink: https://lore.kernel.org/r/20220112202259.3950286-1-keescook@chromium.org\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "19e3e292ee4ec23a9b2278665dd17247a65a2d9a", "tree": "5ec79e74c2b482153f47bd65ebb719d62ff4bfdd", "parents": [ "251202b8de96d2136ba5bd8b59649c532a7ea72a" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Dec 10 15:14:10 2021 +0000" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:57 2024 +0530" }, "message": "arm64: atomics: lse: define RETURN ops in terms of FETCH ops\n\nThe FEAT_LSE atomic instructions include LD* instructions which return\nthe original value of a memory location can be used to directly\nimplement FETCH opertations. Each RETURN op is implemented as a copy of\nthe corresponding FETCH op with a trailing instruction to generate the\nnew value of the memory location. We only directly implement\n*_fetch_add*(), for which we have a trailing `add` instruction.\n\nAs the compiler has no visibility of the `add`, this leads to less than\noptimal code generation when consuming the result.\n\nFor example, the compiler cannot constant-fold the addition into later\noperations, and currently GCC 11.1.0 will compile:\n\n return __lse_atomic_sub_return(1, v) \u003d\u003d 0;\n\nAs:\n\n\tmov w1, #0xffffffff\n\tldaddal w1, w2, [x0]\n\tadd w1, w1, w2\n\tcmp w1, #0x0\n\tcset w0, eq // eq \u003d none\n\tret\n\nThis patch improves this by replacing the `add` with C addition after\nthe inline assembly block, e.g.\n\n\tret +\u003d i;\n\nThis allows the compiler to manipulate `i`. This permits the compiler to\nmerge the `add` and `cmp` for the above, e.g.\n\n\tmov w1, #0xffffffff\n\tldaddal w1, w1, [x0]\n\tcmp w1, #0x1\n\tcset w0, eq // eq \u003d none\n\tret\n\nWith this change the assembly for each RETURN op is identical to the\ncorresponding FETCH op (including barriers and clobbers) so I\u0027ve removed\nthe inline assembly and rewritten each RETURN op in terms of the\ncorresponding FETCH op, e.g.\n\n| static inline void __lse_atomic_add_return(int i, atomic_t *v)\n| {\n| return __lse_atomic_fetch_add(i, v) + i\n| }\n\nThe new construction does not adversely affect the common case, and\nbefore and after this patch GCC 11.1.0 can compile:\n\n\t__lse_atomic_add_return(i, v)\n\nAs:\n\n\tldaddal w0, w2, [x1]\n\tadd w0, w0, w2\n\n... while having the freedom to do better elsewhere.\n\nThis is intended as an optimization and cleanup.\nThere should be no functional change as a result of this patch.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nCc: Boqun Feng \u003cboqun.feng@gmail.com\u003e\nCc: Peter Zijlstra \u003cpeterz@infradead.org\u003e\nCc: Will Deacon \u003cwill@kernel.org\u003e\nAcked-by: Will Deacon \u003cwill@kernel.org\u003e\nAcked-by: Peter Zijlstra (Intel) \u003cpeterz@infradead.org\u003e\nLink: https://lore.kernel.org/r/20211210151410.2782645-6-mark.rutland@arm.com\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "251202b8de96d2136ba5bd8b59649c532a7ea72a", "tree": "69f52b5238e7fe84b2c47d0029f6353cb50583f5", "parents": [ "0dfad7a37ffede5c3feaf07d680aa10484febdfa" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Dec 10 15:14:09 2021 +0000" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:57 2024 +0530" }, "message": "arm64: atomics: lse: improve constraints for simple ops\n\nWe have overly conservative assembly constraints for the basic FEAT_LSE\natomic instructions, and using more accurate and permissive constraints\nwill allow for better code generation.\n\nThe FEAT_LSE basic atomic instructions have come in two forms:\n\n\tLD{op}{order}{size} \u003cRs\u003e, \u003cRt\u003e, [\u003cRn\u003e]\n\tST{op}{order}{size} \u003cRs\u003e, [\u003cRn\u003e]\n\nThe ST* forms are aliases of the LD* forms where:\n\n\tST{op}{order}{size} \u003cRs\u003e, [\u003cRn\u003e]\nIs:\n\tLD{op}{order}{size} \u003cRs\u003e, XZR, [\u003cRn\u003e]\n\nFor either form, both \u003cRs\u003e and \u003cRn\u003e are read but not written back to,\nand \u003cRt\u003e is written with the original value of the memory location.\nWhere (\u003cRt\u003e \u003d\u003d \u003cRs\u003e) or (\u003cRt\u003e \u003d\u003d \u003cRn\u003e), \u003cRt\u003e is written *after* the\nother register value(s) are consumed. There are no UNPREDICTABLE or\nCONSTRAINED UNPREDICTABLE behaviours when any pair of \u003cRs\u003e, \u003cRt\u003e, or\n\u003cRn\u003e are the same register.\n\nOur current inline assembly always uses \u003cRs\u003e \u003d\u003d \u003cRt\u003e, treating this\nregister as both an input and an output (using a \u0027+r\u0027 constraint). This\nforces the compiler to do some unnecessary register shuffling and/or\nredundant value generation.\n\nFor example, the compiler cannot reuse the \u003cRs\u003e value, and currently GCC\n11.1.0 will compile:\n\n\t__lse_atomic_add(1, a);\n\t__lse_atomic_add(1, b);\n\t__lse_atomic_add(1, c);\n\nAs:\n\n\tmov w3, #0x1\n\tmov w4, w3\n\tstadd w4, [x0]\n\tmov w0, w3\n\tstadd w0, [x1]\n\tstadd w3, [x2]\n\nWe can improve this with more accurate constraints, separating \u003cRs\u003e and\n\u003cRt\u003e, where \u003cRs\u003e is an input-only register (\u0027r\u0027), and \u003cRt\u003e is an\noutput-only value (\u0027\u003dr\u0027). As \u003cRt\u003e is written back after \u003cRs\u003e is\nconsumed, it does not need to be earlyclobber (\u0027\u003d\u0026r\u0027), leaving the\ncompiler free to use the same register for both \u003cRs\u003e and \u003cRt\u003e where this\nis desirable.\n\nAt the same time, the redundant \u0027r\u0027 constraint for `v` is removed, as\nthe `+Q` constraint is sufficient.\n\nWith this change, the above example becomes:\n\n\tmov w3, #0x1\n\tstadd w3, [x0]\n\tstadd w3, [x1]\n\tstadd w3, [x2]\n\nI\u0027ve made this change for the non-value-returning and FETCH ops. The\nRETURN ops have a multi-instruction sequence for which we cannot use the\nsame constraints, and a subsequent patch will rewrite hte RETURN ops in\nterms of the FETCH ops, relying on the ability for the compiler to reuse\nthe \u003cRs\u003e value.\n\nThis is intended as an optimization.\nThere should be no functional change as a result of this patch.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nCc: Boqun Feng \u003cboqun.feng@gmail.com\u003e\nCc: Peter Zijlstra \u003cpeterz@infradead.org\u003e\nCc: Will Deacon \u003cwill@kernel.org\u003e\nAcked-by: Will Deacon \u003cwill@kernel.org\u003e\nAcked-by: Peter Zijlstra (Intel) \u003cpeterz@infradead.org\u003e\nLink: https://lore.kernel.org/r/20211210151410.2782645-5-mark.rutland@arm.com\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "0dfad7a37ffede5c3feaf07d680aa10484febdfa", "tree": "81137676ec19ee50fd04f323bd25a79f50bdc00f", "parents": [ "b3688b8934e246fa4a7a3479efc7a59de41c68d8" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Dec 10 15:14:08 2021 +0000" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:57 2024 +0530" }, "message": "arm64: atomics: lse: define ANDs in terms of ANDNOTs\n\nThe FEAT_LSE atomic instructions include atomic bit-clear instructions\n(`ldclr*` and `stclr*`) which can be used to directly implement ANDNOT\noperations. Each AND op is implemented as a copy of the corresponding\nANDNOT op with a leading `mvn` instruction to apply a bitwise NOT to the\n`i` argument.\n\nAs the compiler has no visibility of the `mvn`, this leads to less than\noptimal code generation when generating `i` into a register. For\nexample, __lse_atomic_fetch_and(0xf, v) can be compiled to:\n\n\tmov w1, #0xf\n\tmvn w1, w1\n\tldclral w1, w1, [x2]\n\nThis patch improves this by replacing the `mvn` with NOT in C before the\ninline assembly block, e.g.\n\n\ti \u003d ~i;\n\nThis allows the compiler to generate `i` into a register more optimally,\ne.g.\n\n\tmov w1, #0xfffffff0\n\tldclral w1, w1, [x2]\n\nWith this change the assembly for each AND op is identical to the\ncorresponding ANDNOT op (including barriers and clobbers), so I\u0027ve\nremoved the inline assembly and rewritten each AND op in terms of the\ncorresponding ANDNOT op, e.g.\n\n| static inline void __lse_atomic_and(int i, atomic_t *v)\n| {\n| \treturn __lse_atomic_andnot(~i, v);\n| }\n\nThis is intended as an optimization and cleanup.\nThere should be no functional change as a result of this patch.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nCc: Boqun Feng \u003cboqun.feng@gmail.com\u003e\nCc: Peter Zijlstra \u003cpeterz@infradead.org\u003e\nCc: Will Deacon \u003cwill@kernel.org\u003e\nAcked-by: Will Deacon \u003cwill@kernel.org\u003e\nAcked-by: Peter Zijlstra (Intel) \u003cpeterz@infradead.org\u003e\nLink: https://lore.kernel.org/r/20211210151410.2782645-4-mark.rutland@arm.com\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "b3688b8934e246fa4a7a3479efc7a59de41c68d8", "tree": "213b84bcc7c0c1291ad8716510b3a5cd425d07d8", "parents": [ "0bec54c828e0e2da60a65a644c4a173f60a9d3b7" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Fri Dec 10 15:14:07 2021 +0000" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:57 2024 +0530" }, "message": "arm64: atomics lse: define SUBs in terms of ADDs\n\nThe FEAT_LSE atomic instructions include atomic ADD instructions\n(`stadd*` and `ldadd*`), but do not include atomic SUB instructions, so\nwe must build all of the SUB operations using the ADD instructions. We\nopen-code these today, with each SUB op implemented as a copy of the\ncorresponding ADD op with a leading `neg` instruction in the inline\nassembly to negate the `i` argument.\n\nAs the compiler has no visibility of the `neg`, this leads to less than\noptimal code generation when generating `i` into a register. For\nexample, __les_atomic_fetch_sub(1, v) can be compiled to:\n\n\tmov w1, #0x1\n\tneg w1, w1\n\tldaddal w1, w1, [x2]\n\nThis patch improves this by replacing the `neg` with negation in C\nbefore the inline assembly block, e.g.\n\n\ti \u003d -i;\n\nThis allows the compiler to generate `i` into a register more optimally,\ne.g.\n\n\tmov w1, #0xffffffff\n\tldaddal w1, w1, [x2]\n\nWith this change the assembly for each SUB op is identical to the\ncorresponding ADD op (including barriers and clobbers), so I\u0027ve removed\nthe inline assembly and rewritten each SUB op in terms of the\ncorresponding ADD op, e.g.\n\n| static inline void __lse_atomic_sub(int i, atomic_t *v)\n| {\n| \t__lse_atomic_add(-i, v);\n| }\n\nFor clarity I\u0027ve moved the definition of each SUB op immediately after\nthe corresponding ADD op, and used a single macro to create the RETURN\nforms of both ops.\n\nThis is intended as an optimization and cleanup.\nThere should be no functional change as a result of this patch.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nCc: Boqun Feng \u003cboqun.feng@gmail.com\u003e\nCc: Peter Zijlstra \u003cpeterz@infradead.org\u003e\nCc: Will Deacon \u003cwill@kernel.org\u003e\nAcked-by: Will Deacon \u003cwill@kernel.org\u003e\nAcked-by: Peter Zijlstra (Intel) \u003cpeterz@infradead.org\u003e\nLink: https://lore.kernel.org/r/20211210151410.2782645-3-mark.rutland@arm.com\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "0bec54c828e0e2da60a65a644c4a173f60a9d3b7", "tree": "98c15db2214dfaf5ee6bc93da29a3fe374fc0395", "parents": [ "33aeaf5a3dbba0ebf8086df45cba6cbea4ae95c2" ], "author": { "name": "Kazuki Hashimoto", "email": "kazukih@tuta.io", "time": "Sun Jun 12 23:11:35 2022 +0900" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:57 2024 +0530" }, "message": "arm64: Optimize for LSE atomics\n\nhttps://github.com/kerneltoast/android_kernel_google_floral/commit/2d903dfbedfc4a53475ba914381531c2827cd072\n\nSigned-off-by: Kazuki Hashimoto \u003ckazukih@tuta.io\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "33aeaf5a3dbba0ebf8086df45cba6cbea4ae95c2", "tree": "a2314f7f253c63e24d76f260b5c6370ce318f00e", "parents": [ "8210e6d690e3ad91c25c3a47d1444b93339a2291" ], "author": { "name": "Sultan Alsawaf", "email": "sultan@kerneltoast.com", "time": "Sat Dec 19 00:38:08 2020 -0800" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:57 2024 +0530" }, "message": "arm64: Keep alternative-instruction sections\n\nOtherwise DCE happily discards them and we\u0027re left with a kernel that\ndoesn\u0027t boot.\n\nSigned-off-by: Sultan Alsawaf \u003csultan@kerneltoast.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "8210e6d690e3ad91c25c3a47d1444b93339a2291", "tree": "3f15551e2db0a21db95ea4fcddf38e7f68b234d7", "parents": [ "d0bf31107a73da2721c48ba244a60d21c23d472f" ], "author": { "name": "Arvind Sankar", "email": "nivedita@alum.mit.edu", "time": "Wed Aug 19 10:08:16 2020 -0400" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:56 2024 +0530" }, "message": "lib/string.c: Use freestanding environment\n\ngcc can transform the loop in a naive implementation of memset/memcpy\netc into a call to the function itself. This optimization is enabled by\n-ftree-loop-distribute-patterns.\n\nThis has been the case for a while, but gcc-10.x enables this option at\n-O2 rather than -O3 as in previous versions.\n\nAdd -ffreestanding, which implicitly disables this optimization with\ngcc. It is unclear whether clang performs such optimizations, but\nhopefully it will also not do so in a freestanding environment.\n\nSigned-off-by: Arvind Sankar \u003cnivedita@alum.mit.edu\u003e\nLink: https://gcc.gnu.org/bugzilla/show_bug.cgi?id\u003d56888\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "d0bf31107a73da2721c48ba244a60d21c23d472f", "tree": "8c47afed8ecac8807ff004ecaf214bcc6b4c26f3", "parents": [ "9e8b9b94f1b311f8aae5d2d866b28bff025db41b" ], "author": { "name": "Kevin Bracey", "email": "kevin@bracey.fi", "time": "Tue Jan 18 12:23:50 2022 +0200" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:56 2024 +0530" }, "message": "lib/crc32test: correct printed bytes count\n\ncrc32c_le self test had a stray multiply by two inherited from\nthe crc32_le+crc32_be test loop.\n\nSigned-off-by: Kevin Bracey \u003ckevin@bracey.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "9e8b9b94f1b311f8aae5d2d866b28bff025db41b", "tree": "26b85a7990d2aee92514d74505d061b9fd7cee3f", "parents": [ "0e4fcdd6ab555431b87dfd40a3ed7cd59c728d67" ], "author": { "name": "Kevin Bracey", "email": "kevin@bracey.fi", "time": "Tue Jan 18 12:23:49 2022 +0200" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:56 2024 +0530" }, "message": "lib/crc32: Make crc32_be weak for arch override\n\ncrc32_le and __crc32c_le can be overridden - extend this to crc32_be.\n\nSigned-off-by: Kevin Bracey \u003ckevin@bracey.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "0e4fcdd6ab555431b87dfd40a3ed7cd59c728d67", "tree": "719cc7c4f96976d3acd88f02807e88edc4ee04e0", "parents": [ "66bc189e9ac97b0b5e32330a79fe2c81eabf5337" ], "author": { "name": "Kevin Bracey", "email": "kevin@bracey.fi", "time": "Tue Jan 18 12:23:48 2022 +0200" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:56 2024 +0530" }, "message": "lib/crc32: remove unneeded casts\n\nCasts were added in commit 8f243af42ade (\"sections: fix const sections\nfor crc32 table\") to cope with the tables not being const. They are no\nlonger required since commit f5e38b9284e1 (\"lib: crc32: constify crc32\nlookup table\").\n\nSigned-off-by: Kevin Bracey \u003ckevin@bracey.fi\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "66bc189e9ac97b0b5e32330a79fe2c81eabf5337", "tree": "157a4ea0be82e7fea892d6db65103bb762b13ff7", "parents": [ "f6e036f405f9788367b1f4cb121d61704419ce10" ], "author": { "name": "Alexey Dobriyan", "email": "adobriyan@gmail.com", "time": "Mon Aug 02 23:40:31 2021 +0300" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:56 2024 +0530" }, "message": "isystem: trim/fixup stdarg.h and other headers\n\nDelete/fixup few includes in anticipation of global -isystem compile\noption removal.\n\nNote: crypto/aegis128-neon-inner.c keeps \u003cstddef.h\u003e due to redefinition\nof uintptr_t error (one definition comes from \u003cstddef.h\u003e, another from\n\u003clinux/types.h\u003e).\n\nSigned-off-by: Alexey Dobriyan \u003cadobriyan@gmail.com\u003e\nSigned-off-by: Masahiro Yamada \u003cmasahiroy@kernel.org\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "f6e036f405f9788367b1f4cb121d61704419ce10", "tree": "c86e991acf3517bd760001ed766fbff116565029", "parents": [ "b8d61511378b75e907d3cb5fec3629aa31bab2d4" ], "author": { "name": "Alexey Dobriyan", "email": "adobriyan@gmail.com", "time": "Mon Aug 02 23:40:32 2021 +0300" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:56 2024 +0530" }, "message": "isystem: ship and use stdarg.h\n\nShip minimal stdarg.h (1 type, 4 macros) as \u003clinux/stdarg.h\u003e.\nstdarg.h is the only userspace header commonly used in the kernel.\n\nGPL 2 version of \u003cstdarg.h\u003e can be extracted from\nhttp://archive.debian.org/debian/pool/main/g/gcc-4.2/gcc-4.2_4.2.4.orig.tar.gz\n\nSigned-off-by: Alexey Dobriyan \u003cadobriyan@gmail.com\u003e\nAcked-by: Rafael J. Wysocki \u003crafael.j.wysocki@intel.com\u003e\nAcked-by: Ard Biesheuvel \u003cardb@kernel.org\u003e\nSigned-off-by: Masahiro Yamada \u003cmasahiroy@kernel.org\u003e\nSigned-off-by: Juhyung Park \u003cqkrwngud825@gmail.com\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "b8d61511378b75e907d3cb5fec3629aa31bab2d4", "tree": "a14d65e27e6965f8debf10307b167f965aaad10f", "parents": [ "64474269c8edbcb419c401f8d3fa300a47c6cb40" ], "author": { "name": "Francis Laniel", "email": "laniel_francis@privacyrequired.com", "time": "Tue Dec 15 20:43:50 2020 -0800" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:56 2024 +0530" }, "message": "string.h: add FORTIFY coverage for strscpy()\n\nThe fortified version of strscpy ensures the following before vanilla strscpy\nis called:\n\n1. There is no read overflow because we either size is smaller than\n src length or we shrink size to src length by calling fortified\n strnlen.\n\n2. There is no write overflow because we either failed during\n compilation or at runtime by checking that size is smaller than dest\n size.\n\nLink: https://lkml.kernel.org/r/20201122162451.27551-4-laniel_francis@privacyrequired.com\nSigned-off-by: Francis Laniel \u003claniel_francis@privacyrequired.com\u003e\nAcked-by: Kees Cook \u003ckeescook@chromium.org\u003e\nCc: Daniel Axtens \u003cdja@axtens.net\u003e\nCc: Daniel Micay \u003cdanielmicay@gmail.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "64474269c8edbcb419c401f8d3fa300a47c6cb40", "tree": "c9bdfb46ecb3b41a3c838dbd523a03e73d2d936a", "parents": [ "003785d1c3077c3f12447973d80cc75c85acac76" ], "author": { "name": "Daniel Axtens", "email": "dja@axtens.net", "time": "Tue Dec 15 20:43:44 2020 -0800" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:56 2024 +0530" }, "message": "lib: string.h: detect intra-object overflow in fortified string functions\n\nPatch series \"Fortify strscpy()\", v7.\n\nThis patch implements a fortified version of strscpy() enabled by setting\nCONFIG_FORTIFY_SOURCE\u003dy. The new version ensures the following before\ncalling vanilla strscpy():\n\n1. There is no read overflow because either size is smaller than src\n length or we shrink size to src length by calling fortified strnlen().\n\n2. There is no write overflow because we either failed during\n compilation or at runtime by checking that size is smaller than dest\n size. Note that, if src and dst size cannot be got, the patch defaults\n to call vanilla strscpy().\n\nThe patches adds the following:\n\n1. Implement the fortified version of strscpy().\n\n2. Add a new LKDTM test to ensures the fortified version still returns\n the same value as the vanilla one while panic\u0027ing when there is a write\n overflow.\n\n3. Correct some typos in LKDTM related file.\n\nI based my modifications on top of two patches from Daniel Axtens which\nmodify calls to __builtin_object_size, in fortified string functions, to\nensure the true size of char * are returned and not the surrounding\nstructure size.\n\nAbout performance, I measured the slow down of fortified strscpy(), using\nthe vanilla one as baseline. The hardware I used is an Intel i3 2130 CPU\nclocked at 3.4 GHz. I ran \"Linux 5.10.0-rc4+ SMP PREEMPT\" inside qemu\n3.10 with 4 CPU cores. The following code, called through LKDTM, was used\nas a benchmark:\n\n#define TIMES 10000\n\tchar *src;\n\tchar dst[7];\n\tint i;\n\tktime_t begin;\n\n\tsrc \u003d kstrdup(\"foobar\", GFP_KERNEL);\n\n\tif (src \u003d\u003d NULL)\n\t\treturn;\n\n\tbegin \u003d ktime_get();\n\tfor (i \u003d 0; i \u003c TIMES; i++)\n\t\tstrscpy(dst, src, strlen(src));\n\tpr_info(\"%d fortified strscpy() tooks %lld\", TIMES, ktime_get() - begin);\n\n\tbegin \u003d ktime_get();\n\tfor (i \u003d 0; i \u003c TIMES; i++)\n\t\t__real_strscpy(dst, src, strlen(src));\n\tpr_info(\"%d vanilla strscpy() tooks %lld\", TIMES, ktime_get() - begin);\n\n\tkfree(src);\n\nI called the above code 30 times to compute stats for each version (in ns,\nround to int):\n\n| version | mean | std | median | 95th |\n| --------- | ------- | ------ | ------- | ------- |\n| fortified | 245_069 | 54_657 | 216_230 | 331_122 |\n| vanilla | 172_501 | 70_281 | 143_539 | 219_553 |\n\nOn average, fortified strscpy() is approximately 1.42 times slower than\nvanilla strscpy(). For the 95th percentile, the fortified version is\nabout 1.50 times slower.\n\nSo, clearly the stats are not in favor of fortified strscpy(). But, the\nfortified version loops the string twice (one in strnlen() and another in\nvanilla strscpy()) while the vanilla one only loops once. This can\nexplain why fortified strscpy() is slower than the vanilla one.\n\nThis patch (of 5):\n\nWhen the fortify feature was first introduced in commit 6974f0c4555e\n(\"include/linux/string.h: add the option of fortified string.h\nfunctions\"), Daniel Micay observed:\n\n * It should be possible to optionally use __builtin_object_size(x, 1) for\n some functions (C strings) to detect intra-object overflows (like\n glibc\u0027s _FORTIFY_SOURCE\u003d2), but for now this takes the conservative\n approach to avoid likely compatibility issues.\n\nThis is a case that often cannot be caught by KASAN. Consider:\n\nstruct foo {\n char a[10];\n char b[10];\n}\n\nvoid test() {\n char *msg;\n struct foo foo;\n\n msg \u003d kmalloc(16, GFP_KERNEL);\n strcpy(msg, \"Hello world!!\");\n // this copy overwrites foo.b\n strcpy(foo.a, msg);\n}\n\nThe questionable copy overflows foo.a and writes to foo.b as well. It\ncannot be detected by KASAN. Currently it is also not detected by\nfortify, because strcpy considers __builtin_object_size(x, 0), which\nconsiders the size of the surrounding object (here, struct foo). However,\nif we switch the string functions over to use __builtin_object_size(x, 1),\nthe compiler will measure the size of the closest surrounding subobject\n(here, foo.a), rather than the size of the surrounding object as a whole.\nSee https://gcc.gnu.org/onlinedocs/gcc/Object-Size-Checking.html for more\ninfo.\n\nOnly do this for string functions: we cannot use it on things like memcpy,\nmemmove, memcmp and memchr_inv due to code like this which purposefully\noperates on multiple structure members: (arch/x86/kernel/traps.c)\n\n\t/*\n\t * regs-\u003esp points to the failing IRET frame on the\n\t * ESPFIX64 stack. Copy it to the entry stack. This fills\n\t * in gpregs-\u003ess through gpregs-\u003eip.\n\t *\n\t */\n\tmemmove(\u0026gpregs-\u003eip, (void *)regs-\u003esp, 5*8);\n\nThis change passes an allyesconfig on powerpc and x86, and an x86 kernel\nbuilt with it survives running with syz-stress from syzkaller, so it seems\nsafe so far.\n\nLink: https://lkml.kernel.org/r/20201122162451.27551-1-laniel_francis@privacyrequired.com\nLink: https://lkml.kernel.org/r/20201122162451.27551-2-laniel_francis@privacyrequired.com\nSigned-off-by: Daniel Axtens \u003cdja@axtens.net\u003e\nSigned-off-by: Francis Laniel \u003claniel_francis@privacyrequired.com\u003e\nReviewed-by: Kees Cook \u003ckeescook@chromium.org\u003e\nCc: Daniel Micay \u003cdanielmicay@gmail.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "003785d1c3077c3f12447973d80cc75c85acac76", "tree": "9f140087e7dcf2a66bc9d56a8619cf950110621f", "parents": [ "4392f3b6e9705a68d67f1dc445e625f3b82478c5" ], "author": { "name": "Yury Norov", "email": "yury.norov@gmail.com", "time": "Mon Feb 03 17:37:20 2020 -0800" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:56 2024 +0530" }, "message": "lib/string: add strnchrnul()\n\nPatch series \"lib: rework bitmap_parse\", v5.\n\nSimilarl to the recently revisited bitmap_parselist(), bitmap_parse() is\nineffective and overcomplicated. This series reworks it, aligns its\ninterface with bitmap_parselist() and makes it simpler to use.\n\nThe series also adds a test for the function and fixes usage of it in\ncpumask_parse() according to the new design - drops the calculating of\nlength of an input string.\n\nbitmap_parse() takes the array of numbers to be put into the map in the BE\norder which is reversed to the natural LE order for bitmaps. For example,\nto construct bitmap containing a bit on the position 42, we have to put a\nline \u0027400,0\u0027. Current implementation reads chunk one by one from the\nbeginning (\u0027400\u0027 before \u00270\u0027) and makes bitmap shift after each successful\nparse. It makes the complexity of the whole process as O(n^2). We can do\nit in reverse direction (\u00270\u0027 before \u0027400\u0027) and avoid shifting, but it\nrequires reverse parsing helpers.\n\nThis patch (of 7):\n\nNew function works like strchrnul() with a length limited string.\n\nLink: http://lkml.kernel.org/r/20200102043031.30357-2-yury.norov@gmail.com\nSigned-off-by: Yury Norov \u003cyury.norov@gmail.com\u003e\nReviewed-by: Andy Shevchenko \u003candriy.shevchenko@linux.intel.com\u003e\nCc: Rasmus Villemoes \u003clinux@rasmusvillemoes.dk\u003e\nCc: Amritha Nambiar \u003camritha.nambiar@intel.com\u003e\nCc: Willem de Bruijn \u003cwillemb@google.com\u003e\nCc: Kees Cook \u003ckeescook@chromium.org\u003e\nCc: Matthew Wilcox \u003cwilly@infradead.org\u003e\nCc: \"Tobin C . Harding\" \u003ctobin@kernel.org\u003e\nCc: Will Deacon \u003cwill.deacon@arm.com\u003e\nCc: Miklos Szeredi \u003cmszeredi@redhat.com\u003e\nCc: Vineet Gupta \u003cvineet.gupta1@synopsys.com\u003e\nCc: Chris Wilson \u003cchris@chris-wilson.co.uk\u003e\nCc: Arnaldo Carvalho de Melo \u003cacme@redhat.com\u003e\nCc: Steffen Klassert \u003csteffen.klassert@secunet.com\u003e\nSigned-off-by: Andrew Morton \u003cakpm@linux-foundation.org\u003e\nSigned-off-by: Linus Torvalds \u003ctorvalds@linux-foundation.org\u003e\nSigned-off-by: Pranav Vashi \u003cneobuddy89@gmail.com\u003e\n" }, { "commit": "4392f3b6e9705a68d67f1dc445e625f3b82478c5", "tree": "a57b2e91152470930c842fc16c82028c66e8efc1", "parents": [ "80c9bf578d2b0f9951f3bccdd9e2985f8c20bf59" ], "author": { "name": "James Morse", "email": "james.morse@arm.com", "time": "Thu Jan 27 16:21:27 2022 +0000" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:56 2024 +0530" }, "message": "arm64: insn: Generate 64 bit mask immediates correctly\n\nWhen the insn framework is used to encode an AND/ORR/EOR instruction,\naarch64_encode_immediate() is used to pick the immr imms values.\n\nIf the immediate is a 64bit mask, with bit 63 set, and zeros in any\nof the upper 32 bits, the immr value is incorrectly calculated meaning\nthe wrong mask is generated.\nFor example, 0x8000000000000001 should have an immr of 1, but 32 is used,\nmeaning the resulting mask is 0x0000000300000000.\n\nIt would appear eBPF is unable to hit these cases, as build_insn()\u0027s\nimm value is a s32, so when used with BPF_ALU64, the sign-extended\nu64 immediate would always have all-1s or all-0s in the upper 32 bits.\n\nKVM does not generate a va_mask with any of the top bits set as these\nVA wouldn\u0027t be usable with TTBR0_EL2.\n\nThis happens because the rotation is calculated from fls(~imm), which\ntakes an unsigned int, but the immediate may be 64bit.\n\nUse fls64() so the 64bit mask doesn\u0027t get truncated to a u32.\n\nSigned-off-by: James Morse \u003cjames.morse@arm.com\u003e\nBrown-paper-bag-for: Marc Zyngier \u003cmaz@kernel.org\u003e\nAcked-by: Marc Zyngier \u003cmaz@kernel.org\u003e\nLink: https://lore.kernel.org/r/20220127162127.2391947-4-james.morse@arm.com\nSigned-off-by: Will Deacon \u003cwill@kernel.org\u003e\n" }, { "commit": "80c9bf578d2b0f9951f3bccdd9e2985f8c20bf59", "tree": "e9018b2dc730bf22162bf0edab04fe3f00876733", "parents": [ "3e0c35c76ddb7fe39cac5590fec5a4584ead6a5c" ], "author": { "name": "Kevin Bracey", "email": "kevin@bracey.fi", "time": "Tue Jan 18 12:23:51 2022 +0200" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:56 2024 +0530" }, "message": "arm64: lib: accelerate crc32_be\n\nIt makes no sense to leave crc32_be using the generic code while we\nonly accelerate the little-endian ops.\n\nEven though the big-endian form doesn\u0027t fit as smoothly into the arm64,\nwe can speed it up and avoid hitting the D cache.\n\nTested on Cortex-A53. Without acceleration:\n\n crc32: CRC_LE_BITS \u003d 64, CRC_BE BITS \u003d 64\n crc32: self tests passed, processed 225944 bytes in 192240 nsec\n crc32c: CRC_LE_BITS \u003d 64\n crc32c: self tests passed, processed 112972 bytes in 21360 nsec\n\nWith acceleration:\n\n crc32: CRC_LE_BITS \u003d 64, CRC_BE BITS \u003d 64\n crc32: self tests passed, processed 225944 bytes in 53480 nsec\n crc32c: CRC_LE_BITS \u003d 64\n crc32c: self tests passed, processed 112972 bytes in 21480 nsec\n\nSigned-off-by: Kevin Bracey \u003ckevin@bracey.fi\u003e\nTested-by: Ard Biesheuvel \u003cardb@kernel.org\u003e\nReviewed-by: Ard Biesheuvel \u003cardb@kernel.org\u003e\nAcked-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "3e0c35c76ddb7fe39cac5590fec5a4584ead6a5c", "tree": "7a8acfdd529ca2e602bb61e8f71ef22cfd0d99ee", "parents": [ "64142b3e6b8b90077336807f99d5b2c0df769dbb" ], "author": { "name": "Reiji Watanabe", "email": "reijiw@google.com", "time": "Sun Dec 05 16:47:35 2021 -0800" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:56 2024 +0530" }, "message": "arm64: clear_page() shouldn\u0027t use DC ZVA when DCZID_EL0.DZP \u003d\u003d 1\n\nCurrently, clear_page() uses DC ZVA instruction unconditionally. But it\nshould make sure that DCZID_EL0.DZP, which indicates whether or not use\nof DC ZVA instruction is prohibited, is zero when using the instruction.\nUse STNP instead when DCZID_EL0.DZP \u003d\u003d 1.\n\nFixes: f27bb139c387 (\"arm64: Miscellaneous library functions\")\nSigned-off-by: Reiji Watanabe \u003creijiw@google.com\u003e\nReviewed-by: Robin Murphy \u003crobin.murphy@arm.com\u003e\nLink: https://lore.kernel.org/r/20211206004736.1520989-2-reijiw@google.com\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\n" }, { "commit": "64142b3e6b8b90077336807f99d5b2c0df769dbb", "tree": "9d62367fc26899b17b719b5272820ac5af2e457b", "parents": [ "1eaefc706a25ecf3f2f54aeb6f4b79bfd0dfacee" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Oct 19 17:02:09 2021 +0100" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:56 2024 +0530" }, "message": "arm64: lib: __arch_copy_to_user(): fold fixups into body\n\nLike other functions, __arch_copy_to_user() places its exception fixups\nin the `.fixup` section without any clear association with\n__arch_copy_to_user() itself. If we backtrace the fixup code, it will be\nsymbolized as an offset from the nearest prior symbol, which happens to\nbe `__entry_tramp_text_end`. Further, since the PC adjustment for the\nfixup is akin to a direct branch rather than a function call,\n__arch_copy_to_user() itself will be missing from the backtrace.\n\nThis is confusing and hinders debugging. In general this pattern will\nalso be problematic for CONFIG_LIVEPATCH, since fixups often return to\ntheir associated function, but this isn\u0027t accurately captured in the\nstacktrace.\n\nTo solve these issues for assembly functions, we must move fixups into\nthe body of the functions themselves, after the usual fast-path returns.\nThis patch does so for __arch_copy_to_user().\n\nInline assembly will be dealt with in subsequent patches.\n\nOther than the improved backtracing, there should be no functional\nchange as a result of this patch.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nAcked-by: Robin Murphy \u003crobin.murphy@arm.com\u003e\nReviewed-by: Ard Biesheuvel \u003cardb@kernel.org\u003e\nCc: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nCc: James Morse \u003cjames.morse@arm.com\u003e\nCc: Mark Brown \u003cbroonie@kernel.org\u003e\nCc: Will Deacon \u003cwill@kernel.org\u003e\nLink: https://lore.kernel.org/r/20211019160219.5202-4-mark.rutland@arm.com\nSigned-off-by: Will Deacon \u003cwill@kernel.org\u003e\n" }, { "commit": "1eaefc706a25ecf3f2f54aeb6f4b79bfd0dfacee", "tree": "0f43052f84f1809890946af6baea7c966dc01c97", "parents": [ "725bc29db7659f34dcc79ef47b9439b2e82e624a" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Oct 19 17:02:08 2021 +0100" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:56 2024 +0530" }, "message": "arm64: lib: __arch_copy_from_user(): fold fixups into body\n\nLike other functions, __arch_copy_from_user() places its exception\nfixups in the `.fixup` section without any clear association with\n__arch_copy_from_user() itself. If we backtrace the fixup code, it will\nbe symbolized as an offset from the nearest prior symbol, which happens\nto be `__entry_tramp_text_end`. Further, since the PC adjustment for the\nfixup is akin to a direct branch rather than a function call,\n__arch_copy_from_user() itself will be missing from the backtrace.\n\nThis is confusing and hinders debugging. In general this pattern will\nalso be problematic for CONFIG_LIVEPATCH, since fixups often return to\ntheir associated function, but this isn\u0027t accurately captured in the\nstacktrace.\n\nTo solve these issues for assembly functions, we must move fixups into\nthe body of the functions themselves, after the usual fast-path returns.\nThis patch does so for __arch_copy_from_user().\n\nInline assembly will be dealt with in subsequent patches.\n\nOther than the improved backtracing, there should be no functional\nchange as a result of this patch.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nAcked-by: Robin Murphy \u003crobin.murphy@arm.com\u003e\nReviewed-by: Ard Biesheuvel \u003cardb@kernel.org\u003e\nCc: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nCc: James Morse \u003cjames.morse@arm.com\u003e\nCc: Mark Brown \u003cbroonie@kernel.org\u003e\nCc: Will Deacon \u003cwill@kernel.org\u003e\nLink: https://lore.kernel.org/r/20211019160219.5202-3-mark.rutland@arm.com\nSigned-off-by: Will Deacon \u003cwill@kernel.org\u003e\n" }, { "commit": "725bc29db7659f34dcc79ef47b9439b2e82e624a", "tree": "ea21fae947f416e2717836d1fc34f16716c773cc", "parents": [ "5e80b21669df59d4031bae0c7d067851ca30c43d" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Tue Oct 19 17:02:07 2021 +0100" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:56 2024 +0530" }, "message": "arm64: lib: __arch_clear_user(): fold fixups into body\n\nLike other functions, __arch_clear_user() places its exception fixups in\nthe `.fixup` section without any clear association with\n__arch_clear_user() itself. If we backtrace the fixup code, it will be\nsymbolized as an offset from the nearest prior symbol, which happens to\nbe `__entry_tramp_text_end`. Further, since the PC adjustment for the\nfixup is akin to a direct branch rather than a function call,\n__arch_clear_user() itself will be missing from the backtrace.\n\nThis is confusing and hinders debugging. In general this pattern will\nalso be problematic for CONFIG_LIVEPATCH, since fixups often return to\ntheir associated function, but this isn\u0027t accurately captured in the\nstacktrace.\n\nTo solve these issues for assembly functions, we must move fixups into\nthe body of the functions themselves, after the usual fast-path returns.\nThis patch does so for __arch_clear_user().\n\nInline assembly will be dealt with in subsequent patches.\n\nOther than the improved backtracing, there should be no functional\nchange as a result of this patch.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nAcked-by: Robin Murphy \u003crobin.murphy@arm.com\u003e\nReviewed-by: Ard Biesheuvel \u003cardb@kernel.org\u003e\nCc: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nCc: James Morse \u003cjames.morse@arm.com\u003e\nCc: Mark Brown \u003cbroonie@kernel.org\u003e\nCc: Will Deacon \u003cwill@kernel.org\u003e\nLink: https://lore.kernel.org/r/20211019160219.5202-2-mark.rutland@arm.com\nSigned-off-by: Will Deacon \u003cwill@kernel.org\u003e\n" }, { "commit": "5e80b21669df59d4031bae0c7d067851ca30c43d", "tree": "c55fdd7d6637a5e64363615477c9aa0a96e0ad16", "parents": [ "68f86df55cda2f822d89d2a5f4f4da08f3cc50da" ], "author": { "name": "Alexey Dobriyan", "email": "adobriyan@gmail.com", "time": "Mon Aug 02 23:43:15 2021 +0300" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:56 2024 +0530" }, "message": "isystem: delete global -isystem compile option\n\nFurther isolate kernel from userspace, prevent accidental inclusion of\nundesireable headers, mainly float.h and stdatomic.h.\n\nnds32 keeps -isystem globally due to intrinsics used in entrenched header.\n\n-isystem is selectively reenabled for some files, again, for intrinsics.\n\nCompile tested on:\n\nhexagon-defconfig hexagon-allmodconfig\nalpha-allmodconfig alpha-allnoconfig alpha-defconfig arm64-allmodconfig\narm64-allnoconfig arm64-defconfig arm-am200epdkit arm-aspeed_g4\narm-aspeed_g5 arm-assabet arm-at91_dt arm-axm55xx arm-badge4 arm-bcm2835\narm-cerfcube arm-clps711x arm-cm_x300 arm-cns3420vb arm-colibri_pxa270\narm-colibri_pxa300 arm-collie arm-corgi arm-davinci_all arm-dove\narm-ep93xx arm-eseries_pxa arm-exynos arm-ezx arm-footbridge arm-gemini\narm-h3600 arm-h5000 arm-hackkit arm-hisi arm-imote2 arm-imx_v4_v5\narm-imx_v6_v7 arm-integrator arm-iop32x arm-ixp4xx arm-jornada720\narm-keystone arm-lart arm-lpc18xx arm-lpc32xx arm-lpd270 arm-lubbock\narm-magician arm-mainstone arm-milbeaut_m10v arm-mini2440 arm-mmp2\narm-moxart arm-mps2 arm-multi_v4t arm-multi_v5 arm-multi_v7 arm-mv78xx0\narm-mvebu_v5 arm-mvebu_v7 arm-mxs arm-neponset arm-netwinder arm-nhk8815\narm-omap1 arm-omap2plus arm-orion5x arm-oxnas_v6 arm-palmz72 arm-pcm027\narm-pleb arm-pxa arm-pxa168 arm-pxa255-idp arm-pxa3xx arm-pxa910\narm-qcom arm-realview arm-rpc arm-s3c2410 arm-s3c6400 arm-s5pv210\narm-sama5 arm-shannon arm-shmobile arm-simpad arm-socfpga arm-spear13xx\narm-spear3xx arm-spear6xx arm-spitz arm-stm32 arm-sunxi arm-tct_hammer\narm-tegra arm-trizeps4 arm-u8500 arm-versatile arm-vexpress arm-vf610m4\narm-viper arm-vt8500_v6_v7 arm-xcep arm-zeus csky-allmodconfig\ncsky-allnoconfig csky-defconfig h8300-edosk2674 h8300-h8300h-sim\nh8300-h8s-sim i386-allmodconfig i386-allnoconfig i386-defconfig\nia64-allmodconfig ia64-allnoconfig ia64-bigsur ia64-generic ia64-gensparse\nia64-tiger ia64-zx1 m68k-amcore m68k-amiga m68k-apollo m68k-atari\nm68k-bvme6000 m68k-hp300 m68k-m5208evb m68k-m5249evb m68k-m5272c3\nm68k-m5275evb m68k-m5307c3 m68k-m5407c3 m68k-m5475evb m68k-mac\nm68k-multi m68k-mvme147 m68k-mvme16x m68k-q40 m68k-stmark2 m68k-sun3\nm68k-sun3x microblaze-allmodconfig microblaze-allnoconfig microblaze-mmu\nmips-ar7 mips-ath25 mips-ath79 mips-bcm47xx mips-bcm63xx mips-bigsur\nmips-bmips_be mips-bmips_stb mips-capcella mips-cavium_octeon mips-ci20\nmips-cobalt mips-cu1000-neo mips-cu1830-neo mips-db1xxx mips-decstation\nmips-decstation_64 mips-decstation_r4k mips-e55 mips-fuloong2e\nmips-gcw0 mips-generic mips-gpr mips-ip22 mips-ip27 mips-ip28 mips-ip32\nmips-jazz mips-jmr3927 mips-lemote2f mips-loongson1b mips-loongson1c\nmips-loongson2k mips-loongson3 mips-malta mips-maltaaprp mips-malta_kvm\nmips-malta_qemu_32r6 mips-maltasmvp mips-maltasmvp_eva mips-maltaup\nmips-maltaup_xpa mips-mpc30x mips-mtx1 mips-nlm_xlp mips-nlm_xlr\nmips-omega2p mips-pic32mzda mips-pistachio mips-qi_lb60 mips-rb532\nmips-rbtx49xx mips-rm200 mips-rs90 mips-rt305x mips-sb1250_swarm\nmips-tb0219 mips-tb0226 mips-tb0287 mips-vocore2 mips-workpad mips-xway\nnds32-allmodconfig nds32-allnoconfig nds32-defconfig nios2-10m50\nnios2-3c120 nios2-allmodconfig nios2-allnoconfig openrisc-allmodconfig\nopenrisc-allnoconfig openrisc-or1klitex openrisc-or1ksim\nopenrisc-simple_smp parisc-allnoconfig parisc-generic-32bit\nparisc-generic-64bit powerpc-acadia powerpc-adder875 powerpc-akebono\npowerpc-amigaone powerpc-arches powerpc-asp8347 powerpc-bamboo\npowerpc-bluestone powerpc-canyonlands powerpc-cell powerpc-chrp32\npowerpc-cm5200 powerpc-currituck powerpc-ebony powerpc-eiger\npowerpc-ep8248e powerpc-ep88xc powerpc-fsp2 powerpc-g5 powerpc-gamecube\npowerpc-ge_imp3a powerpc-holly powerpc-icon powerpc-iss476-smp\npowerpc-katmai powerpc-kilauea powerpc-klondike powerpc-kmeter1\npowerpc-ksi8560 powerpc-linkstation powerpc-lite5200b powerpc-makalu\npowerpc-maple powerpc-mgcoge powerpc-microwatt powerpc-motionpro\npowerpc-mpc512x powerpc-mpc5200 powerpc-mpc7448_hpc2 powerpc-mpc8272_ads\npowerpc-mpc8313_rdb powerpc-mpc8315_rdb powerpc-mpc832x_mds\npowerpc-mpc832x_rdb powerpc-mpc834x_itx powerpc-mpc834x_itxgp\npowerpc-mpc834x_mds powerpc-mpc836x_mds powerpc-mpc836x_rdk\npowerpc-mpc837x_mds powerpc-mpc837x_rdb powerpc-mpc83xx\npowerpc-mpc8540_ads powerpc-mpc8560_ads powerpc-mpc85xx_cds\npowerpc-mpc866_ads powerpc-mpc885_ads powerpc-mvme5100 powerpc-obs600\npowerpc-pasemi powerpc-pcm030 powerpc-pmac32 powerpc-powernv\npowerpc-ppa8548 powerpc-ppc40x powerpc-ppc44x powerpc-ppc64\npowerpc-ppc64e powerpc-ppc6xx powerpc-pq2fads powerpc-ps3\npowerpc-pseries powerpc-rainier powerpc-redwood powerpc-sam440ep\npowerpc-sbc8548 powerpc-sequoia powerpc-skiroot powerpc-socrates\npowerpc-storcenter powerpc-stx_gp3 powerpc-taishan powerpc-tqm5200\npowerpc-tqm8540 powerpc-tqm8541 powerpc-tqm8548 powerpc-tqm8555\npowerpc-tqm8560 powerpc-tqm8xx powerpc-walnut powerpc-warp powerpc-wii\npowerpc-xes_mpc85xx riscv-allmodconfig riscv-allnoconfig riscv-nommu_k210\nriscv-nommu_k210_sdcard riscv-nommu_virt riscv-rv32 s390-allmodconfig\ns390-allnoconfig s390-debug s390-zfcpdump sh-ap325rxa sh-apsh4a3a\nsh-apsh4ad0a sh-dreamcast sh-ecovec24 sh-ecovec24-romimage sh-edosk7705\nsh-edosk7760 sh-espt sh-hp6xx sh-j2 sh-kfr2r09 sh-kfr2r09-romimage\nsh-landisk sh-lboxre2 sh-magicpanelr2 sh-microdev sh-migor sh-polaris\nsh-r7780mp sh-r7785rp sh-rsk7201 sh-rsk7203 sh-rsk7264 sh-rsk7269\nsh-rts7751r2d1 sh-rts7751r2dplus sh-sdk7780 sh-sdk7786 sh-se7206 sh-se7343\nsh-se7619 sh-se7705 sh-se7712 sh-se7721 sh-se7722 sh-se7724 sh-se7750\nsh-se7751 sh-se7780 sh-secureedge5410 sh-sh03 sh-sh2007 sh-sh7710voipgw\nsh-sh7724_generic sh-sh7757lcr sh-sh7763rdp sh-sh7770_generic sh-sh7785lcr\nsh-sh7785lcr_32bit sh-shmin sh-shx3 sh-titan sh-ul2 sh-urquell\nsparc-allmodconfig sparc-allnoconfig sparc-sparc32 sparc-sparc64\num-i386-allmodconfig um-i386-allnoconfig um-i386-defconfig\num-x86_64-allmodconfig um-x86_64-allnoconfig x86_64-allmodconfig\nx86_64-allnoconfig x86_64-defconfig xtensa-allmodconfig xtensa-allnoconfig\nxtensa-audio_kc705 xtensa-cadence_csp xtensa-common xtensa-generic_kc705\nxtensa-iss xtensa-nommu_kc705 xtensa-smp_lx200 xtensa-virt\nxtensa-xip_kc705\n\nTested-by: Nathan Chancellor \u003cnathan@kernel.org\u003e # build (hexagon)\nSigned-off-by: Alexey Dobriyan \u003cadobriyan@gmail.com\u003e\nAcked-by: Ard Biesheuvel \u003cardb@kernel.org\u003e\nSigned-off-by: Masahiro Yamada \u003cmasahiroy@kernel.org\u003e\nSigned-off-by: Juhyung Park \u003cqkrwngud825@gmail.com\u003e\n" }, { "commit": "68f86df55cda2f822d89d2a5f4f4da08f3cc50da", "tree": "9e382011efbf5cef639b00db831486017f33d0d0", "parents": [ "f7870b49d755b228f5ab34b426ec88ca7af2e768" ], "author": { "name": "Jason Wang", "email": "wangborong@cdjrlc.com", "time": "Mon Jul 26 20:29:07 2021 +0800" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:56 2024 +0530" }, "message": "arm64: use __func__ to get function name in pr_err\n\nPrefer using \u0027\"%s...\", __func__\u0027 to get current function\u0027s name in\na debug message.\n\nSigned-off-by: Jason Wang \u003cwangborong@cdjrlc.com\u003e\nAcked-by: Will Deacon \u003cwill@kernel.org\u003e\nLink: https://lore.kernel.org/r/20210726122907.51529-1-wangborong@cdjrlc.com\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\n" }, { "commit": "f7870b49d755b228f5ab34b426ec88ca7af2e768", "tree": "f668c962ef6ae836d9ae21b0cbf7c5779c032008", "parents": [ "a2f71a3141fa2bee6d724036ebc8a2b675a1099f" ], "author": { "name": "Robin Murphy", "email": "robin.murphy@arm.com", "time": "Mon Jul 12 15:27:46 2021 +0100" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:56 2024 +0530" }, "message": "arm64: Avoid premature usercopy failure\n\nAl reminds us that the usercopy API must only return complete failure\nif absolutely nothing could be copied. Currently, if userspace does\nsomething silly like giving us an unaligned pointer to Device memory,\nor a size which overruns MTE tag bounds, we may fail to honour that\nrequirement when faulting on a multi-byte access even though a smaller\naccess could have succeeded.\n\nAdd a mitigation to the fixup routines to fall back to a single-byte\ncopy if we faulted on a larger access before anything has been written\nto the destination, to guarantee making *some* forward progress. We\nneedn\u0027t be too concerned about the overall performance since this should\nonly occur when callers are doing something a bit dodgy in the first\nplace. Particularly broken userspace might still be able to trick\ngeneric_perform_write() into an infinite loop by targeting write() at\nan mmap() of some read-only device register where the fault-in load\nsucceeds but any store synchronously aborts such that copy_to_user() is\ngenuinely unable to make progress, but, well, don\u0027t do that...\n\nCC: stable@vger.kernel.org\nReported-by: Chen Huang \u003cchenhuang5@huawei.com\u003e\nSuggested-by: Al Viro \u003cviro@zeniv.linux.org.uk\u003e\nReviewed-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\nSigned-off-by: Robin Murphy \u003crobin.murphy@arm.com\u003e\nLink: https://lore.kernel.org/r/dc03d5c675731a1f24a62417dba5429ad744234e.1626098433.git.robin.murphy@arm.com\nSigned-off-by: Will Deacon \u003cwill@kernel.org\u003e\n" }, { "commit": "a2f71a3141fa2bee6d724036ebc8a2b675a1099f", "tree": "c153b060bb5c75f67816d72141e957b6d1551c3f", "parents": [ "d97365da7ed526b08f767b228c9e3ee34903899c" ], "author": { "name": "Will Deacon", "email": "will@kernel.org", "time": "Fri Mar 19 10:01:09 2021 +0000" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:56 2024 +0530" }, "message": "arm64: lib: Annotate {clear, copy}_page() as position-independent\n\nclear_page() and copy_page() are suitable for use outside of the kernel\naddress space, so annotate them as position-independent code.\n\nSigned-off-by: Will Deacon \u003cwill@kernel.org\u003e\nSigned-off-by: Quentin Perret \u003cqperret@google.com\u003e\nSigned-off-by: Marc Zyngier \u003cmaz@kernel.org\u003e\nLink: https://lore.kernel.org/r/20210319100146.1149909-2-qperret@google.com\n" }, { "commit": "d97365da7ed526b08f767b228c9e3ee34903899c", "tree": "6df365403295b85a3577ae5c0db3aa8cff209d83", "parents": [ "5c20e4ea8ecddb27ec3600c6f3042c52fd99d497" ], "author": { "name": "Mark Rutland", "email": "mark.rutland@arm.com", "time": "Wed Dec 02 13:15:51 2020 +0000" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:56 2024 +0530" }, "message": "arm64: uaccess: simplify __copy_user_flushcache()\n\nCurrently __copy_user_flushcache() open-codes raw_copy_from_user(), and\ndoesn\u0027t use uaccess_mask_ptr() on the user address. Let\u0027s have it call\nraw_copy_from_user(), which is both a simplification and ensures that\nuser pointers are masked under speculation.\n\nThere should be no functional change as a result of this patch.\n\nSigned-off-by: Mark Rutland \u003cmark.rutland@arm.com\u003e\nReviewed-by: Robin Murphy \u003crobin.murphy@arm.com\u003e\nCc: Christoph Hellwig \u003chch@lst.de\u003e\nCc: Will Deacon \u003cwill@kernel.org\u003e\nLink: https://lore.kernel.org/r/20201202131558.39270-6-mark.rutland@arm.com\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\n" }, { "commit": "5c20e4ea8ecddb27ec3600c6f3042c52fd99d497", "tree": "25431b4a123ed503d51923ee791e113c0fa01b3d", "parents": [ "9c009c1d0c5478c33f246cf17bee5ee8b0c0cdc5" ], "author": { "name": "Ard Biesheuvel", "email": "ardb@kernel.org", "time": "Sat Feb 05 16:23:45 2022 +0100" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:56 2024 +0530" }, "message": "lib/xor: make xor prototypes more friendly to compiler vectorization\n\nModern compilers are perfectly capable of extracting parallelism from\nthe XOR routines, provided that the prototypes reflect the nature of the\ninput accurately, in particular, the fact that the input vectors are\nexpected not to overlap. This is not documented explicitly, but is\nimplied by the interchangeability of the various C routines, some of\nwhich use temporary variables while others don\u0027t: this means that these\nroutines only behave identically for non-overlapping inputs.\n\nSo let\u0027s decorate these input vectors with the __restrict modifier,\nwhich informs the compiler that there is no overlap. While at it, make\nthe input-only vectors pointer-to-const as well.\n\nTested-by: Nathan Chancellor \u003cnathan@kernel.org\u003e\nSigned-off-by: Ard Biesheuvel \u003cardb@kernel.org\u003e\nReviewed-by: Nick Desaulniers \u003cndesaulniers@google.com\u003e\nLink: https://github.com/ClangBuiltLinux/linux/issues/563\nSigned-off-by: Herbert Xu \u003cherbert@gondor.apana.org.au\u003e\n" }, { "commit": "9c009c1d0c5478c33f246cf17bee5ee8b0c0cdc5", "tree": "96c8de50999075c5ad356a3c92b8e2258d6704ea", "parents": [ "e81e051438f4107c7f578fdffd3a72dc976512fb" ], "author": { "name": "Ard Biesheuvel", "email": "ardb@kernel.org", "time": "Mon Dec 13 15:02:52 2021 +0100" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:56 2024 +0530" }, "message": "arm64/xor: use EOR3 instructions when available\n\nUse the EOR3 instruction to implement xor_blocks() if the instruction is\navailable, which is the case if the CPU implements the SHA-3 extension.\nThis is about 20% faster on Apple M1 when using the 5-way version.\n\nSigned-off-by: Ard Biesheuvel \u003cardb@kernel.org\u003e\nLink: https://lore.kernel.org/r/20211213140252.2856053-1-ardb@kernel.org\nSigned-off-by: Catalin Marinas \u003ccatalin.marinas@arm.com\u003e\n" }, { "commit": "e81e051438f4107c7f578fdffd3a72dc976512fb", "tree": "7f9410e295f5cf7d6edd4c5fcb3888e8e52d5326", "parents": [ "f14074e53a6188f645efe4a06d718c5c5f6b186f" ], "author": { "name": "Will Deacon", "email": "will@kernel.org", "time": "Tue Apr 14 22:22:47 2020 +0100" }, "committer": { "name": "Pranav Vashi", "email": "neobuddy89@gmail.com", "time": "Mon Oct 21 21:54:55 2024 +0530" }, "message": "arm64: csum: Disable KASAN for do_csum()\n\ndo_csum() over-reads the source buffer and therefore abuses\nREAD_ONCE_NOCHECK() to avoid tripping up KASAN. In preparation for\nREAD_ONCE_NOCHECK() becoming a macro, and therefore losing its\n\u0027__no_sanitize_address\u0027 annotation, just annotate do_csum() explicitly\nand fall back to normal loads.\n\nCc: Mark Rutland \u003cmark.rutland@arm.com\u003e\nCc: Robin Murphy \u003crobin.murphy@arm.com\u003e\nSigned-off-by: Will Deacon \u003cwill@kernel.org\u003e\n" } ], "next": "f14074e53a6188f645efe4a06d718c5c5f6b186f" }